Fix reversed bit issue in DCMX mask for "xvtstdcdp" and "xvtstdcsp" P9 implementation

[NeHuang]

Summary

Did experiments on power 9 machine, checked the outputs for NaN & Infinity+ cases with corresponding DCMX bit set. Confirmed the DCMX mask bit for NaN and infinity+ are reversely set, which is not consistent with the document description.

Fixed the issue and created test cases to cover the two cases.

[NeHuang]

Ping..

[Yi-Hong.Lyu]

The implementation change seems reasonable. I encode the instruction manually and it is correct. LGTM.

[stefanp]

LGTM

[amyk]

Looks good, thank you for fixing and adding the test case.

[nemanjai]

@stefanp Victor doesn't have commit access yet. Can you commit this for him?

[NeHuang]

Thanks all for the review!

[stefanp]

@nemanjai
I will commit this for Victor.

llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td

class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
   bits<6> XB;
 
   let Pattern = pattern;
 
   let Inst{6-10}  = XT{4-0};
   let Inst{11-15} = DCMX{4-0};
   let Inst{16-20} = XB{4-0};
   let Inst{21-24} = xo1;
-  let Inst{25}    = DCMX{5};
+  let Inst{25}    = DCMX{6};
   let Inst{26-28} = xo2;
-  let Inst{29}    = DCMX{6};
+  let Inst{29}    = DCMX{5};
   let Inst{30}    = XB{5};
   let Inst{31}    = XT{5};
 }
 
 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;

llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt

 # CHECK: mtvsrws 34, 3
 0x7c 0x43 0x03 0x27
 
 # CHECK: mtvsrdd 34, 3, 12
 0x7c 0x43 0x63 0x67
 
 # CHECK: mfvsrld 3, 34
 0x7c 0x43 0x02 0x67
+
+# CHECK: xvtstdcdp 63, 63, 65
+0xf3 0xe1 0xff 0xeb
+
+# CHECK: xvtstdcsp 63, 63, 34
+0xf3 0xe2 0xfe 0xaf

llvm/trunk/test/MC/PowerPC/vsx.s

 
 # CHECK-BE: mtvsrdd 34, 3, 12                  # encoding: [0x7c,0x43,0x63,0x67]
 # CHECK-LE: mtvsrdd 34, 3, 12                  # encoding: [0x67,0x63,0x43,0x7c]
             mtvsrdd 34, 3, 12
 
 # CHECK-BE: mfvsrld 3, 34                      # encoding: [0x7c,0x43,0x02,0x67]
 # CHECK-LE: mfvsrld 3, 34                      # encoding: [0x67,0x02,0x43,0x7c]
             mfvsrld 3, 34
+
+# CHECK-BE: xvtstdcdp 63, 63, 65               # encoding: [0xf3,0xe1,0xff,0xeb]
+# CHECK-LE: xvtstdcdp 63, 63, 65               # encoding: [0xeb,0xff,0xe1,0xf3]
+            xvtstdcdp 63, 63, 65
+# CHECK-BE: xvtstdcsp 63, 63, 34               # encoding: [0xf3,0xe2,0xfe,0xaf]
+# CHECK-LE: xvtstdcsp 63, 63, 34               # encoding: [0xaf,0xfe,0xe2,0xf3]
+            xvtstdcsp 63, 63, 34