[MIPS MSA] Avoid some DAG combines for vector shifts

[Petar.Avramovic]

Summary

DAG combiner combines two shifts (for different shift amounts) into
shift + and with bitmask. Vector bitmasks require either quite a few
instructions or extra constant pool space. Avoid such combines as
leaving two vector shifts as they are produces better end results.

[RKSimon]

Intel targets tend to only accept vector shifts on Port0, while vector logic can use Port0/1/5 - not sure how much of an issue that would be @craig.topper ? Some AMD targets are almost as bad while others (Jaguar) can issue vector immediate shifts to any vector integer pipe.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6694

A comment would be nice

test/CodeGen/X86/combine-shl.ll

574

This comment needs adjusting.

[craig.topper]

I think only Skylake CPUs have more than 1 shift execution port if I remember right. I'm not sure what the impact would be. Can we limit this to MIPS MSA using the TLI.shouldFoldShiftPairToMask hook? Not sure why the call to that hook is made before we know the other value is a constant.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6689

Doesn't this have the same issue?

[Petar.Avramovic]

Restrict changes to MIPS backend only.
Use shouldFoldShiftPairToMask to avoid all attempts
to combine shifts if operands have vector type.

[atanasyan]

LGTM

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
       TLI.shouldFoldShiftPairToMask(N, Level)) {
     if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       uint64_t c1 = N0C1->getZExtValue();
       if (c1 < OpSizeInBits) {
         uint64_t c2 = N1C->getZExtValue();
         APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
         SDValue Shift;
         if (c2 > c1) {
           Mask <<= c2 - c1;
           SDLoc DL(N);
           Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
                               DAG.getConstant(c2 - c1, DL, N1.getValueType()));
         } else {
+          if ((c2 < c1) && N0.getValueType().isVector())
+            return SDValue();
           Mask.lshrInPlace(c1 - c2);
           SDLoc DL(N);
           Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
                               DAG.getConstant(c1 - c2, DL, N1.getValueType()));
         }
         SDLoc DL(N0);
         return DAG.getNode(ISD::AND, DL, VT, Shift,
                            DAG.getConstant(Mask, DL, VT));

test/CodeGen/Mips/msa/avoid_shift_combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64el-linux-gnu -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s
+
+define void @avoid_shift_combine(<2 x i64>* %a, <2 x i64>* %b) {
+; CHECK-LABEL: avoid_shift_combine:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld.d $w0, 0($4)
+; CHECK-NEXT:    srli.d $w0, $w0, 52
+; CHECK-NEXT:    slli.d $w0, $w0, 51
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    st.d $w0, 0($5)
+entry:
+  %0 = load <2 x i64>, <2 x i64>* %a
+  %1 = tail call <2 x i64> @llvm.mips.srli.d(<2 x i64> %0, i32 52)
+  %2 = tail call <2 x i64> @llvm.mips.slli.d(<2 x i64> %1, i32 51)
+  store <2 x i64> %2, <2 x i64>* %b
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.slli.d(<2 x i64>, i32)
+declare <2 x i64> @llvm.mips.srli.d(<2 x i64>, i32)

test/CodeGen/X86/combine-shl.ll

 ; AVX-NEXT:    vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 3, i32 4, i32 5, i32 8>
   %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
   ret <4 x i32> %2
 }
 
 ; fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 >= C2
 define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_shl_le_lshr0:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    psrld $2, %xmm0
-; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
+; SSE-NEXT:    psrld $5, %xmm0
+; SSE-NEXT:    pslld $3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: combine_vec_shl_le_lshr0:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [1073741816,1073741816,1073741816,1073741816]
-; AVX-NEXT:    vpsrld $2, %xmm0, %xmm0
-; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $5, %xmm0, %xmm0
+; AVX-NEXT:    vpslld $3, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
   %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) {
 ; SSE2-LABEL: combine_vec_shl_le_lshr1: