[MIPS GlobalISel] Select any extending load and truncating store

[Petar.Avramovic]

Summary

Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and
G_SEXTLOAD. That is perform widenScalarDst to size given by the target
and avoid additional checks in common code. Targets can reorder or add
additional rules in LegalizeRuleSet for the opcode to achieve desired
behavior.

Select extending load that does not have specified type of extension
into zero extending load.

Select truncating store that stores number of bytes indicated by size
in MachineMemoperand.

[Petar.Avramovic]

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

281–284

Hi Matt, I added this additional rule in order to keep the existing behavior (tests legalize-sextload-flat.mir and legalize-zextload-flat.mir) as I am not sure if G_LOADing one byte into s32 is supported by AMDGPU.

[arsenm]

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

1043–1044

I have a patch which also drops this, but now that I think about it, I think this is just checking the wrong size. I think this should really be checking for the memory size rather than result size (but all 3 load opcodes should be consistent here)

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

281–284

Does anything actually break without this?

If no tests fail, you can drop this. I have several local patches rewriting the load and store legality to handle everything

281–284

s8->s32 is fine in any address space for any load type

[Petar.Avramovic]

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

1043–1044

I agree that memory size should be checked, but I think it should not be done here as this is widenScalar and that it should be done in another rule concerning memsize e.g. unsupportedIfMemSizeNotPow2().
Are there any widenScalar sizes that are not target specific and that should be handled in general code?

[arsenm]

LGTM

[Petar.Avramovic]

Hi, Matt. Here are the updated legalizer and tests for AMDGPU.

[arsenm]

LGTM

[arsenm]

Are you going to commit this?

[atanasyan]

LGTM

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

if (TypeIdx != 0)
       return UnableToLegalize;
     Observer.changingInstr(MI);
     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
     widenScalarDst(MI, WideTy);
     Observer.changedInstr(MI);
     return Legalized;
 
   case TargetOpcode::G_LOAD:
-    // For some types like i24, we might try to widen to i32. To properly handle
-    // this we should be using a dedicated extending load, until then avoid
-    // trying to legalize.
-    if (alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) !=
-        WideTy.getSizeInBits())
-      return UnableToLegalize;
-    LLVM_FALLTHROUGH;
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
     Observer.changingInstr(MI);
     widenScalarDst(MI, WideTy);
     Observer.changedInstr(MI);
     return Legalized;
 
   case TargetOpcode::G_STORE: {

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

.legalIf([=, &ST](const LegalityQuery &Query) {
 
         case 256:
         case 512:
           // TODO: constant loads
         default:
           return false;
         }
       })
+    .unsupportedIf([=](const LegalityQuery &Query) {
+      return Query.Opcode == G_LOAD &&
+             alignTo(Query.Types[0].getSizeInBits(), 8) < 32;
+    })
     .clampScalar(0, S32, S64);
 
 
   auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
     .legalForTypesWithMemSize({
         {S32, GlobalPtr, 8},
         {S32, GlobalPtr, 16},
         {S32, LocalPtr, 8},

lib/Target/Mips/MipsInstructionSelector.cpp

 }
 
 /// Returning Opc indicates that we failed to select MIPS instruction opcode.
 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
   if (Opc == TargetOpcode::G_STORE)
     switch (MemSizeInBytes) {
     case 4:
       return Mips::SW;
+    case 2:
+      return Mips::SH;
+    case 1:
+      return Mips::SB;
     default:
       return Opc;
     }
   else
+    // Unspecified extending load is selected into zeroExtending load.
     switch (MemSizeInBytes) {
     case 4:
       return Mips::LW;
     case 2:
       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
     case 1:
       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
     default:

lib/Target/Mips/MipsLegalizerInfo.cpp

MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({s32})
       .clampScalar(0, s32, s32);
 
   getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE})
       .lowerFor({{s32, s1}});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
-      .legalForCartesianProduct({p0, s32}, {p0});
+      .legalForTypesWithMemSize({{s32, p0, 8},
+                                 {s32, p0, 16},
+                                 {s32, p0, 32},
+                                 {p0, p0, 32}})
+      .minScalar(0, s32);
 
   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
       .legalForTypesWithMemSize({{s32, p0, 8},
                                  {s32, p0, 16}})
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder(G_SELECT)
       .legalForCartesianProduct({p0, s32}, {s32})

test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+  define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+  define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name:            load_store_i8
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i8
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY1]], 0 :: (load 1 from %ir.py)
+    ; MIPS32: SB [[LBu]], [[COPY]], 0 :: (store 1 into %ir.px)
+    ; MIPS32: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+    %3:gprb(s32) = COPY %4(s32)
+    G_STORE %3(s32), %0(p0) :: (store 1 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i16
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i16
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY1]], 0 :: (load 2 from %ir.py)
+    ; MIPS32: SH [[LHu]], [[COPY]], 0 :: (store 2 into %ir.px)
+    ; MIPS32: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+    %3:gprb(s32) = COPY %4(s32)
+    G_STORE %3(s32), %0(p0) :: (store 2 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY1]], 0 :: (load 4 from %ir.py)
+    ; MIPS32: SW [[LW]], [[COPY]], 0 :: (store 4 into %ir.px)
+    ; MIPS32: RetRA
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+    G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+    RetRA
+
+...

test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
+  define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
+  define void @load_store_i1(i1* %px, i1* %py) {entry: ret void}
+  define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+  define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+  define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name:            load1_s8_to_load1_s32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load1_s8_to_load1_s32
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.px)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %2:_(s32) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            load2_s16_to_load2_s32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: load2_s16_to_load2_s32
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.px)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %2:_(s32) = G_LOAD %0(p0) :: (load 2 from %ir.px)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            load_store_i1
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i1
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s1) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+    G_STORE %2(s1), %0(p0) :: (store 1 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i8
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i8
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+    ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s8) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+    G_STORE %2(s8), %0(p0) :: (store 1 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i16
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i16
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 2 from %ir.py)
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+    ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 2 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s16) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+    G_STORE %2(s16), %0(p0) :: (store 2 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.py)
+    ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store 4 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+    G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+    RetRA
+
+...

test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i8 @load1_s8_to_load1_s32(i8* %px) {
+; MIPS32-LABEL: load1_s8_to_load1_s32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lbu $2, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i8, i8* %px
+  ret i8 %0
+}
+
+define i16 @load2_s16_to_load2_s32(i16* %px) {
+; MIPS32-LABEL: load2_s16_to_load2_s32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lhu $2, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i16, i16* %px
+  ret i16 %0
+}
+
+define void @load_store_i1(i1* %px, i1* %py) {
+; MIPS32-LABEL: load_store_i1:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lbu $5, 0($5)
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $5, $1
+; MIPS32-NEXT:    sb $1, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i1, i1* %py
+  store i1 %0, i1* %px
+  ret void
+}
+
+define void @load_store_i8(i8* %px, i8* %py) {
+; MIPS32-LABEL: load_store_i8:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lbu $5, 0($5)
+; MIPS32-NEXT:    sb $5, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i8, i8* %py
+  store i8 %0, i8* %px
+  ret void
+}
+
+define void @load_store_i16(i16* %px, i16* %py) {
+; MIPS32-LABEL: load_store_i16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lhu $5, 0($5)
+; MIPS32-NEXT:    sh $5, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i16, i16* %py
+  store i16 %0, i16* %px
+  ret void
+}
+
+define void @load_store_i32(i32* %px, i32* %py) {
+; MIPS32-LABEL: load_store_i32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lw $5, 0($5)
+; MIPS32-NEXT:    sw $5, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %py
+  store i32 %0, i32* %px
+  ret void
+}

test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+  define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+  define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name:            load_store_i8
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i8
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
+    ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+    %3:_(s32) = COPY %4(s32)
+    G_STORE %3(s32), %0(p0) :: (store 1 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i16
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i16
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 2 from %ir.py)
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
+    ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 2 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+    %3:_(s32) = COPY %4(s32)
+    G_STORE %3(s32), %0(p0) :: (store 2 into %ir.px)
+    RetRA
+
+...
+---
+name:            load_store_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: load_store_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.py)
+    ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store 4 into %ir.px)
+    ; MIPS32: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+    G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+    RetRA
+
+...