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Differential D56001

[MIPS GlobalISel] Select G_SELECT
ClosedPublic

Authored by Petar.Avramovic on Dec 21 2018, 6:28 AM.

Details

Reviewers
atanasyan
petarj
dsanders
Commits
rG09dff3334931: [MIPS GlobalISel] Select G_SELECT
rL350063: [MIPS GlobalISel] Select G_SELECT
Summary

Add widen scalar for type index 1 (i1 condition)for G_SELECT.
Select G_SELECT for pointer, s32(integer) and smaller low level
types on MIPS32.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Dec 21 2018, 6:28 AM
Herald added subscribers: arichardson, kristof.beyls, rovka, sdardis. · View Herald TranscriptDec 21 2018, 6:28 AM
atanasyan accepted this revision.Dec 25 2018, 5:32 AM

LGTM

This revision is now accepted and ready to land.Dec 25 2018, 5:32 AM
Closed by commit rL350063: [MIPS GlobalISel] Select G_SELECT (authored by Petar.Avramovic). · Explain WhyDec 25 2018, 6:46 AM
This revision was automatically updated to reflect the committed changes.
Herald added subscribers: llvm-commits, jrtc27. · View Herald TranscriptDec 25 2018, 6:46 AM

Revision Contents

PathSize
lib/
CodeGen/
GlobalISel/
19 lines
Target/
Mips/
9 lines
5 lines
7 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
72 lines
legalizer/
172 lines
llvm-ir/
83 lines
regbankselect/
70 lines

Diff 179281

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 771 Lines • ▼ Show 20 Lines case TargetOpcode::G_LSHR:
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
case TargetOpcode::G_SELECT: case TargetOpcode::G_SELECT:
if (TypeIdx != 0)
return UnableToLegalize;
// Perform operation at larger width (any extension is fine here, high bits
// don't affect the result) and then truncate the result back to the
// original type.
Observer.changingInstr(MI); Observer.changingInstr(MI);
if (TypeIdx == 0) {
// Perform operation at larger width (any extension is fine here, high
// bits don't affect the result) and then truncate the result back to the
// original type.
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
} else {
// Explicit extension is required here since high bits affect the result.
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
}
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FPTOUI:
if (TypeIdx != 0) if (TypeIdx != 0)
return UnableToLegalize; return UnableToLegalize;
Observer.changingInstr(MI); Observer.changingInstr(MI);
▲ Show 20 Lines • Show All 541 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
.addDef(I.getOperand(0).getReg()) .addDef(I.getOperand(0).getReg())
.addUse(HILOReg); .addUse(HILOReg);
if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
return false; return false;
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
case G_SELECT: {
// Handle operands with pointer type.
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
.add(I.getOperand(0))
.add(I.getOperand(2))
.add(I.getOperand(1))
.add(I.getOperand(3));
break;
}
case G_CONSTANT: { case G_CONSTANT: {
int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue(); int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineInstr *LUi, *ORi; MachineInstr *LUi, *ORi;
LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
.addDef(LUiReg) .addDef(LUiReg)
.addImm(Imm >> 16); .addImm(Imm >> 16);
▲ Show 20 Lines • Show All 135 Lines • Show Last 20 Lines

lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 29 Lines getActionDefinitionsBuilder(G_ADD)
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_UADDE) getActionDefinitionsBuilder(G_UADDE)
.lowerFor({{s32, s1}}); .lowerFor({{s32, s1}});
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0}); .legalForCartesianProduct({p0, s32}, {p0});
getActionDefinitionsBuilder(G_SELECT)
.legalForCartesianProduct({p0, s32}, {s32})
.minScalar(0, s32)
.minScalar(1, s32);
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
.legalFor({s32}); .legalFor({s32});
getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV}) getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
Show All 36 Lines

lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break; break;
case G_ICMP: case G_ICMP:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
&Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx]}); &Mips::ValueMappings[Mips::GPRIdx]});
break; break;
case G_SELECT:
OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx]});
break;
default: default:
return getInvalidInstructionMapping(); return getInvalidInstructionMapping();
} }
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping, return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
NumOperands); NumOperands);
} }

test/CodeGen/Mips/GlobalISel/instruction-select/select.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @select_i32() {entry: ret void}
define void @select_ptr() {entry: ret void}
...
---
name: select_i32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_i32
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32: $v0 = COPY [[MOVN_I_I]]
; MIPS32: RetRA implicit $v0
%3:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(s32) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(s32)
RetRA implicit $v0
...
---
name: select_ptr
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_ptr
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32: $v0 = COPY [[MOVN_I_I]]
; MIPS32: RetRA implicit $v0
%3:gprb(s32) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%6:gprb(s32) = G_CONSTANT i32 1
%7:gprb(s32) = COPY %3(s32)
%5:gprb(s32) = G_AND %7, %6
%4:gprb(p0) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(p0)
RetRA implicit $v0
...

test/CodeGen/Mips/GlobalISel/legalizer/select.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @select_i8() {entry: ret void}
define void @select_i16() {entry: ret void}
define void @select_i32() {entry: ret void}
define void @select_ptr() {entry: ret void}
define void @select_with_negation() {entry: ret void}
...
---
name: select_i8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_i8
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; MIPS32: $v0 = COPY [[COPY6]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %4(s32)
%5:_(s32) = COPY $a2
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s8)
$v0 = COPY %7(s32)
RetRA implicit $v0
...
---
name: select_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_i16
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; MIPS32: $v0 = COPY [[COPY6]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %4(s32)
%5:_(s32) = COPY $a2
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_SELECT %0(s1), %1, %2
%7:_(s32) = G_ANYEXT %6(s16)
$v0 = COPY %7(s32)
RetRA implicit $v0
...
---
name: select_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_i32
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%4:_(s32) = G_SELECT %0(s1), %1, %2
$v0 = COPY %4(s32)
RetRA implicit $v0
...
---
name: select_ptr
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_ptr
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](p0)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%4:_(p0) = G_SELECT %0(s1), %1, %2
$v0 = COPY %4(p0)
RetRA implicit $v0
...
---
name: select_with_negation
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: select_with_negation
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%3:_(s32) = COPY $a3
%5:_(s1) = G_CONSTANT i1 true
%4:_(s1) = G_ICMP intpred(slt), %0(s32), %1
%6:_(s1) = G_XOR %4, %5
%7:_(s32) = G_SELECT %6(s1), %2, %3
$v0 = COPY %7(s32)
RetRA implicit $v0
...

test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
; MIPS32-LABEL: select_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%cond = select i1 %test, i8 %a, i8 %b
ret i8 %cond
}
define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
; MIPS32-LABEL: select_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%cond = select i1 %test, i16 %a, i16 %b
ret i16 %cond
}
define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
; MIPS32-LABEL: select_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%cond = select i1 %test, i32 %a, i32 %b
ret i32 %cond
}
define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
; MIPS32-LABEL: select_ptr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%cond = select i1 %test, i32* %a, i32* %b
ret i32* %cond
}
define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
; MIPS32-LABEL: select_with_negation:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 65535
; MIPS32-NEXT: slt $4, $4, $5
; MIPS32-NEXT: xor $1, $4, $1
; MIPS32-NEXT: lui $4, 0
; MIPS32-NEXT: ori $4, $4, 1
; MIPS32-NEXT: and $1, $1, $4
; MIPS32-NEXT: movn $7, $6, $1
; MIPS32-NEXT: move $2, $7
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%cmp = icmp slt i32 %a, %b
%lneg = xor i1 %cmp, true
%cond = select i1 %lneg, i32 %x, i32 %y
ret i32 %cond
}

test/CodeGen/Mips/GlobalISel/regbankselect/select.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @select_i32(i32, i32) {entry: ret void}
define void @select_ptr(i32, i32) {entry: ret void}
...
---
name: select_i32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_i32
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
%4:_(s32) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(s32)
RetRA implicit $v0
...
---
name: select_ptr
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; MIPS32-LABEL: name: select_ptr
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](p0)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%6:_(s32) = G_CONSTANT i32 1
%7:_(s32) = COPY %3(s32)
%5:_(s32) = G_AND %7, %6
%4:_(p0) = G_SELECT %5(s32), %1, %2
$v0 = COPY %4(p0)
RetRA implicit $v0
...