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Differential D55810

[Power9] Enable the Out-of-Order scheduling model for P9 hw
ClosedPublic

Authored by steven.zhang on Dec 17 2018, 11:21 PM.

Details

Reviewers
nemanjai
jsji
kbarton
hfinkel
stefanp
Commits
rGf24ec7bdd06d: [Power9] Enable the Out-of-Order scheduling model for P9 hw
rL350285: [Power9] Enable the Out-of-Order scheduling model for P9 hw
Summary

When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact.

This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

  • x264_r: +6.95%
  • cactuBSSN_r: +6.94%
  • lbm_r: +4.11%
  • xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. The root cause of the deg of xz_r has been addressed and it is another issue that exposed by this change.

Diff Detail

Repository
rL LLVM

Event Timeline

steven.zhang created this revision.Dec 17 2018, 11:21 PM
Herald added subscribers: hiraditya, qcolombet. · View Herald TranscriptDec 17 2018, 11:21 PM
nemanjai accepted this revision.Dec 29 2018, 1:35 PM

LGTM. We definitely want to go ahead with this.

This revision is now accepted and ready to land.Dec 29 2018, 1:35 PM
Closed by commit rL350285: [Power9] Enable the Out-of-Order scheduling model for P9 hw (authored by • qshanz). · Explain WhyJan 2 2019, 9:08 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 179996

llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td

Show All 27 Linesdef P9Model : SchedMachineModel {
// A total of 16 cycles to recover from a branch mispredict. // A total of 16 cycles to recover from a branch mispredict.
let MispredictPenalty = 16; let MispredictPenalty = 16;
// Try to make sure we have at least 10 dispatch groups in a loop. // Try to make sure we have at least 10 dispatch groups in a loop.
// A dispatch group is 6 instructions. // A dispatch group is 6 instructions.
let LoopMicroOpBufferSize = 60; let LoopMicroOpBufferSize = 60;
// As iops are dispatched to a slice, they are held in an independent slice
// issue queue until all register sources and other dependencies have been
// resolved and they can be issued. Each of four execution slices has an
// 11-entry iop issue queue.
let MicroOpBufferSize = 44;
let CompleteModel = 1; let CompleteModel = 1;
// Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
// Engine) on Power 9. // Engine) on Power 9.
let UnsupportedFeatures = [HasQPX, HasSPE]; let UnsupportedFeatures = [HasQPX, HasSPE];
} }
▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/PR33671.ll

Show All 21 Linesentry:
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>* %1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 16 %2 = load <4 x i32>, <4 x i32>* %1, align 16
store <4 x i32> %2, <4 x i32>* %0, align 16 store <4 x i32> %2, <4 x i32>* %0, align 16
ret void ret void
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
; CHECK: addi 3, 3, 8 ; CHECK: addi 3, 3, 8
; CHECK: lxvx [[LD:[0-9]+]], 0, 3 ; CHECK: lxvx [[LD:[0-9]+]], 0, 3
; CHECK: addi 3, 4, 4 ; CHECK: addi [[REG:[0-9]+]], 4, 4
; CHECK: stxvx [[LD]], 0, 3 ; CHECK: stxvx [[LD]], 0, [[REG]]
} }

llvm/trunk/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

Show All 27 Lines
; CHECK-P9-LABEL: testExpandPostRAPseudo: ; CHECK-P9-LABEL: testExpandPostRAPseudo:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: lfiwzx f0, 0, r3 ; CHECK-P9: lfiwzx f0, 0, r3
; CHECK-P9: addis r4, r2, .LC0@toc@ha ; CHECK-P9: addis r4, r2, .LC0@toc@ha
; CHECK-P9: ld r4, .LC0@toc@l(r4) ; CHECK-P9: ld r4, .LC0@toc@l(r4)
; CHECK-P9: xxpermdi vs0, f0, f0, 2 ; CHECK-P9: xxpermdi vs0, f0, f0, 2
; CHECK-P9: xxspltw vs0, vs0, 3 ; CHECK-P9: xxspltw vs0, vs0, 3
; CHECK-P9: stxvx vs0, 0, r4 ; CHECK-P9: stxvx vs0, 0, r4
; CHECK-P9: lis r4, 1024
; CHECK-P9: lfiwax f0, 0, r3 ; CHECK-P9: lfiwax f0, 0, r3
; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: xscvsxdsp f0, f0 ; CHECK-P9: xscvsxdsp f0, f0
; CHECK-P9: ld r3, 0(r3) ; CHECK-P9: ld r3, 0(r3)
; CHECK-P9: lis r4, 1024
; CHECK-P9: stfsx f0, r3, r4 ; CHECK-P9: stfsx f0, r3, r4
; CHECK-P9: blr ; CHECK-P9: blr
entry: entry:
%0 = load i32, i32* %ptr, align 4 %0 = load i32, i32* %ptr, align 4
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
store <4 x i32> %splat.splat, <4 x i32>* @a, align 16 store <4 x i32> %splat.splat, <4 x i32>* @a, align 16
tail call void asm sideeffect "#Clobber Rigisters", "~{f0},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() tail call void asm sideeffect "#Clobber Rigisters", "~{f0},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
%1 = load i32, i32* %ptr, align 4 %1 = load i32, i32* %ptr, align 4
%conv = sitofp i32 %1 to float %conv = sitofp i32 %1 to float
%2 = load float*, float** @pb, align 8 %2 = load float*, float** @pb, align 8
%add.ptr = getelementptr inbounds float, float* %2, i64 16777216 %add.ptr = getelementptr inbounds float, float* %2, i64 16777216
store float %conv, float* %add.ptr, align 4 store float %conv, float* %add.ptr, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/build-vector-tests.ll

Show First 20 Lines • Show All 1,238 Lines • ▼ Show 20 Linesentry:
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
%conv5 = fptosi float %d to i32 %conv5 = fptosi float %d to i32
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
; P9BE-LABEL: fromRegsConvftoi ; P9BE-LABEL: fromRegsConvftoi
; P9LE-LABEL: fromRegsConvftoi ; P9LE-LABEL: fromRegsConvftoi
; P8BE-LABEL: fromRegsConvftoi ; P8BE-LABEL: fromRegsConvftoi
; P8LE-LABEL: fromRegsConvftoi ; P8LE-LABEL: fromRegsConvftoi
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P9BE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P9BE: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9BE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9BE: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9BE: vmrgew v2, [[REG3]], [[REG4]] ; P9BE: vmrgew v2, [[REG3]], [[REG4]]
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P9LE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P9LE: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9LE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9LE: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9LE: vmrgew v2, [[REG4]], [[REG3]] ; P9LE: vmrgew v2, [[REG4]], [[REG3]]
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P8BE: vmrgew v2, [[REG3]], [[REG4]] ; P8BE: vmrgew v2, [[REG3]], [[REG4]]
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Linesentry:
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
%conv5 = fptosi double %d to i32 %conv5 = fptosi double %d to i32
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
; P9BE-LABEL: fromRegsConvdtoi ; P9BE-LABEL: fromRegsConvdtoi
; P9LE-LABEL: fromRegsConvdtoi ; P9LE-LABEL: fromRegsConvdtoi
; P8BE-LABEL: fromRegsConvdtoi ; P8BE-LABEL: fromRegsConvdtoi
; P8LE-LABEL: fromRegsConvdtoi ; P8LE-LABEL: fromRegsConvdtoi
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P9BE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P9BE: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9BE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9BE: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9BE: vmrgew v2, [[REG3]], [[REG4]] ; P9BE: vmrgew v2, [[REG3]], [[REG4]]
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P9LE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P9LE: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9LE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9LE: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9LE: vmrgew v2, [[REG4]], [[REG3]] ; P9LE: vmrgew v2, [[REG4]], [[REG3]]
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P8BE: vmrgew v2, [[REG3]], [[REG4]] ; P8BE: vmrgew v2, [[REG3]], [[REG4]]
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdx ; P8BE: lfdx
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfdux ; P9LE: lfdux
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: xvcvdpsxws ; P9BE: xvcvdpsxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfdux ; P9LE: lfdux
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: xxmrghd
; P9LE: xvcvdpsxws ; P9LE: xvcvdpsxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
▲ Show 20 Lines • Show All 578 Lines • ▼ Show 20 Linesentry:
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
%conv5 = fptoui float %d to i32 %conv5 = fptoui float %d to i32
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
; P9BE-LABEL: fromRegsConvftoui ; P9BE-LABEL: fromRegsConvftoui
; P9LE-LABEL: fromRegsConvftoui ; P9LE-LABEL: fromRegsConvftoui
; P8BE-LABEL: fromRegsConvftoui ; P8BE-LABEL: fromRegsConvftoui
; P8LE-LABEL: fromRegsConvftoui ; P8LE-LABEL: fromRegsConvftoui
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P9BE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P9BE: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9BE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9BE: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9BE: vmrgew v2, [[REG3]], [[REG4]] ; P9BE: vmrgew v2, [[REG3]], [[REG4]]
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P9LE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P9LE: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9LE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9LE: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9LE: vmrgew v2, [[REG4]], [[REG3]] ; P9LE: vmrgew v2, [[REG4]], [[REG3]]
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P8BE: vmrgew v2, [[REG3]], [[REG4]] ; P8BE: vmrgew v2, [[REG3]], [[REG4]]
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Linesentry:
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
%conv5 = fptoui double %d to i32 %conv5 = fptoui double %d to i32
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
; P9BE-LABEL: fromRegsConvdtoui ; P9BE-LABEL: fromRegsConvdtoui
; P9LE-LABEL: fromRegsConvdtoui ; P9LE-LABEL: fromRegsConvdtoui
; P8BE-LABEL: fromRegsConvdtoui ; P8BE-LABEL: fromRegsConvdtoui
; P8LE-LABEL: fromRegsConvdtoui ; P8LE-LABEL: fromRegsConvdtoui
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P9BE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P9BE: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9BE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9BE: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9BE: vmrgew v2, [[REG3]], [[REG4]] ; P9BE: vmrgew v2, [[REG3]], [[REG4]]
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P9LE: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P9LE: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P9LE: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P9LE: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P9LE: vmrgew v2, [[REG4]], [[REG3]] ; P9LE: vmrgew v2, [[REG4]], [[REG3]]
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 ; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] ; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] ; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
; P8BE: vmrgew v2, [[REG3]], [[REG4]] ; P8BE: vmrgew v2, [[REG3]], [[REG4]]
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 ; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
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; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdx ; P8BE: lfdx
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
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; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfdux ; P9LE: lfdux
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: xvcvdpuxws ; P9BE: xvcvdpuxws
; P9BE: vmrgew v2 ; P9BE: vmrgew v2
; P9LE: lfdux ; P9LE: lfdux
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: lfd ; P9LE: lfd
; P9LE: xxmrghd ; P9LE: xxmrghd
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: xxmrghd
; P9LE: xvcvdpuxws ; P9LE: xvcvdpuxws
; P9LE: vmrgew v2 ; P9LE: vmrgew v2
; P8BE: lfdux ; P8BE: lfdux
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: lfd ; P8BE: lfd
; P8BE: xxmrghd ; P8BE: xxmrghd
; P8BE: xxmrghd ; P8BE: xxmrghd
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llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
entry: entry:
%b.addr = alloca i64, align 8 %b.addr = alloca i64, align 8
store i64 %b, i64* %b.addr, align 8 store i64 %b, i64* %b.addr, align 8
%0 = load fp128, fp128* @A, align 16 %0 = load fp128, fp128* @A, align 16
%1 = load i64, i64* %b.addr, align 8 %1 = load i64, i64* %b.addr, align 8
%2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1) %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
ret fp128 %2 ret fp128 %2
; CHECK-LABEL: insert_exp_qp ; CHECK-LABEL: insert_exp_qp
; CHECK: mtvsrd [[FPREG:f[0-9]+]], r3 ; CHECK-DAG: mtvsrd [[FPREG:f[0-9]+]], r3
; CHECK: lxvx [[VECREG:v[0-9]+]] ; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]] ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64) declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
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llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; Since we can only pass a max of 8 float128 value in VSX registers, ensure we ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
; store to stack if passing more. ; store to stack if passing more.
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
align 16 %a) { align 16 %a) {
; CHECK-LABEL: testStruct_03: ; CHECK-LABEL: testStruct_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 128(r1)
; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1) ; CHECK-NEXT: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1) ; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1) ; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1) ; CHECK-NEXT: std r3, 32(r1)
; CHECK-NEXT: lxv v2, 128(r1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_03: ; CHECK-BE-LABEL: testStruct_03:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 144(r1)
; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-NEXT: std r9, 96(r1)
; CHECK-BE-NEXT: std r8, 88(r1) ; CHECK-BE-NEXT: std r8, 88(r1)
; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r7, 80(r1)
; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r6, 72(r1)
; CHECK-BE-NEXT: std r5, 64(r1) ; CHECK-BE-NEXT: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1) ; CHECK-BE-NEXT: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-NEXT: std r3, 48(r1)
; CHECK-BE-NEXT: lxv v2, 144(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a7 = getelementptr inbounds %struct.With9fp128params, %a7 = getelementptr inbounds %struct.With9fp128params,
%struct.With9fp128params* %a, i64 0, i32 6 %struct.With9fp128params* %a, i64 0, i32 6
%0 = load fp128, fp128* %a7, align 16 %0 = load fp128, fp128* %a7, align 16
ret fp128 %0 ret fp128 %0
} }
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i128 %a.coerce.fca.1.extract to fp128 %0 = bitcast i128 %a.coerce.fca.1.extract to fp128
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) { define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-LABEL: testMixedAggregate_03: ; CHECK-LABEL: testMixedAggregate_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-DAG: mtvsrwa v2, r3 ; CHECK: mtvsrwa v2, r3
; CHECK-DAG: mtvsrdd v3, r6, r5
; CHECK: mtvsrd v4, r10
; CHECK: xscvsdqp v2, v2 ; CHECK: xscvsdqp v2, v2
; CHECK-DAG: xscvsdqp v[[REG:[0-9]+]], v4 ; CHECK: mtvsrdd v3, r6, r5
; CHECK-DAG: xsaddqp v2, v3, v2 ; CHECK: xsaddqp v2, v3, v2
; CHECK: mtvsrd v[[REG1:[0-9]+]], r10
; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]]
; CHECK: xsaddqp v2, v2, v[[REG]] ; CHECK: xsaddqp v2, v2, v[[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0 %sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
%sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32 %sa.sroa.0.0.extract.trunc = trunc i128 %sa.coerce.fca.0.extract to i32
%sa.coerce.fca.1.extract = extractvalue [4 x i128] %sa.coerce, 1 %sa.coerce.fca.1.extract = extractvalue [4 x i128] %sa.coerce, 1
%sa.coerce.fca.3.extract = extractvalue [4 x i128] %sa.coerce, 3 %sa.coerce.fca.3.extract = extractvalue [4 x i128] %sa.coerce, 3
%sa.sroa.6.48.extract.shift = lshr i128 %sa.coerce.fca.3.extract, 64 %sa.sroa.6.48.extract.shift = lshr i128 %sa.coerce.fca.3.extract, 64
Show All 10 Lines
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) { define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
; CHECK-LABEL: testNestedAggregate: ; CHECK-LABEL: testNestedAggregate:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: std r8, 72(r1) ; CHECK-NEXT: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: lxv v2, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1) ; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1) ; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1) ; CHECK-NEXT: std r3, 32(r1)
; CHECK-NEXT: lxv v2, 64(r1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: testNestedAggregate: ; CHECK-BE-LABEL: testNestedAggregate:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: std r8, 88(r1) ; CHECK-BE-NEXT: std r8, 88(r1)
; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r7, 80(r1)
; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-NEXT: std r9, 96(r1)
; CHECK-BE-NEXT: lxv v2, 80(r1)
; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r6, 72(r1)
; CHECK-BE-NEXT: std r5, 64(r1) ; CHECK-BE-NEXT: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1) ; CHECK-BE-NEXT: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-NEXT: std r3, 48(r1)
; CHECK-BE-NEXT: lxv v2, 80(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1 %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
%0 = load fp128, fp128* %c, align 16 %0 = load fp128, fp128* %c, align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128 %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define fp128 @sum_float128(i32 signext %count, ...) { define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-LABEL: sum_float128: ; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r11, r2, .LCPI17_0@toc@ha
; CHECK-NEXT: cmpwi cr0, r3, 1
; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1) ; CHECK-NEXT: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1) ; CHECK-NEXT: cmpwi cr0, r3, 1
; CHECK-NEXT: std r4, 40(r1) ; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: addi r11, r11, .LCPI17_0@toc@l ; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-NEXT: lxvx v2, 0, r11 ; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
; CHECK-NEXT: lxvx v2, 0, [[REG1]]
; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxvx v3, 0, r3
; CHECK-NEXT: xsaddqp v2, v3, v2 ; CHECK-NEXT: xsaddqp v2, v3, v2
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
; CHECK-NEXT: std [[REG2]], -8(r1)
; CHECK-NEXT: lxv v3, 16(r3) ; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: addi r3, r1, 72
; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%0 = bitcast i8** %ap to i8* %0 = bitcast i8** %ap to i8*
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2 call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) #2
%cmp = icmp slt i32 %count, 1 %cmp = icmp slt i32 %count, 1
br i1 %cmp, label %cleanup, label %if.end br i1 %cmp, label %cleanup, label %if.end
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llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Linesentry:
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.exp2.f128(fp128 %Val) declare fp128 @llvm.exp2.f128(fp128 %Val)
define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b, define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,
fp128* nocapture %res) { fp128* nocapture %res) {
; CHECK-LABEL: qp_powi: ; CHECK-LABEL: qp_powi:
; CHECK: lxv v2, 0(r3) ; CHECK: lxv v2, 0(r3)
; CHECK: lwz r3, 0(r4) ; CHECK: lwz r5, 0(r4)
; CHECK: bl __powikf2 ; CHECK: bl __powikf2
; CHECK: blr ; CHECK: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load i32, i32* %b, align 8 %1 = load i32, i32* %b, align 8
%2 = tail call fp128 @llvm.powi.f128(fp128 %0, i32 %1) %2 = tail call fp128 @llvm.powi.f128(fp128 %0, i32 %1)
store fp128 %2, fp128* %res, align 16 store fp128 %2, fp128* %res, align 16
ret void ret void
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llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll

Show First 20 Lines • Show All 438 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) { define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2dp_03: ; CHECK-LABEL: qpConv2dp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxvx v2, 0, r5
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16 %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
%conv = fptrunc fp128 %0 to double %conv = fptrunc fp128 %0 to double
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom %arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom
store double %conv, double* %arrayidx, align 8 store double %conv, double* %arrayidx, align 8
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) { define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2sp_03: ; CHECK-LABEL: qpConv2sp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
; CHECK-NEXT: lxv v2, 48(r5) ; CHECK-NEXT: lxv v2, 48(r5)
; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xscvqpdpo v2, v2
; CHECK-NEXT: xsrsp f0, v2 ; CHECK-NEXT: xsrsp f0, v2
; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: stfsx f0, r3, r4 ; CHECK-NEXT: stfsx f0, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16 %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
%conv = fptrunc fp128 %0 to float %conv = fptrunc fp128 %0 to float
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom %arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom
store float %conv, float* %arrayidx, align 4 store float %conv, float* %arrayidx, align 4
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) { define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) {
; CHECK-LABEL: dpConv2qp_03: ; CHECK-LABEL: dpConv2qp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: sldi r4, r4, 4 ; CHECK-DAG: sldi r4, r4, 4
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-DAG: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, r3, r4 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = fpext double %a to fp128 %conv = fpext double %a to fp128
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom %arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom
store fp128 %conv, fp128* %arrayidx, align 16 store fp128 %conv, fp128* %arrayidx, align 16
ret void ret void
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) { define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) {
; CHECK-LABEL: spConv2qp_03: ; CHECK-LABEL: spConv2qp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: sldi r4, r4, 4 ; CHECK-DAG: sldi r4, r4, 4
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-DAG: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, r3, r4 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = fpext float %a to fp128 %conv = fpext float %a to fp128
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom %arrayidx = getelementptr inbounds fp128, fp128* %res, i64 %idxprom
store fp128 %conv, fp128* %arrayidx, align 16 store fp128 %conv, fp128* %arrayidx, align 16
ret void ret void
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; array of float128 types ; array of float128 types
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @fp128Array(fp128* nocapture readonly %farray, define fp128 @fp128Array(fp128* nocapture readonly %farray,
; CHECK-LABEL: fp128Array: ; CHECK-LABEL: fp128Array:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 4 ; CHECK-NEXT: sldi r4, r4, 4
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: add r4, r3, r4 ; CHECK-NEXT: add [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: lxv v3, -16(r4) ; CHECK-NEXT: lxv v3, -16([[REG]])
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
i32 signext %loopcnt, fp128* nocapture readnone %sum) { i32 signext %loopcnt, fp128* nocapture readnone %sum) {
entry: entry:
%0 = load fp128, fp128* %farray, align 16 %0 = load fp128, fp128* %farray, align 16
%sub = add nsw i32 %loopcnt, -1 %sub = add nsw i32 %loopcnt, -1
%idxprom = sext i32 %sub to i64 %idxprom = sext i32 %sub to i64
%arrayidx1 = getelementptr inbounds fp128, fp128* %farray, i64 %idxprom %arrayidx1 = getelementptr inbounds fp128, fp128* %farray, i64 %idxprom
%1 = load fp128, fp128* %arrayidx1, align 16 %1 = load fp128, fp128* %arrayidx1, align 16
%add = fadd fp128 %0, %1 %add = fadd fp128 %0, %1
ret fp128 %add ret fp128 %add
} }
; Up to 12 qualified floating-point arguments can be passed in v2-v13. ; Up to 12 qualified floating-point arguments can be passed in v2-v13.
; Function to test passing 13 float128 parameters. ; Function to test passing 13 float128 parameters.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5, define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-LABEL: maxVecParam: ; CHECK-LABEL: maxVecParam:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xsaddqp v2, v2, v4 ; CHECK-NEXT: xsaddqp v2, v2, v4
; CHECK-NEXT: xsaddqp v2, v2, v5 ; CHECK-NEXT: xsaddqp v2, v2, v5
; CHECK-NEXT: xsaddqp v2, v2, v6 ; CHECK-NEXT: xsaddqp v2, v2, v6
; CHECK-NEXT: xsaddqp v2, v2, v7 ; CHECK-NEXT: xsaddqp v2, v2, v7
; CHECK-NEXT: xsaddqp v2, v2, v8 ; CHECK-NEXT: xsaddqp v2, v2, v8
; CHECK-NEXT: xsaddqp v2, v2, v9 ; CHECK-NEXT: xsaddqp v2, v2, v9
; CHECK-NEXT: xsaddqp v2, v2, v10 ; CHECK-NEXT: xsaddqp v2, v2, v10
; CHECK-NEXT: xsaddqp v2, v2, v11 ; CHECK-NEXT: xsaddqp v2, v2, v11
; CHECK-NEXT: xsaddqp v2, v2, v12 ; CHECK-NEXT: xsaddqp v2, v2, v12
; CHECK-NEXT: xsaddqp v2, v2, v13 ; CHECK-NEXT: xsaddqp v2, v2, v13
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xssubqp v2, v2, v[[REG0]] ; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10, fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
fp128 %p11, fp128 %p12, fp128 %p13) { fp128 %p11, fp128 %p12, fp128 %p13) {
entry: entry:
%add = fadd fp128 %p1, %p2 %add = fadd fp128 %p1, %p2
%add1 = fadd fp128 %add, %p3 %add1 = fadd fp128 %add, %p3
%add2 = fadd fp128 %add1, %p4 %add2 = fadd fp128 %add1, %p4
Show All 9 Linesentry:
ret fp128 %sub ret fp128 %sub
} }
; Passing a mix of float128 and other type parameters. ; Passing a mix of float128 and other type parameters.
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) { define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01: ; CHECK-LABEL: mixParam_01:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrwa v4, r5 ; CHECK-DAG: mtvsrwa [[REG1:v[0-9]+]], r5
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-DAG: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvsdqp v[[REG0:[0-9]+]], v4 ; CHECK-NEXT: xscvsdqp v[[REG0:[0-9]+]], [[REG1]]
; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]] ; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add = fadd fp128 %a, %b %add = fadd fp128 %a, %b
%conv = sitofp i32 %i to fp128 %conv = sitofp i32 %i to fp128
%add1 = fadd fp128 %add, %conv %add1 = fadd fp128 %add, %conv
ret fp128 %add1 ret fp128 %add1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) { define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01f: ; CHECK-LABEL: mixParam_01f:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrwa v[[REG0:[0-9]+]], r3 ; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r3
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-DAG: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvsdqp v[[REG1:[0-9]+]], v[[REG0]] ; CHECK-NEXT: xscvsdqp v[[REG1:[0-9]+]], v[[REG0]]
; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]] ; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add = fadd fp128 %a, %b %add = fadd fp128 %a, %b
%conv = sitofp i32 %i to fp128 %conv = sitofp i32 %i to fp128
%add1 = fadd fp128 %add, %conv %add1 = fadd fp128 %add, %conv
ret fp128 %add1 ret fp128 %add1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3, define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02: ; CHECK-LABEL: mixParam_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-DAG: lwz r3, 96(r1) ; CHECK: lwz r3, 96(r1)
; CHECK: add r4, r7, r9 ; CHECK: add r4, r7, r9
; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1 ; CHECK: add r4, r4, r10
; CHECK-DAG: add r4, r4, r10 ; CHECK: add r3, r4, r3
; CHECK: clrldi r3, r3, 32
; CHECK: std r3, 0(r6)
; CHECK: lxv v[[REG1:[0-9]+]], 0(r8)
; CHECK: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK: xscvdpqp v[[REG0]], v[[REG0]] ; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: add r3, r4, r3 ; CHECK: xsaddqp v2, v[[REG1]], v2
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK: xsaddqp v2, v2, v3
; CHECK-NEXT: std r3, 0(r6)
; CHECK-NEXT: lxv v[[REG1:[0-9]+]], 0(r8)
; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5, i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) { i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
entry: entry:
%conv = sext i16 %p4 to i32 %conv = sext i16 %p4 to i32
%add = add nsw i32 %conv, %p6 %add = add nsw i32 %conv, %p6
%conv1 = zext i8 %p7 to i32 %conv1 = zext i8 %p7 to i32
%add2 = add nsw i32 %add, %conv1 %add2 = add nsw i32 %add, %conv1
%add3 = add i32 %add2, %p8 %add3 = add i32 %add2, %p8
%conv4 = zext i32 %add3 to i64 %conv4 = zext i32 %add3 to i64
store i64 %conv4, i64* %p3, align 8 store i64 %conv4, i64* %p3, align 8
%0 = load fp128, fp128* %p5, align 16 %0 = load fp128, fp128* %p5, align 16
%add5 = fadd fp128 %0, %p1 %add5 = fadd fp128 %0, %p1
%conv6 = fpext double %p2 to fp128 %conv6 = fpext double %p2 to fp128
%add7 = fadd fp128 %add5, %conv6 %add7 = fadd fp128 %add5, %conv6
ret fp128 %add7 ret fp128 %add7
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3, define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02f: ; CHECK-LABEL: mixParam_02f:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r4, r4, r6 ; CHECK-NEXT: add r4, r4, r6
; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-NEXT: add r4, r4, r7 ; CHECK-NEXT: add r4, r4, r7
; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: add r4, r4, r8 ; CHECK-NEXT: add r4, r4, r8
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: std r4, 0(r3) ; CHECK-DAG: std r4, 0(r3)
; CHECK-NEXT: lxv v[[REG1:[0-9]+]], 0(r5) ; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r5)
; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2 ; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]] ; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5, i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) { i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
entry: entry:
%conv = sext i16 %p4 to i32 %conv = sext i16 %p4 to i32
%add = add nsw i32 %conv, %p6 %add = add nsw i32 %conv, %p6
Show All 10 Lines
} }
; Passing a mix of float128 and vector parameters. ; Passing a mix of float128 and vector parameters.
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1, define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03: ; CHECK-LABEL: mixParam_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-DAG: ld r3, 104(r1) ; CHECK-DAG: ld r3, 104(r1)
; CHECK-DAG: mtvsrwa v[[REG2:[0-9]+]], r10
; CHECK-DAG: stxv v2, 0(r9) ; CHECK-DAG: stxv v2, 0(r9)
; CHECK-DAG: xscvsdqp v[[REG1:[0-9]+]], v[[REG2]]
; CHECK: stxvx v3, 0, r3 ; CHECK: stxvx v3, 0, r3
; CHECK-NEXT: lxv v2, 0(r9) ; CHECK: mtvsrwa v[[REG2:[0-9]+]], r10
; CHECK-DAG: xscvsdqp v[[REG1:[0-9]+]], v[[REG2]]
; CHECK-DAG: lxv v2, 0(r9)
; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]] ; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r5) ; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
<4 x i32>* nocapture %vec2) { <4 x i32>* nocapture %vec2) {
entry: entry:
store fp128 %f1, fp128* %f2, align 16 store fp128 %f1, fp128* %f2, align 16
store <4 x i32> %vec1, <4 x i32>* %vec2, align 16 store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
%0 = load fp128, fp128* %f2, align 16 %0 = load fp128, fp128* %f2, align 16
%conv = sitofp i32 %i1 to fp128 %conv = sitofp i32 %i1 to fp128
%add = fadd fp128 %0, %conv %add = fadd fp128 %0, %conv
%conv1 = fptrunc fp128 %add to double %conv1 = fptrunc fp128 %add to double
store double %conv1, double* %d1, align 8 store double %conv1, double* %d1, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1, define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03f: ; CHECK-LABEL: mixParam_03f:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrwa v[[REG0:[0-9]+]], r5 ; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r5
; CHECK-NEXT: stxv v[[REG1:[0-9]+]], 0(r4) ; CHECK-DAG: stxv v[[REG1:[0-9]+]], 0(r4)
; CHECK-NEXT: stxv v[[REG2:[0-9]+]], 0(r7) ; CHECK-DAG: stxv v[[REG2:[0-9]+]], 0(r7)
; CHECK-NEXT: lxv v[[REG1]], 0(r4) ; CHECK-DAG: lxv v[[REG1]], 0(r4)
; CHECK-NEXT: xscvsdqp v[[REG3:[0-9]+]], v[[REG0]] ; CHECK-NEXT: xscvsdqp v[[REG3:[0-9]+]], v[[REG0]]
; CHECK-NEXT: xsaddqp v[[REG4:[0-9]+]], v[[REG1]], v[[REG3]] ; CHECK-NEXT: xsaddqp v[[REG4:[0-9]+]], v[[REG1]], v[[REG3]]
; CHECK-NEXT: xscvqpdp v2, v[[REG4]] ; CHECK-NEXT: xscvqpdp v2, v[[REG4]]
; CHECK-NEXT: stxsd v2, 0(r3) ; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
<4 x i32>* nocapture %vec2) { <4 x i32>* nocapture %vec2) {
entry: entry:
Show All 9 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesentry:
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0, ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16 i64 1), align 16
%add = fadd fp128 %0, %1 %add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i64 %conv = fptosi fp128 %add to i64
ret i64 %conv ret i64 %conv
; CHECK-LABEL: qpConv2sdw_03 ; CHECK-LABEL: qpConv2sdw_03
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha ; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) ; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) ; CHECK: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] ; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] ; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]] ; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2sdw_04(fp128* nocapture readonly %a, define void @qpConv2sdw_04(fp128* nocapture readonly %a,
Show All 24 Linesentry:
%conv = fptosi fp128 %0 to i64 %conv = fptosi fp128 %0 to i64
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8 store i64 %conv, i64* %arrayidx, align 8
ret void ret void
; CHECK-LABEL: qpConv2sdw_testXForm ; CHECK-LABEL: qpConv2sdw_testXForm
; CHECK: xscvqpsdz v[[CONV:[0-9]+]], ; CHECK: xscvqpsdz v[[CONV:[0-9]+]],
; CHECK-NEXT: stxsdx v[[CONV]], r3, r4 ; CHECK: stxsdx v[[CONV]], r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2udw(fp128* nocapture readonly %a) { define i64 @qpConv2udw(fp128* nocapture readonly %a) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i64 %conv = fptoui fp128 %0 to i64
Show All 32 Linesentry:
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0, ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16 i64 1), align 16
%add = fadd fp128 %0, %1 %add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i64 %conv = fptoui fp128 %add to i64
ret i64 %conv ret i64 %conv
; CHECK-LABEL: qpConv2udw_03 ; CHECK-LABEL: qpConv2udw_03
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha ; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) ; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) ; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] ; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]] ; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
; CHECK-NEXT: mfvsrd r3, v[[CONV]] ; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2udw_04(fp128* nocapture readonly %a, define void @qpConv2udw_04(fp128* nocapture readonly %a,
Show All 24 Linesentry:
%conv = fptoui fp128 %0 to i64 %conv = fptoui fp128 %0 to i64
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8 store i64 %conv, i64* %arrayidx, align 8
ret void ret void
; CHECK-LABEL: qpConv2udw_testXForm ; CHECK-LABEL: qpConv2udw_testXForm
; CHECK: xscvqpudz v[[CONV:[0-9]+]], ; CHECK: xscvqpudz v[[CONV:[0-9]+]],
; CHECK-NEXT: stxsdx v[[CONV]], r3, r4 ; CHECK: stxsdx v[[CONV]], r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i32 @qpConv2sw(fp128* nocapture readonly %a) { define signext i32 @qpConv2sw(fp128* nocapture readonly %a) {
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i32 %conv = fptosi fp128 %0 to i32
Show All 33 Linesentry:
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0, ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16 i64 1), align 16
%add = fadd fp128 %0, %1 %add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i32 %conv = fptosi fp128 %add to i32
ret i32 %conv ret i32 %conv
; CHECK-LABEL: qpConv2sw_03 ; CHECK-LABEL: qpConv2sw_03
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha ; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) ; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) ; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] ; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]] ; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]] ; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
; CHECK-NEXT: extsw r3, r[[REG2]] ; CHECK-NEXT: extsw r3, r[[REG2]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesentry:
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0, ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16 i64 1), align 16
%add = fadd fp128 %0, %1 %add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i32 %conv = fptoui fp128 %add to i32
ret i32 %conv ret i32 %conv
; CHECK-LABEL: qpConv2uw_03 ; CHECK-LABEL: qpConv2uw_03
; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha ; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha
; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) ; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]])
; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) ; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] ; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]] ; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]]
; CHECK-NEXT: mfvsrwz r3, v[[CONV]] ; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2uw_04(fp128* nocapture readonly %a, define void @qpConv2uw_04(fp128* nocapture readonly %a,
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesentry:
store i16 %conv, i16* %res, align 2 store i16 %conv, i16* %res, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) { define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw_03: ; CHECK-LABEL: qpConv2shw_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
store i16 %conv, i16* %res, align 2 store i16 %conv, i16* %res, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) { define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw_03: ; CHECK-LABEL: qpConv2uhw_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
store i8 %conv, i8* %res, align 1 store i8 %conv, i8* %res, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) { define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb_03: ; CHECK-LABEL: qpConv2sb_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
store i8 %conv, i8* %res, align 1 store i8 %conv, i8* %res, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) { define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub_03: ; CHECK-LABEL: qpConv2ub_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LC0@toc@ha
; CHECK-NEXT: lxv v3, 16(r4) ; CHECK-NEXT: ld [[REG1:r[0-9]+]], .LC0@toc@l([[REG]])
; CHECK-NEXT: lxv v3, 16([[REG1]])
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds %1 = load fp128, fp128* getelementptr inbounds
Show All 26 Lines

llvm/trunk/test/CodeGen/PowerPC/mi-scheduling-lhs.ll

Show All 34 Lines
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret i32 0 ret i32 0
; CHECK-LABEL: foo ; CHECK-LABEL: foo
; CHECK: addis [[REG1:[0-9]+]], 2, a@toc@ha ; CHECK: addis [[REG1:[0-9]+]], 2, a@toc@ha
; CHECK: li [[REG4:[0-9]+]], 5 ; CHECK: li [[REG4:[0-9]+]], 5
; CHECK: [[LAB:[a-z0-9A-Z_.]+]]: ; CHECK: [[LAB:[a-z0-9A-Z_.]+]]:
; CHECK: ld [[REG2:[0-9]+]], a@toc@l([[REG1]]) ; CHECK: ld [[REG2:[0-9]+]], a@toc@l([[REG1]])
; CHECK: ld [[REG3:[0-9]+]], 0([[REG2]])
; CHECK: stw [[REG4]], 8([[REG2]]) ; CHECK: stw [[REG4]], 8([[REG2]])
; CHECK: ld [[REG3:[0-9]+]], 0([[REG2]])
; CHECK: stw [[REG4]], 8([[REG3]]) ; CHECK: stw [[REG4]], 8([[REG3]])
; CHECK: std [[REG3]], 0([[REG3]]) ; CHECK: std [[REG3]], 0([[REG3]])
; CHECK: bdnz [[LAB]] ; CHECK: bdnz [[LAB]]
} }

llvm/trunk/test/CodeGen/PowerPC/mulld.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN ; RUN: --check-prefix=CHECK-ITIN
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN ; RUN: --check-prefix=CHECK-ITIN
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN ; RUN: --check-prefix=CHECK-ITIN
define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) { define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
; CHECK-LABEL: bn_mul_comba8: ; CHECK-LABEL: bn_mul_comba8:
; CHECK: mulhdu ; CHECK: mulhdu
; CHECK-NEXT: mulld ; CHECK-NEXT: mulld
; CHECK-NEXT: mulhdu ; CHECK: mulhdu
; CHECK-NEXT: mulld ; CHECK: mulld
; CHECK-NEXT: mulhdu ; CHECK-NEXT: mulhdu
; CHECK-ITIN-LABEL: bn_mul_comba8: ; CHECK-ITIN-LABEL: bn_mul_comba8:
; CHECK-ITIN: mulhdu ; CHECK-ITIN: mulhdu
; CHECK-ITIN-NEXT: mulld ; CHECK-ITIN-NEXT: mulld
; CHECK-ITIN-NEXT: mulhdu ; CHECK-ITIN-NEXT: mulhdu
; CHECK-ITIN-NEXT: mulld ; CHECK-ITIN-NEXT: mulld
Show All 30 Lines

llvm/trunk/test/CodeGen/PowerPC/pre-inc-disable.ll

; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
; RUN: < %s | FileCheck %s --check-prefix=P9BE ; RUN: < %s | FileCheck %s --check-prefix=P9BE
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_1: ; CHECK-LABEL: test_pre_inc_disable_1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: addis r6, r2
; CHECK: addis r7, r2,
; CHECK: lfd f0, 0(r5) ; CHECK: lfd f0, 0(r5)
; CHECK: xxlxor v4, v4, v4 ; CHECK: addis r5, r2
; CHECK: addi r5, r6, ; CHECK: addi r5, r5,
; CHECK: addi r6, r7,
; CHECK: lxvx v2, 0, r5 ; CHECK: lxvx v2, 0, r5
; CHECK: lxvx v3, 0, r6 ; CHECK: addis r5, r2,
; CHECK: addi r5, r5,
; CHECK: lxvx v4, 0, r5
; CHECK: xxpermdi v5, f0, f0, 2 ; CHECK: xxpermdi v5, f0, f0, 2
; CHECK-DAG: vperm v[[VR1:[0-9]+]], v4, v5, v2 ; CHECK: xxlxor v3, v3, v3
; CHECK-DAG: vperm v[[VR2:[0-9]+]], v5, v4, v3 ; CHECK-DAG: vperm v[[VR1:[0-9]+]], v5, v3, v4
; CHECK-DAG: vperm v[[VR2:[0-9]+]], v3, v5, v2
; CHECK-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]] ; CHECK-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]]
; CHECK-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]] ; CHECK-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]]
; CHECK: .LBB0_1: # %for.cond1.preheader ; CHECK: .LBB0_1: # %for.cond1.preheader
; CHECK: lfd f0, 0(r3) ; CHECK: lfd f0, 0(r3)
; CHECK: xxpermdi v1, f0, f0, 2 ; CHECK: xxpermdi v1, f0, f0, 2
; CHECK: vperm v6, v1, v4, v3 ; CHECK: vperm v6, v3, v1, v2
; CHECK: vperm v1, v4, v1, v2 ; CHECK: vperm v1, v1, v3, v4
; CHECK-DAG: xvnegsp v6, v6 ; CHECK-DAG: xvnegsp v6, v6
; CHECK-DAG: xvnegsp v1, v1 ; CHECK-DAG: xvnegsp v1, v1
; CHECK-DAG: vabsduw v1, v1, v[[VR3]] ; CHECK-DAG: vabsduw v1, v1, v[[VR3]]
; CHECK-DAG: vabsduw v6, v6, v[[VR4]] ; CHECK-DAG: vabsduw v6, v6, v[[VR4]]
; CHECK: vadduwm v1, v6, v1 ; CHECK: vadduwm v1, v1, v6
; CHECK: xxswapd v6, v1 ; CHECK: xxswapd v6, v1
; CHECK: vadduwm v1, v1, v6 ; CHECK: vadduwm v1, v1, v6
; CHECK: xxspltw v6, v1, 2 ; CHECK: xxspltw v6, v1, 2
; CHECK: vadduwm v1, v1, v6 ; CHECK: vadduwm v1, v1, v6
; CHECK: vextuwrx r7, r6, v1 ; CHECK: vextuwrx r7, r5, v1
; CHECK: ldux r8, r3, r4 ; CHECK: ldux r8, r3, r4
; CHECK: add r3, r3, r4 ; CHECK: add r3, r3, r4
; CHECK: add r5, r7, r5 ; CHECK: add r6, r7, r6
; CHECK: mtvsrd f0, r8 ; CHECK: mtvsrd f0, r8
; CHECK: xxswapd v1, vs0 ; CHECK: xxswapd v1, vs0
; CHECK: vperm v6, v1, v4, v3 ; CHECK: vperm v6, v3, v1, v2
; CHECK: vperm v1, v4, v1, v2 ; CHECK: vperm v1, v1, v3, v4
; CHECK-DAG: xvnegsp v6, v6 ; CHECK-DAG: xvnegsp v6, v6
; CHECK-DAG: xvnegsp v1, v1 ; CHECK-DAG: xvnegsp v1, v1
; CHECK-DAG: vabsduw v1, v1, v[[VR3]] ; CHECK-DAG: vabsduw v1, v1, v[[VR3]]
; CHECK-DAG: vabsduw v6, v6, v[[VR4]] ; CHECK-DAG: vabsduw v6, v6, v[[VR4]]
; CHECK: vadduwm v1, v6, v1 ; CHECK: vadduwm v1, v1, v6
; CHECK: xxswapd v6, v1 ; CHECK: xxswapd v6, v1
; CHECK: vadduwm v1, v1, v6 ; CHECK: vadduwm v1, v1, v6
; CHECK: xxspltw v6, v1, 2 ; CHECK: xxspltw v6, v1, 2
; CHECK: vadduwm v1, v1, v6 ; CHECK: vadduwm v1, v1, v6
; CHECK: vextuwrx r8, r6, v1 ; CHECK: vextuwrx r7, r5, v1
; CHECK: add r5, r8, r5 ; CHECK: add r6, r7, r6
; CHECK: bdnz .LBB0_1 ; CHECK: bdnz .LBB0_1
; CHECK: extsw r3, r5 ; CHECK: extsw r3, r6
; CHECK: blr ; CHECK: blr
; P9BE-LABEL: test_pre_inc_disable_1: ; P9BE-LABEL: test_pre_inc_disable_1:
; P9BE: addis r6, r2,
; P9BE: addis r7, r2,
; P9BE: lfd f0, 0(r5) ; P9BE: lfd f0, 0(r5)
; P9BE: xxlxor v4, v4, v4 ; P9BE: addis r5, r2,
; P9BE: addi r5, r6, ; P9BE: addi r5, r5,
; P9BE: addi r6, r7,
; P9BE: lxvx v2, 0, r5 ; P9BE: lxvx v2, 0, r5
; P9BE: lxvx v3, 0, r6 ; P9BE: addis r5, r2,
; P9BE: addi r5, r5,
; P9BE: lxvx v4, 0, r5
; P9BE: xxlor v5, vs0, vs0 ; P9BE: xxlor v5, vs0, vs0
; P9BE: li r6, 0 ; P9BE: xxlxor v3, v3, v3
; P9BE-DAG: vperm v[[VR1:[0-9]+]], v4, v5, v2 ; P9BE-DAG: li r5, 0
; P9BE-DAG: vperm v[[VR2:[0-9]+]], v4, v5, v3 ; P9BE-DAG: vperm v[[VR1:[0-9]+]], v3, v5, v2
; P9BE-DAG: vperm v[[VR2:[0-9]+]], v3, v5, v4
; P9BE-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]] ; P9BE-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]]
; P9BE-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]] ; P9BE-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]]
; P9BE: .LBB0_1: # %for.cond1.preheader ; P9BE: .LBB0_1: # %for.cond1.preheader
; P9BE: lfd f0, 0(r3) ; P9BE: lfd f0, 0(r3)
; P9BE: xxlor v1, vs0, vs0 ; P9BE: xxlor v1, vs0, vs0
; P9BE: vperm v6, v4, v1, v3 ; P9BE: vperm v6, v3, v1, v4
; P9BE: vperm v1, v4, v1, v2 ; P9BE: vperm v1, v3, v1, v2
; P9BE-DAG: xvnegsp v6, v6 ; P9BE-DAG: xvnegsp v6, v6
; P9BE-DAG: xvnegsp v1, v1 ; P9BE-DAG: xvnegsp v1, v1
; P9BE-DAG: vabsduw v1, v1, v[[VR3]] ; P9BE-DAG: vabsduw v1, v1, v[[VR3]]
; P9BE-DAG: vabsduw v6, v6, v[[VR4]] ; P9BE-DAG: vabsduw v6, v6, v[[VR4]]
; P9BE: vadduwm v1, v6, v1 ; P9BE: vadduwm v1, v6, v1
; P9BE: xxswapd v6, v1 ; P9BE: xxswapd v6, v1
; P9BE: vadduwm v1, v1, v6 ; P9BE: vadduwm v1, v1, v6
; P9BE: xxspltw v6, v1, 1 ; P9BE: xxspltw v6, v1, 1
; P9BE: vadduwm v1, v1, v6 ; P9BE: vadduwm v1, v1, v6
; P9BE: vextuwlx r[[GR1:[0-9]+]], r6, v1 ; P9BE: vextuwlx r[[GR1:[0-9]+]], r5, v1
; P9BE: add r6, r[[GR1]], r6
; P9BE: ldux r[[GR2:[0-9]+]], r3, r4 ; P9BE: ldux r[[GR2:[0-9]+]], r3, r4
; P9BE: add r3, r3, r4 ; P9BE: add r3, r3, r4
; P9BE: add r5, r[[GR1]], r5
; P9BE: mtvsrd v1, r[[GR2]] ; P9BE: mtvsrd v1, r[[GR2]]
; P9BE: vperm v6, v4, v1, v3 ; P9BE: vperm v6, v3, v1, v2
; P9BE: vperm v1, v4, v1, v2 ; P9BE: vperm v1, v3, v1, v4
; P9BE-DAG: xvnegsp v6, v6 ; P9BE-DAG: xvnegsp v6, v6
; P9BE-DAG: xvnegsp v1, v1 ; P9BE-DAG: xvnegsp v1, v1
; P9BE-DAG: vabsduw v1, v1, v[[VR3]] ; P9BE-DAG: vabsduw v1, v1, v[[VR4]]
; P9BE-DAG: vabsduw v6, v6, v[[VR4]] ; P9BE-DAG: vabsduw v6, v6, v[[VR3]]
; P9BE: vadduwm v1, v6, v1 ; P9BE: vadduwm v1, v1, v6
; P9BE: xxswapd v6, v1 ; P9BE: xxswapd v6, v1
; P9BE: vadduwm v1, v1, v6 ; P9BE: vadduwm v1, v1, v6
; P9BE: xxspltw v6, v1, 1 ; P9BE: xxspltw v6, v1, 1
; P9BE: vadduwm v1, v1, v6 ; P9BE: vadduwm v1, v1, v6
; P9BE: vextuwlx r8, r6, v1 ; P9BE: vextuwlx r7, r5, v1
; P9BE: add r5, r8, r5 ; P9BE: add r6, r7, r6
; P9BE: bdnz .LBB0_1 ; P9BE: bdnz .LBB0_1
; P9BE: extsw r3, r5 ; P9BE: extsw r3, r6
; P9BE: blr ; P9BE: blr
entry: entry:
%idx.ext = sext i32 %i_stride_pix1 to i64 %idx.ext = sext i32 %i_stride_pix1 to i64
%0 = bitcast i8* %pix2 to <8 x i8>* %0 = bitcast i8* %pix2 to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 1 %1 = load <8 x i8>, <8 x i8>* %0, align 1
%2 = zext <8 x i8> %1 to <8 x i32> %2 = zext <8 x i8> %1 to <8 x i32>
br label %for.cond1.preheader br label %for.cond1.preheader
Show All 39 Lines
for.cond.cleanup: ; preds = %for.cond1.preheader for.cond.cleanup: ; preds = %for.cond1.preheader
ret i32 %op.extra.1 ret i32 %op.extra.1
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_2: ; CHECK-LABEL: test_pre_inc_disable_2:
; CHECK: addis r5, r2,
; CHECK: addis r6, r2,
; CHECK: lfd f0, 0(r3) ; CHECK: lfd f0, 0(r3)
; CHECK: lfd f1, 0(r4) ; CHECK: addis r3, r2,
; CHECK: xxlxor v0, v0, v0 ; CHECK: addi r3, r3, .LCPI1_0@toc@l
; CHECK: addi r3, r5, .LCPI1_0@toc@l ; CHECK: lxvx v4, 0, r3
; CHECK: addi r4, r6, .LCPI1_1@toc@l ; CHECK: addis r3, r2,
; CHECK: lxvx v2, 0, r3 ; CHECK: xxpermdi v2, f0, f0, 2
; CHECK: lxvx v3, 0, r4 ; CHECK: lfd f0, 0(r4)
; CHECK: xxpermdi v4, f0, f0, 2 ; CHECK: addi r3, r3, .LCPI1_1@toc@l
; CHECK: xxpermdi v5, f1, f1, 2 ; CHECK: xxlxor v3, v3, v3
; CHECK: vperm v1, v4, v0, v2 ; CHECK: lxvx v0, 0, r3
; CHECK: vperm v4, v0, v4, v3 ; CHECK: xxpermdi v1, f0, f0, 2
; CHECK: vperm v2, v5, v0, v2 ; CHECK: vperm v5, v2, v3, v4
; CHECK: vperm v3, v0, v5, v3 ; CHECK: vperm v2, v3, v2, v0
; CHECK: vabsduw v3, v4, v3 ; CHECK: vperm v0, v3, v1, v0
; CHECK: vabsduw v2, v1, v2 ; CHECK: vperm v3, v1, v3, v4
; CHECK: vadduwm v2, v2, v3 ; CHECK: vabsduw v2, v2, v0
; CHECK: vabsduw v3, v5, v3
; CHECK: vadduwm v2, v3, v2
; CHECK: xxswapd v3, v2 ; CHECK: xxswapd v3, v2
; CHECK: vadduwm v2, v2, v3 ; CHECK: vadduwm v2, v2, v3
; CHECK: xxspltw v3, v2, 2 ; CHECK: xxspltw v3, v2, 2
; CHECK: vadduwm v2, v2, v3 ; CHECK: vadduwm v2, v2, v3
; CHECK: vextuwrx r3, r3, v2 ; CHECK: vextuwrx r3, r3, v2
; CHECK: extsw r3, r3 ; CHECK: extsw r3, r3
; CHECK: blr ; CHECK: blr
; P9BE-LABEL: test_pre_inc_disable_2: ; P9BE-LABEL: test_pre_inc_disable_2:
; P9BE: addis r5, r2,
; P9BE: addis r6, r2,
; P9BE: lfd f0, 0(r3) ; P9BE: lfd f0, 0(r3)
; P9BE: lfd f1, 0(r4) ; P9BE: addis r3, r2,
; P9BE: xxlxor v5, v5, v5 ; P9BE: addi r3, r3,
; P9BE: addi r3, r5, ; P9BE: lxvx v4, 0, r3
; P9BE: addi r4, r6, ; P9BE: addis r3, r2,
; P9BE: lxvx v2, 0, r3 ; P9BE: addi r3, r3,
; P9BE: lxvx v3, 0, r4 ; P9BE: xxlor v2, vs0, vs0
; P9BE: xxlor v4, vs0, vs0 ; P9BE: lfd f0, 0(r4)
; P9BE: xxlor v0, vs1, vs1 ; P9BE: lxvx v0, 0, r3
; P9BE: vperm v1, v5, v4, v2 ; P9BE: xxlxor v3, v3, v3
; P9BE: vperm v4, v5, v4, v3 ; P9BE: xxlor v1, vs0, vs0
; P9BE: vperm v2, v5, v0, v2 ; P9BE: vperm v5, v3, v2, v4
; P9BE: vperm v3, v5, v0, v3 ; P9BE: vperm v2, v3, v2, v0
; P9BE: vabsduw v3, v4, v3 ; P9BE: vperm v0, v3, v1, v0
; P9BE: vabsduw v2, v1, v2 ; P9BE: vperm v3, v3, v1, v4
; P9BE: vadduwm v2, v2, v3 ; P9BE: vabsduw v2, v2, v0
; P9BE: vabsduw v3, v5, v3
; P9BE: vadduwm v2, v3, v2
; P9BE: xxswapd v3, v2 ; P9BE: xxswapd v3, v2
; P9BE: vadduwm v2, v2, v3 ; P9BE: vadduwm v2, v2, v3
; P9BE: xxspltw v3, v2, 1 ; P9BE: xxspltw v3, v2, 1
; P9BE: vadduwm v2, v2, v3 ; P9BE: vadduwm v2, v2, v3
; P9BE: vextuwlx r3, r3, v2 ; P9BE: vextuwlx r3, r3, v2
; P9BE: extsw r3, r3 ; P9BE: extsw r3, r3
; P9BE: blr ; P9BE: blr
entry: entry:
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/scalar_vector_test_2.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; P8BE-NEXT: blr
ret void ret void
} }
define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) { define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
; P9LE-LABEL: test_liwzx2: ; P9LE-LABEL: test_liwzx2:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lfiwzx f0, 0, r3 ; P9LE-NEXT: lfiwzx f0, 0, r3
; P9LE-NEXT: lfiwzx f1, 0, r4 ; P9LE-NEXT: lfiwzx f1, 0, r4
; P9LE-NEXT: mr r3, r5
; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 ; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
; P9LE-NEXT: xxpermdi vs1, f1, f1, 2 ; P9LE-NEXT: xxpermdi vs1, f1, f1, 2
; P9LE-NEXT: xvsubsp vs0, vs0, vs1 ; P9LE-NEXT: xvsubsp vs0, vs0, vs1
; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3 ; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P9LE-NEXT: xscvspdpn f0, vs0 ; P9LE-NEXT: xscvspdpn f0, vs0
; P9LE-NEXT: mr r3, r5
; P9LE-NEXT: stfs f0, 0(r5) ; P9LE-NEXT: stfs f0, 0(r5)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: test_liwzx2: ; P9BE-LABEL: test_liwzx2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lfiwzx f0, 0, r3 ; P9BE-NEXT: lfiwzx f0, 0, r3
; P9BE-NEXT: lfiwzx f1, 0, r4 ; P9BE-NEXT: lfiwzx f1, 0, r4
; P9BE-NEXT: mr r3, r5
; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 ; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
; P9BE-NEXT: xxsldwi vs1, f1, f1, 1 ; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
; P9BE-NEXT: xvsubsp vs0, vs0, vs1 ; P9BE-NEXT: xvsubsp vs0, vs0, vs1
; P9BE-NEXT: xscvspdpn f0, vs0 ; P9BE-NEXT: xscvspdpn f0, vs0
; P9BE-NEXT: mr r3, r5
; P9BE-NEXT: stfs f0, 0(r5) ; P9BE-NEXT: stfs f0, 0(r5)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: test_liwzx2: ; P8LE-LABEL: test_liwzx2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lfiwzx f0, 0, r3 ; P8LE-NEXT: lfiwzx f0, 0, r3
; P8LE-NEXT: lfiwzx f1, 0, r4 ; P8LE-NEXT: lfiwzx f1, 0, r4
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
Show All 25 Lines

llvm/trunk/test/CodeGen/PowerPC/scalar_vector_test_4.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %vecins ret <4 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) { define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f2: ; P9LE-LABEL: s2v_test_f2:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4 ; P9LE-NEXT: addi r3, r3, 4
; P9LE-NEXT: xxspltw v2, v2, 2 ; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-NEXT: lfiwzx f0, 0, r3 ; P9LE-DAG: lfiwzx f0, 0, r3
; P9LE-NEXT: xxpermdi v3, f0, f0, 2 ; P9LE-NEXT: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f2: ; P9BE-LABEL: s2v_test_f2:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4 ; P9BE: addi r3, r3, 4
; P9BE: xxspltw v2, v2, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE: lfiwzx f0, 0, r3 ; P9BE-DAG: lfiwzx f0, 0, r3
; P9BE-NEXT: xxsldwi v3, f0, f0, 1 ; P9BE-NEXT: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2 ; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f2: ; P8LE-LABEL: s2v_test_f2:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4 ; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: xxspltw v2, v2, 2 ; P8LE-NEXT: xxspltw v2, v2, 2
Show All 17 Linesentry:
ret <2 x float> %vecins ret <2 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) { define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) {
; P9LE-LABEL: s2v_test_f3: ; P9LE-LABEL: s2v_test_f3:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r7, 2 ; P9LE-NEXT: sldi r4, r7, 2
; P9LE-NEXT: xxspltw v2, v2, 2
; P9LE-NEXT: lfiwzx f0, r3, r4 ; P9LE-NEXT: lfiwzx f0, r3, r4
; P9LE-NEXT: xxpermdi v3, f0, f0, 2 ; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-DAG: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f3: ; P9BE-LABEL: s2v_test_f3:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: sldi r4, r7, 2 ; P9BE: sldi r4, r7, 2
; P9BE: xxspltw v2, v2, 1
; P9BE: lfiwzx f0, r3, r4 ; P9BE: lfiwzx f0, r3, r4
; P9BE-NEXT: xxsldwi v3, f0, f0, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2 ; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f3: ; P8LE-LABEL: s2v_test_f3:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r7, 2 ; P8LE-NEXT: sldi r4, r7, 2
; P8LE-NEXT: xxspltw v2, v2, 2 ; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: lfiwzx f0, r3, r4 ; P8LE-NEXT: lfiwzx f0, r3, r4
Show All 17 Linesentry:
ret <2 x float> %vecins ret <2 x float> %vecins
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) { define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) {
; P9LE-LABEL: s2v_test_f4: ; P9LE-LABEL: s2v_test_f4:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addi r3, r3, 4 ; P9LE-NEXT: addi r3, r3, 4
; P9LE-NEXT: xxspltw v2, v2, 2
; P9LE-NEXT: lfiwzx f0, 0, r3 ; P9LE-NEXT: lfiwzx f0, 0, r3
; P9LE-NEXT: xxpermdi v3, f0, f0, 2 ; P9LE-DAG: xxspltw v2, v2, 2
; P9LE-DAG: xxpermdi v3, f0, f0, 2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; P9BE-LABEL: s2v_test_f4: ; P9BE-LABEL: s2v_test_f4:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE: addi r3, r3, 4 ; P9BE: addi r3, r3, 4
; P9BE: xxspltw v2, v2, 1
; P9BE: lfiwzx f0, 0, r3 ; P9BE: lfiwzx f0, 0, r3
; P9BE-NEXT: xxsldwi v3, f0, f0, 1 ; P9BE-DAG: xxspltw v2, v2, 1
; P9BE-DAG: xxsldwi v3, f0, f0, 1
; P9BE: vmrghw v2, v3, v2 ; P9BE: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; P8LE-LABEL: s2v_test_f4: ; P8LE-LABEL: s2v_test_f4:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4 ; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: xxspltw v2, v2, 2 ; P8LE-NEXT: xxspltw v2, v2, 2
; P8LE-NEXT: lfiwzx f0, 0, r3 ; P8LE-NEXT: lfiwzx f0, 0, r3
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/store_fptoi.ll

Show First 20 Lines • Show All 290 Lines • ▼ Show 20 Linesentry:
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %b, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %b, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8 store i64 %conv, i64* %arrayidx, align 8
ret void ret void
; CHECK-LABEL: spConv2sdw_x ; CHECK-LABEL: spConv2sdw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3
; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2sdw_x ; CHECK-PWR8-LABEL: spConv2sdw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3
; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sw_x(float* nocapture readonly %a, i32* nocapture %b, define void @spConv2sw_x(float* nocapture readonly %a, i32* nocapture %b,
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
store i32 %conv, i32* %arrayidx, align 4 store i32 %conv, i32* %arrayidx, align 4
ret void ret void
; CHECK-LABEL: spConv2sw_x ; CHECK-LABEL: spConv2sw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2
; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2sw_x ; CHECK-PWR8-LABEL: spConv2sw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2shw_x(float* nocapture readonly %a, i16* nocapture %b, define void @spConv2shw_x(float* nocapture readonly %a, i16* nocapture %b,
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i16 %conv = fptosi float %0 to i16
%idxprom = sext i32 %idx to i64 %idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i16, i16* %b, i64 %idxprom %arrayidx = getelementptr inbounds i16, i16* %b, i64 %idxprom
store i16 %conv, i16* %arrayidx, align 2 store i16 %conv, i16* %arrayidx, align 2
ret void ret void
; CHECK-LABEL: spConv2shw_x ; CHECK-LABEL: spConv2shw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1
; CHECK: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2shw_x ; CHECK-PWR8-LABEL: spConv2shw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
▲ Show 20 Lines • Show All 314 Lines • ▼ Show 20 Linesentry:
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
%idxprom = zext i32 %idx to i64 %idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %b, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %b, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8 store i64 %conv, i64* %arrayidx, align 8
ret void ret void
; CHECK-LABEL: spConv2udw_x ; CHECK-LABEL: spConv2udw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3
; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2udw_x ; CHECK-PWR8-LABEL: spConv2udw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3
; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2uw_x(float* nocapture readonly %a, i32* nocapture %b, define void @spConv2uw_x(float* nocapture readonly %a, i32* nocapture %b,
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
%idxprom = zext i32 %idx to i64 %idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
store i32 %conv, i32* %arrayidx, align 4 store i32 %conv, i32* %arrayidx, align 4
ret void ret void
; CHECK-LABEL: spConv2uw_x ; CHECK-LABEL: spConv2uw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2
; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2uw_x ; CHECK-PWR8-LABEL: spConv2uw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2uhw_x(float* nocapture readonly %a, i16* nocapture %b, define void @spConv2uhw_x(float* nocapture readonly %a, i16* nocapture %b,
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
%idxprom = zext i32 %idx to i64 %idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds i16, i16* %b, i64 %idxprom %arrayidx = getelementptr inbounds i16, i16* %b, i64 %idxprom
store i16 %conv, i16* %arrayidx, align 2 store i16 %conv, i16* %arrayidx, align 2
ret void ret void
; CHECK-LABEL: spConv2uhw_x ; CHECK-LABEL: spConv2uhw_x
; CHECK: lfs [[LD:[0-9]+]], 0(3) ; CHECK: lfs [[LD:[0-9]+]], 0(3)
; CHECK: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1
; CHECK: xscvdpuxws [[CONV:[0-9]+]], [[LD]] ; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] ; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-PWR8-LABEL: spConv2uhw_x ; CHECK-PWR8-LABEL: spConv2uhw_x
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]] ; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
Show All 28 Lines

llvm/trunk/test/CodeGen/PowerPC/stwu-sched.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN ; RUN: --check-prefix=CHECK-ITIN
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
; RUN: --check-prefix=CHECK-ITIN ; RUN: --check-prefix=CHECK-ITIN
%0 = type { i32, i32 } %0 = type { i32, i32 }
; Function Attrs: norecurse nounwind writeonly ; Function Attrs: norecurse nounwind writeonly
define void @initCombList(%0* nocapture, i32 signext) local_unnamed_addr #0 { define void @initCombList(%0* nocapture, i32 signext) local_unnamed_addr #0 {
; CHECK-LABEL: initCombList: ; CHECK-LABEL: initCombList:
; CHECK: addi 3, 3, -8 ; CHECK: addi 4, 4, -8
; CHECK-NEXT: stwu 5, 64(4) ; CHECK: stwu 5, 64(3)
; CHECK-ITIN-LABEL: initCombList: ; CHECK-ITIN-LABEL: initCombList:
; CHECK-ITIN: stwu 5, 64(4) ; CHECK-ITIN: stwu 5, 64(4)
; CHECK-ITIN-NEXT: addi 3, 3, -8 ; CHECK-ITIN-NEXT: addi 3, 3, -8
%3 = zext i32 %1 to i64 %3 = zext i32 %1 to i64
br i1 undef, label %6, label %4 br i1 undef, label %6, label %4
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll

; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -O3 < %s | FileCheck %s ; RUN: -O3 < %s | FileCheck %s
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ ; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mattr=-power9-vector < %s | FileCheck %s ; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR
; These tests verify that VSX swap optimization works when loading a scalar ; These tests verify that VSX swap optimization works when loading a scalar
; into a vector register. ; into a vector register.
@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 @x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 @z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
@y = global double 1.780000e+00, align 8 @y = global double 1.780000e+00, align 8
define void @bar0() { define void @bar0() {
; CHECK-LABEL: bar0: ; CHECK-LABEL: bar0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: addis r3, r2, .LC0@toc@ha ; CHECK: addis r3, r2, .LC0@toc@ha
; CHECK: addis r4, r2, .LC1@toc@ha ; CHECK: addis r4, r2, .LC1@toc@ha
; CHECK: ld r3, .LC0@toc@l(r3) ; CHECK: ld r3, .LC0@toc@l(r3)
; CHECK: addis r3, r2, .LC2@toc@ha ; CHECK: addis r3, r2, .LC2@toc@ha
; CHECK: ld r3, .LC2@toc@l(r3) ; CHECK: ld r3, .LC2@toc@l(r3)
; CHECK: xxpermdi vs0, vs0, vs1, 1 ; CHECK: xxpermdi vs0, vs0, vs1, 1
; CHECK: stxvd2x vs0, 0, r3 ; CHECK: stxvd2x vs0, 0, r3
; CHECK: blr ; CHECK: blr
; ;
; CHECK-P9-NOVECTOR-LABEL: bar0:
; CHECK-P9-NOVECTOR: # %bb.0: # %entry
; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
; CHECK-P9-NOVECTOR: xxpermdi vs0, vs1, vs0, 1
; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
; CHECK-P9-NOVECTOR: blr
;
; CHECK-P9-LABEL: bar0: ; CHECK-P9-LABEL: bar0:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: addis r4, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3) ; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: ld r4, .LC1@toc@l(r4) ; CHECK-P9: lxvx vs0, 0, r3
; CHECK-P9: lfd f0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: lxvx vs1, 0, r4 ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: lfd f1, 0(r3)
; CHECK-P9: addis r3, r2, .LC2@toc@ha ; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxpermdi vs0, f0, f0, 2 ; CHECK-P9: xxpermdi vs1, f1, f1, 2
; CHECK-P9: xxpermdi vs0, vs1, vs0, 1 ; CHECK-P9: xxpermdi vs0, vs0, vs1, 1
; CHECK-P9: stxvx vs0, 0, r3 ; CHECK-P9: stxvx vs0, 0, r3
; CHECK-P9: blr ; CHECK-P9: blr
entry: entry:
%0 = load <2 x double>, <2 x double>* @x, align 16 %0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 0 %vecins = insertelement <2 x double> %0, double %1, i32 0
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }
define void @bar1() { define void @bar1() {
; CHECK-LABEL: bar1: ; CHECK-LABEL: bar1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: addis r3, r2, .LC0@toc@ha ; CHECK: addis r3, r2, .LC0@toc@ha
; CHECK: addis r4, r2, .LC1@toc@ha ; CHECK: addis r4, r2, .LC1@toc@ha
; CHECK: ld r3, .LC0@toc@l(r3) ; CHECK: ld r3, .LC0@toc@l(r3)
; CHECK: addis r3, r2, .LC2@toc@ha ; CHECK: addis r3, r2, .LC2@toc@ha
; CHECK: ld r3, .LC2@toc@l(r3) ; CHECK: ld r3, .LC2@toc@l(r3)
; CHECK: xxmrghd vs0, vs1, vs0 ; CHECK: xxmrghd vs0, vs1, vs0
; CHECK: stxvd2x vs0, 0, r3 ; CHECK: stxvd2x vs0, 0, r3
; CHECK: blr ; CHECK: blr
; ;
; CHECK-P9-NOVECTOR-LABEL: bar1:
; CHECK-P9-NOVECTOR: # %bb.0: # %entry
; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
; CHECK-P9-NOVECTOR: xxmrghd vs0, vs0, vs1
; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
; CHECK-P9-NOVECTOR: blr
;
; CHECK-P9-LABEL: bar1: ; CHECK-P9-LABEL: bar1:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: addis r4, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3) ; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: ld r4, .LC1@toc@l(r4) ; CHECK-P9: lxvx vs0, 0, r3
; CHECK-P9: lfd f0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: lxvx vs1, 0, r4 ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: lfd f1, 0(r3)
; CHECK-P9: addis r3, r2, .LC2@toc@ha ; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxpermdi vs0, f0, f0, 2 ; CHECK-P9: xxpermdi vs1, f1, f1, 2
; CHECK-P9: xxmrgld vs0, vs0, vs1 ; CHECK-P9: xxmrgld vs0, vs1, vs0
; CHECK-P9: stxvx vs0, 0, r3 ; CHECK-P9: stxvx vs0, 0, r3
; CHECK-P9: blr ; CHECK-P9: blr
entry: entry:
%0 = load <2 x double>, <2 x double>* @x, align 16 %0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 1 %vecins = insertelement <2 x double> %0, double %1, i32 1
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec-itofp.ll

Show All 10 Lines
define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = uitofp <8 x i16> %0 to <8 x double> %1 = uitofp <8 x i16> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %Sink, align 16 store <8 x double> %1, <8 x double>* %Sink, align 16
ret void ret void
; CHECK-P9-LABEL: @test8 ; CHECK-P9-LABEL: @test8
; CHECK-P9: vperm ; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P8-LABEL: @test8 ; CHECK-P8-LABEL: @test8
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
} }
define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = uitofp <4 x i16> %0 to <4 x double> %1 = uitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %Sink, align 16 store <4 x double> %1, <4 x double>* %Sink, align 16
ret void ret void
; CHECK-P9-LABEL: @test4 ; CHECK-P9-LABEL: @test4
; CHECK-P9: vperm ; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P9: vperm
; CHECK-P9: xvcvuxddp ; CHECK-P9: xvcvuxddp
; CHECK-P8-LABEL: @test4 ; CHECK-P8-LABEL: @test4
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: vperm ; CHECK-P8: vperm
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
; CHECK-P8: xvcvuxddp ; CHECK-P8: xvcvuxddp
} }
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define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = sitofp <8 x i16> %0 to <8 x double> %1 = sitofp <8 x i16> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %Sink, align 16 store <8 x double> %1, <8 x double>* %Sink, align 16
ret void ret void
; CHECK-P9-LABEL: @stest8 ; CHECK-P9-LABEL: @stest8
; CHECK-P9: vperm ; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: vextsh2d
; CHECK-P9: vextsh2d
; CHECK-P9: vextsh2d ; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
} }
define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = sitofp <4 x i16> %0 to <4 x double> %1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %Sink, align 16 store <4 x double> %1, <4 x double>* %Sink, align 16
ret void ret void
; CHECK-P9-LABEL: @stest4 ; CHECK-P9-LABEL: @stest4
; CHECK-P9: vperm ; CHECK-P9: vperm
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: vextsh2d ; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
; CHECK-P9: vperm
; CHECK-P9: vextsh2d
; CHECK-P9: xvcvsxddp ; CHECK-P9: xvcvsxddp
} }
define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
entry: entry:
%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16 %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
%1 = sitofp <2 x i16> %0 to <2 x double> %1 = sitofp <2 x i16> %0 to <2 x double>
store <2 x double> %1, <2 x double>* %Sink, align 16 store <2 x double> %1, <2 x double>* %Sink, align 16
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

Show All 30 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i16> %1 = fptoui <2 x float> %0 to <2 x i16>
%2 = bitcast <2 x i16> %1 to i32 %2 = bitcast <2 x i16> %1 to i32
ret i32 %2 ret i32 %2
Show All 30 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v4, v5
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xxswapd vs1, v2
; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-BE-NEXT: xscvspdpn f3, v2
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: mfvsrwz r6, f2 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r6, r6, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v4, v5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <4 x float> %a to <4 x i16> %0 = fptoui <4 x float> %a to <4 x i16>
%1 = bitcast <4 x i16> %0 to i64 %1 = bitcast <4 x i16> %0 to i64
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v1, v6 ; CHECK-P8-NEXT: vmrglh v5, v1, v6
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r9, f0
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mfvsrwz r7, f5 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mfvsrwz r8, f6 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: mfvsrwz r10, f7 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f6, r9 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: mtvsrd f4, r7 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v1, vs5 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v7, vs7 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v4, v1, v0 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglh v5, v6, v7
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs6, vs0
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r6, r6, 48
; CHECK-BE-NEXT: sldi r7, r7, 48
; CHECK-BE-NEXT: sldi r8, r8, 48
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: mtvsrd v1, r8 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: mtvsrd v7, r10 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: vmrghh v4, v1, v0 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghh v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptoui <8 x float> %a to <8 x i16> %1 = fptoui <8 x float> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: xscvspdpn f5, vs1
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xscvspdpn f8, vs3
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs4, vs1
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs5, vs3
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs11, vs1
; CHECK-P9-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs7, vs3
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvspdpn f11, vs11
; CHECK-P9-NEXT: xscvspdpn f12, vs12
; CHECK-P9-NEXT: xscvspdpn f13, vs13
; CHECK-P9-NEXT: xscvspdpn v2, v2
; CHECK-P9-NEXT: xscvspdpn v3, v3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpsxws f11, f11 ; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xscvdpsxws f12, f12 ; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f13, f13 ; CHECK-P9-NEXT: mtvsrd f4, r5
; CHECK-P9-NEXT: xscvdpsxws v2, v2 ; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r4, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: mfvsrwz r12, f1
; CHECK-P9-NEXT: mfvsrwz r0, f0
; CHECK-P9-NEXT: mfvsrwz r6, f4
; CHECK-P9-NEXT: mfvsrwz r7, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r9, f7
; CHECK-P9-NEXT: mfvsrwz r10, f8
; CHECK-P9-NEXT: mfvsrwz r11, f9
; CHECK-P9-NEXT: mfvsrwz r30, f10
; CHECK-P9-NEXT: mfvsrwz r29, f11
; CHECK-P9-NEXT: mfvsrwz r28, f12
; CHECK-P9-NEXT: mfvsrwz r27, f13
; CHECK-P9-NEXT: mfvsrwz r26, v2
; CHECK-P9-NEXT: mfvsrwz r25, v3
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtvsrd f1, r5
; CHECK-P9-NEXT: mtvsrd f8, r12 ; CHECK-P9-NEXT: mfvsrwz r5, f6
; CHECK-P9-NEXT: mtvsrd f9, r0 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f2, r6 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: mtvsrd f3, r7 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: mtvsrd f4, r8 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrd f5, r9 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: mtvsrd f6, r10 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r11 ; CHECK-P9-NEXT: mtvsrd f6, r5
; CHECK-P9-NEXT: mtvsrd f10, r30 ; CHECK-P9-NEXT: mfvsrwz r5, f7
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: mtvsrd f11, r29 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mtvsrd f12, r28 ; CHECK-P9-NEXT: xxswapd v3, vs5
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: mtvsrd f7, r5
; CHECK-P9-NEXT: mtvsrd f13, r27 ; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: mtvsrd v2, r26 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xxswapd v5, vs7
; CHECK-P9-NEXT: mtvsrd v3, r25 ; CHECK-P9-NEXT: mtvsrd f3, r5
; CHECK-P9-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: xxswapd v1, vs4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v6, vs5 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v7, vs6 ; CHECK-P9-NEXT: vmrglh v5, v5, v0
; CHECK-P9-NEXT: xxswapd v8, vs1 ; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: xxswapd v9, vs7 ; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: xxswapd v10, vs10 ; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: xxswapd v11, vs11
; CHECK-P9-NEXT: xxswapd v12, vs8
; CHECK-P9-NEXT: xxswapd v13, vs12
; CHECK-P9-NEXT: xxswapd v14, vs13
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs9
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglh v5, v0, v5
; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: vmrglh v0, v7, v6
; CHECK-P9-NEXT: vmrglh v1, v8, v9
; CHECK-P9-NEXT: vmrglh v6, v11, v10
; CHECK-P9-NEXT: vmrglh v7, v12, v13
; CHECK-P9-NEXT: vmrglh v2, v2, v14
; CHECK-P9-NEXT: vmrglh v3, v15, v3
; CHECK-P9-NEXT: vmrglw v4, v4, v5
; CHECK-P9-NEXT: vmrglw v5, v1, v0
; CHECK-P9-NEXT: vmrglw v0, v7, v6
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxmrgld vs0, v5, v4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxmrgld vs1, v2, v0 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f10
; CHECK-P9-NEXT: mtvsrd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 16(r4) ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs5, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs8, vs2
; CHECK-BE-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs11, vs1
; CHECK-BE-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd v2, vs0
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xscvspdpn f9, vs9
; CHECK-BE-NEXT: xscvspdpn f10, vs10
; CHECK-BE-NEXT: xscvspdpn f11, vs11
; CHECK-BE-NEXT: xscvspdpn f12, vs12
; CHECK-BE-NEXT: xscvspdpn f13, vs13
; CHECK-BE-NEXT: xscvspdpn v2, v2
; CHECK-BE-NEXT: xscvspdpn v3, v3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r12, f1
; CHECK-BE-NEXT: mfvsrwz r0, f0
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r9, f7
; CHECK-BE-NEXT: mfvsrwz r10, f8
; CHECK-BE-NEXT: mfvsrwz r11, f9
; CHECK-BE-NEXT: mfvsrwz r30, f10
; CHECK-BE-NEXT: mfvsrwz r29, f11
; CHECK-BE-NEXT: mfvsrwz r28, f12
; CHECK-BE-NEXT: mfvsrwz r27, f13
; CHECK-BE-NEXT: mfvsrwz r26, v2
; CHECK-BE-NEXT: mfvsrwz r25, v3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r12, r12, 48 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: sldi r0, r0, 48 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: sldi r7, r7, 48 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: sldi r8, r8, 48 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r9, r9, 48 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: sldi r10, r10, 48 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r11, r11, 48 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: sldi r30, r30, 48 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: sldi r29, r29, 48 ; CHECK-BE-NEXT: mfvsrwz r4, f5
; CHECK-BE-NEXT: sldi r28, r28, 48 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r27, r27, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r26, r26, 48
; CHECK-BE-NEXT: sldi r25, r25, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mtvsrd v10, r12 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v14, r0 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: mtvsrd v4, r6 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r7 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v0, r8 ; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: mtvsrd v1, r9 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v6, r10 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mtvsrd v7, r11 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v8, r30 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v9, r29 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v11, r28 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mtvsrd v12, r27 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: mtvsrd v13, r26 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v15, r25 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v0 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v5, v6, v1 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v7 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: vmrghh v0, v9, v8 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: vmrghh v1, v10, v11 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v6, v13, v12 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v7, v14, v15 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: vmrghw v2, v2, v4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghw v3, v3, v5 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghw v4, v1, v0 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v5, v7, v6 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: xxmrghd vs1, v5, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i16> %1 = fptoui <16 x float> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }
Show All 19 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptosi <2 x float> %0 to <2 x i16> %1 = fptosi <2 x float> %0 to <2 x i16>
%2 = bitcast <2 x i16> %1 to i32 %2 = bitcast <2 x i16> %1 to i32
ret i32 %2 ret i32 %2
Show All 30 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v4, v5
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xxswapd vs1, v2
; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-BE-NEXT: xscvspdpn f3, v2
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: mfvsrwz r6, f2 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r6, r6, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v4, v5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <4 x float> %a to <4 x i16> %0 = fptosi <4 x float> %a to <4 x i16>
%1 = bitcast <4 x i16> %0 to i64 %1 = bitcast <4 x i16> %0 to i64
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v1, v6 ; CHECK-P8-NEXT: vmrglh v5, v1, v6
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r9, f0
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mfvsrwz r7, f5 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mfvsrwz r8, f6 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: mfvsrwz r10, f7 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f6, r9 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: mtvsrd f4, r7 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v1, vs5 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v7, vs7 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v4, v1, v0 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglh v5, v6, v7
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs6, vs0
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r6, r6, 48
; CHECK-BE-NEXT: sldi r7, r7, 48
; CHECK-BE-NEXT: sldi r8, r8, 48
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: mtvsrd v1, r8 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: mtvsrd v7, r10 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: vmrghh v4, v1, v0 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghh v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptosi <8 x float> %a to <8 x i16> %1 = fptosi <8 x float> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: xscvspdpn f5, vs1
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xscvspdpn f8, vs3
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs4, vs1
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs5, vs3
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs11, vs1
; CHECK-P9-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs7, vs3
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvspdpn f11, vs11
; CHECK-P9-NEXT: xscvspdpn f12, vs12
; CHECK-P9-NEXT: xscvspdpn f13, vs13
; CHECK-P9-NEXT: xscvspdpn v2, v2
; CHECK-P9-NEXT: xscvspdpn v3, v3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpsxws f11, f11 ; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xscvdpsxws f12, f12 ; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: xscvdpsxws f13, f13 ; CHECK-P9-NEXT: mtvsrd f4, r5
; CHECK-P9-NEXT: xscvdpsxws v2, v2 ; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r4, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: mfvsrwz r12, f1
; CHECK-P9-NEXT: mfvsrwz r0, f0
; CHECK-P9-NEXT: mfvsrwz r6, f4
; CHECK-P9-NEXT: mfvsrwz r7, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r9, f7
; CHECK-P9-NEXT: mfvsrwz r10, f8
; CHECK-P9-NEXT: mfvsrwz r11, f9
; CHECK-P9-NEXT: mfvsrwz r30, f10
; CHECK-P9-NEXT: mfvsrwz r29, f11
; CHECK-P9-NEXT: mfvsrwz r28, f12
; CHECK-P9-NEXT: mfvsrwz r27, f13
; CHECK-P9-NEXT: mfvsrwz r26, v2
; CHECK-P9-NEXT: mfvsrwz r25, v3
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtvsrd f1, r5
; CHECK-P9-NEXT: mtvsrd f8, r12 ; CHECK-P9-NEXT: mfvsrwz r5, f6
; CHECK-P9-NEXT: mtvsrd f9, r0 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f2, r6 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: mtvsrd f3, r7 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: mtvsrd f4, r8 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrd f5, r9 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: mtvsrd f6, r10 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r11 ; CHECK-P9-NEXT: mtvsrd f6, r5
; CHECK-P9-NEXT: mtvsrd f10, r30 ; CHECK-P9-NEXT: mfvsrwz r5, f7
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: mtvsrd f11, r29 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mtvsrd f12, r28 ; CHECK-P9-NEXT: xxswapd v3, vs5
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: mtvsrd f7, r5
; CHECK-P9-NEXT: mtvsrd f13, r27 ; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: mtvsrd v2, r26 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xxswapd v5, vs7
; CHECK-P9-NEXT: mtvsrd v3, r25 ; CHECK-P9-NEXT: mtvsrd f3, r5
; CHECK-P9-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: xxswapd v1, vs4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v6, vs5 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v7, vs6 ; CHECK-P9-NEXT: vmrglh v5, v5, v0
; CHECK-P9-NEXT: xxswapd v8, vs1 ; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: xxswapd v9, vs7 ; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: xxswapd v10, vs10 ; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: xxswapd v11, vs11
; CHECK-P9-NEXT: xxswapd v12, vs8
; CHECK-P9-NEXT: xxswapd v13, vs12
; CHECK-P9-NEXT: xxswapd v14, vs13
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs9
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglh v5, v0, v5
; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: vmrglh v0, v7, v6
; CHECK-P9-NEXT: vmrglh v1, v8, v9
; CHECK-P9-NEXT: vmrglh v6, v11, v10
; CHECK-P9-NEXT: vmrglh v7, v12, v13
; CHECK-P9-NEXT: vmrglh v2, v2, v14
; CHECK-P9-NEXT: vmrglh v3, v15, v3
; CHECK-P9-NEXT: vmrglw v4, v4, v5
; CHECK-P9-NEXT: vmrglw v5, v1, v0
; CHECK-P9-NEXT: vmrglw v0, v7, v6
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxmrgld vs0, v5, v4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxmrgld vs1, v2, v0 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f10
; CHECK-P9-NEXT: mtvsrd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 16(r4) ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs5, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs8, vs2
; CHECK-BE-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs11, vs1
; CHECK-BE-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd v2, vs0
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xscvspdpn f9, vs9
; CHECK-BE-NEXT: xscvspdpn f10, vs10
; CHECK-BE-NEXT: xscvspdpn f11, vs11
; CHECK-BE-NEXT: xscvspdpn f12, vs12
; CHECK-BE-NEXT: xscvspdpn f13, vs13
; CHECK-BE-NEXT: xscvspdpn v2, v2
; CHECK-BE-NEXT: xscvspdpn v3, v3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r12, f1
; CHECK-BE-NEXT: mfvsrwz r0, f0
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r9, f7
; CHECK-BE-NEXT: mfvsrwz r10, f8
; CHECK-BE-NEXT: mfvsrwz r11, f9
; CHECK-BE-NEXT: mfvsrwz r30, f10
; CHECK-BE-NEXT: mfvsrwz r29, f11
; CHECK-BE-NEXT: mfvsrwz r28, f12
; CHECK-BE-NEXT: mfvsrwz r27, f13
; CHECK-BE-NEXT: mfvsrwz r26, v2
; CHECK-BE-NEXT: mfvsrwz r25, v3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r12, r12, 48 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: sldi r0, r0, 48 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: sldi r7, r7, 48 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: sldi r8, r8, 48 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r9, r9, 48 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: sldi r10, r10, 48 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r11, r11, 48 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: sldi r30, r30, 48 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: sldi r29, r29, 48 ; CHECK-BE-NEXT: mfvsrwz r4, f5
; CHECK-BE-NEXT: sldi r28, r28, 48 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r27, r27, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r26, r26, 48
; CHECK-BE-NEXT: sldi r25, r25, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mtvsrd v10, r12 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v14, r0 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: mtvsrd v4, r6 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r7 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v0, r8 ; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: mtvsrd v1, r9 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v6, r10 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mtvsrd v7, r11 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v8, r30 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v9, r29 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v11, r28 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mtvsrd v12, r27 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: mtvsrd v13, r26 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v15, r25 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v0 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v5, v6, v1 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v7 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: vmrghh v0, v9, v8 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: vmrghh v1, v10, v11 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghh v6, v13, v12 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v7, v14, v15 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: vmrghw v2, v2, v4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghw v3, v3, v5 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghw v4, v1, v0 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v5, v7, v6 ; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: xxmrghd vs1, v5, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptosi <16 x float> %a to <16 x i16> %1 = fptosi <16 x float> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

Show All 29 Lines
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1 ; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i64> %1 = fptoui <2 x float> %0 to <2 x i64>
ret <2 x i64> %1 ret <2 x i64> %1
} }
Show All 17 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2 ; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs1, vs3, vs2 ; CHECK-P9-NEXT: xscvspdpn f1, v2
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: xxswapd vs2, v2 ; CHECK-BE-NEXT: xxswapd vs2, v2
; CHECK-BE-NEXT: xscvspdpn f3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxmrghd vs0, vs3, vs0
; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <4 x float> %a to <4 x i64> %0 = fptoui <4 x float> %a to <4 x i64>
store <4 x i64> %0, <4 x i64>* %agg.result, align 32 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
ret void ret void
} }
define void @test8elt(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
Show All 33 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxswapd vs2, vs0
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: xxmrghd vs0, vs3, vs0
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs4, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xxmrghd vs3, vs4, vs3
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f4, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs4 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxmrghd vs3, vs6, vs5
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs7
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xxmrghd vs2, vs4, vs2
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: stxv vs3, 32(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs2, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs4, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs3
; CHECK-BE-NEXT: xscvspdpn f3, vs0
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs4
; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs4
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs4, vs3
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
; CHECK-BE-NEXT: xxmrghd vs3, vs7, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 32(r3) ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 16(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptoui <8 x float> %a to <8 x i64> %1 = fptoui <8 x float> %a to <8 x i64>
store <8 x i64> %1, <8 x i64>* %agg.result, align 64 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r7
; CHECK-P8-NEXT: stxvd2x vs4, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r6
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs4, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxsldwi vs5, vs4, vs4, 3
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: xxswapd vs6, vs4
; CHECK-P9-NEXT: lxv vs3, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs2, vs0
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs5, vs1
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs8, vs0
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs11, vs3
; CHECK-P9-NEXT: xxsldwi vs12, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxsldwi v3, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxmrghd vs5, vs6, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs4
; CHECK-P9-NEXT: xxsldwi vs4, vs4, vs4, 1
; CHECK-P9-NEXT: lxv vs3, 32(r4)
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxswapd vs7, vs3
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f9, vs9 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f10, vs10 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f11, vs11 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xscvspdpn f12, vs12 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f13, vs13 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f31, v2 ; CHECK-P9-NEXT: xxmrghd vs0, vs2, vs0
; CHECK-P9-NEXT: xscvspdpn f30, v3 ; CHECK-P9-NEXT: xxmrghd vs4, vs6, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs6
; CHECK-P9-NEXT: xxmrghd vs5, vs8, vs7
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs9
; CHECK-P9-NEXT: xxmrghd vs6, vs11, vs10
; CHECK-P9-NEXT: xxmrghd vs3, vs3, vs12
; CHECK-P9-NEXT: xxmrghd vs7, vs31, vs13
; CHECK-P9-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxmrghd vs2, vs2, vs30
; CHECK-P9-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs3
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: lxv vs2, 48(r4)
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xscvspdpn f8, vs8
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: stxv vs6, 64(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: stxv vs3, 80(r3)
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: stxv vs2, 112(r3) ; CHECK-P9-NEXT: stxv vs2, 112(r3)
; CHECK-P9-NEXT: stxv vs7, 96(r3) ; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs3, 80(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs6, 64(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs4, 16(r4)
; CHECK-BE-NEXT: lxv vs2, 48(r4) ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 1
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xxsldwi vs8, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs9, vs0
; CHECK-BE-NEXT: xxsldwi vs10, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs11, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs12, vs3
; CHECK-BE-NEXT: xxsldwi vs13, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi v2, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd v3, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 1
; CHECK-BE-NEXT: xscvspdpn f6, vs6 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
; CHECK-BE-NEXT: xscvspdpn f5, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 1
; CHECK-BE-NEXT: xscvspdpn f7, vs7 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xxmrghd vs5, vs5, vs6
; CHECK-BE-NEXT: xscvspdpn f9, vs9 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 3
; CHECK-BE-NEXT: xscvspdpn f10, vs10 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: xscvspdpn f11, vs11 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f12, vs12 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f13, vs13 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f31, v2 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-BE-NEXT: xscvspdpn f30, v3 ; CHECK-BE-NEXT: lxv vs2, 48(r4)
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs4 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 1
; CHECK-BE-NEXT: xxmrghd vs4, vs6, vs5
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs7
; CHECK-BE-NEXT: xxmrghd vs5, vs9, vs8
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs10
; CHECK-BE-NEXT: xxmrghd vs6, vs12, vs11
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs13
; CHECK-BE-NEXT: xxmrghd vs7, vs30, vs31
; CHECK-BE-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
; CHECK-BE-NEXT: xscvspdpn f6, vs3
; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xxmrghd vs6, vs6, vs7
; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs7
; CHECK-BE-NEXT: xscvspdpn f7, vs2
; CHECK-BE-NEXT: xxmrghd vs7, vs7, vs8
; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs8
; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
; CHECK-BE-NEXT: stxv vs5, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 80(r3)
; CHECK-BE-NEXT: stxv vs0, 32(r3) ; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs4, 16(r3) ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: stxv vs2, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 48(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 96(r3)
; CHECK-BE-NEXT: stxv vs6, 80(r3)
; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i64> %1 = fptoui <16 x float> %a to <16 x i64>
store <16 x i64> %1, <16 x i64>* %agg.result, align 128 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
ret void ret void
} }
Show All 18 Lines
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1 ; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i64> %1 = fptoui <2 x float> %0 to <2 x i64>
ret <2 x i64> %1 ret <2 x i64> %1
} }
Show All 17 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2 ; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs1, vs3, vs2 ; CHECK-P9-NEXT: xscvspdpn f1, v2
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: xxswapd vs2, v2 ; CHECK-BE-NEXT: xxswapd vs2, v2
; CHECK-BE-NEXT: xscvspdpn f3, v2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxmrghd vs0, vs3, vs0
; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <4 x float> %a to <4 x i64> %0 = fptoui <4 x float> %a to <4 x i64>
store <4 x i64> %0, <4 x i64>* %agg.result, align 32 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
ret void ret void
} }
define void @test8elt_signed(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
Show All 33 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxswapd vs2, vs0
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: xxmrghd vs0, vs3, vs0
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs4, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xxmrghd vs3, vs4, vs3
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f4, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs4 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxmrghd vs3, vs6, vs5
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs7
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xxmrghd vs2, vs4, vs2
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: stxv vs3, 32(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs2, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs4, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs3
; CHECK-BE-NEXT: xscvspdpn f3, vs0
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs4
; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs4
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs4, vs3
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
; CHECK-BE-NEXT: xxmrghd vs3, vs7, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 32(r3) ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 16(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptoui <8 x float> %a to <8 x i64> %1 = fptoui <8 x float> %a to <8 x i64>
store <8 x i64> %1, <8 x i64>* %agg.result, align 64 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r7
; CHECK-P8-NEXT: stxvd2x vs4, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r6
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs4, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxsldwi vs5, vs4, vs4, 3
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: xxswapd vs6, vs4
; CHECK-P9-NEXT: lxv vs3, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs2, vs0
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs5, vs1
; CHECK-P9-NEXT: xxsldwi vs6, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs8, vs0
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs11, vs3
; CHECK-P9-NEXT: xxsldwi vs12, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxsldwi v3, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5 ; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxmrghd vs5, vs6, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs4
; CHECK-P9-NEXT: xxsldwi vs4, vs4, vs4, 1
; CHECK-P9-NEXT: lxv vs3, 32(r4)
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xxswapd vs7, vs3
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f9, vs9 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f10, vs10 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f11, vs11 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xscvspdpn f12, vs12 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f13, vs13 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f31, v2 ; CHECK-P9-NEXT: xxmrghd vs0, vs2, vs0
; CHECK-P9-NEXT: xscvspdpn f30, v3 ; CHECK-P9-NEXT: xxmrghd vs4, vs6, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs6
; CHECK-P9-NEXT: xxmrghd vs5, vs8, vs7
; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs9
; CHECK-P9-NEXT: xxmrghd vs6, vs11, vs10
; CHECK-P9-NEXT: xxmrghd vs3, vs3, vs12
; CHECK-P9-NEXT: xxmrghd vs7, vs31, vs13
; CHECK-P9-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxmrghd vs2, vs2, vs30
; CHECK-P9-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs3
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: lxv vs2, 48(r4)
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xscvspdpn f8, vs8
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: stxv vs6, 64(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: stxv vs3, 80(r3)
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: stxv vs2, 112(r3) ; CHECK-P9-NEXT: stxv vs2, 112(r3)
; CHECK-P9-NEXT: stxv vs7, 96(r3) ; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs3, 80(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs6, 64(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs4, 16(r4)
; CHECK-BE-NEXT: lxv vs2, 48(r4) ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 1
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xxsldwi vs8, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs9, vs0
; CHECK-BE-NEXT: xxsldwi vs10, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs11, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs12, vs3
; CHECK-BE-NEXT: xxsldwi vs13, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi v2, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd v3, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 1
; CHECK-BE-NEXT: xscvspdpn f6, vs6 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
; CHECK-BE-NEXT: xscvspdpn f5, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 1
; CHECK-BE-NEXT: xscvspdpn f7, vs7 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xxmrghd vs5, vs5, vs6
; CHECK-BE-NEXT: xscvspdpn f9, vs9 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 3
; CHECK-BE-NEXT: xscvspdpn f10, vs10 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: xscvspdpn f11, vs11 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f12, vs12 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f13, vs13 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f31, v2 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
; CHECK-BE-NEXT: xscvspdpn f30, v3 ; CHECK-BE-NEXT: lxv vs2, 48(r4)
; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs4 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 1
; CHECK-BE-NEXT: xxmrghd vs4, vs6, vs5
; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs7
; CHECK-BE-NEXT: xxmrghd vs5, vs9, vs8
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs10
; CHECK-BE-NEXT: xxmrghd vs6, vs12, vs11
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs13
; CHECK-BE-NEXT: xxmrghd vs7, vs30, vs31
; CHECK-BE-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
; CHECK-BE-NEXT: xscvspdpn f6, vs3
; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xxmrghd vs6, vs6, vs7
; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs7
; CHECK-BE-NEXT: xscvspdpn f7, vs2
; CHECK-BE-NEXT: xxmrghd vs7, vs7, vs8
; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvspdpn f8, vs8
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs8
; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
; CHECK-BE-NEXT: stxv vs5, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 80(r3)
; CHECK-BE-NEXT: stxv vs0, 32(r3) ; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs4, 16(r3) ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: stxv vs2, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 48(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 96(r3)
; CHECK-BE-NEXT: stxv vs6, 80(r3)
; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i64> %1 = fptoui <16 x float> %a to <16 x i64>
store <16 x i64> %1, <16 x i64>* %agg.result, align 128 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

Show All 33 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i8> %1 = fptoui <2 x float> %0 to <2 x i8>
Show All 32 Lines
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v3, v4, v5
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xxswapd vs1, v2
; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-BE-NEXT: xscvspdpn f3, v2
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: mfvsrwz r6, f2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v4, v2
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <4 x float> %a to <4 x i8> %0 = fptoui <4 x float> %a to <4 x i8>
%1 = bitcast <4 x i8> %0 to i32 %1 = bitcast <4 x i8> %0 to i32
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r9, f0
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mfvsrwz r7, f5 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mfvsrwz r8, f6 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: mfvsrwz r10, f7 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f6, r9 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: mtvsrd f4, r7 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v1, vs5 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v7, vs7 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v4, v1, v0 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglb v5, v6, v7
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs6, vs0
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: mfvsrwz r6, f4 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r7, f5 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: mtvsrd v1, r8 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: mtvsrd v7, r10 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: vmrghb v4, v1, v0 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptoui <8 x float> %a to <8 x i8> %1 = fptoui <8 x float> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v7, v6 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 0(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs5, vs3
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs11, vs1
; CHECK-P9-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs2, 48(r3)
; CHECK-P9-NEXT: lxv vs3, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvspdpn f11, vs11
; CHECK-P9-NEXT: xscvspdpn f12, vs12
; CHECK-P9-NEXT: xscvspdpn f13, vs13
; CHECK-P9-NEXT: xscvspdpn v2, v2
; CHECK-P9-NEXT: xscvspdpn v3, v3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r11, f1
; CHECK-P9-NEXT: mfvsrwz r12, f0
; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r7, f6
; CHECK-P9-NEXT: mfvsrwz r8, f7
; CHECK-P9-NEXT: mfvsrwz r9, f8
; CHECK-P9-NEXT: mfvsrwz r10, f9
; CHECK-P9-NEXT: mfvsrwz r0, f10
; CHECK-P9-NEXT: mfvsrwz r30, f11
; CHECK-P9-NEXT: mfvsrwz r29, f12
; CHECK-P9-NEXT: mfvsrwz r28, f13
; CHECK-P9-NEXT: mfvsrwz r27, v2
; CHECK-P9-NEXT: mfvsrwz r26, v3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f8, r11
; CHECK-P9-NEXT: mtvsrd f9, r12
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f5, r8
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: mtvsrd f7, r10
; CHECK-P9-NEXT: mtvsrd f10, r0
; CHECK-P9-NEXT: mtvsrd f11, r30
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd f12, r29
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd f13, r28
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd v2, r27
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd v3, r26
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxsldwi vs0, vs4, vs4, 3
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxswapd v1, vs4 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v6, vs5 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v7, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v8, vs1 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs10
; CHECK-P9-NEXT: xxswapd v11, vs11
; CHECK-P9-NEXT: xxswapd v12, vs8
; CHECK-P9-NEXT: xxswapd v13, vs12
; CHECK-P9-NEXT: xxswapd v14, vs13
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs9
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglb v5, v0, v5
; CHECK-P9-NEXT: vmrglb v4, v4, v1
; CHECK-P9-NEXT: vmrglb v0, v7, v6
; CHECK-P9-NEXT: vmrglb v1, v8, v9
; CHECK-P9-NEXT: vmrglb v6, v11, v10
; CHECK-P9-NEXT: vmrglb v7, v12, v13
; CHECK-P9-NEXT: vmrglb v2, v2, v14
; CHECK-P9-NEXT: vmrglb v3, v15, v3
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglh v5, v1, v0
; CHECK-P9-NEXT: vmrglh v0, v7, v6
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxmrgld v2, v2, v3 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs4
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs5, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs8, vs2
; CHECK-BE-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs11, vs1
; CHECK-BE-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd v2, vs0
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvspdpn f6, vs6 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f7, vs7 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xscvspdpn f9, vs9 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: xscvspdpn f10, vs10 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f11, vs11 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f12, vs12 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f13, vs13 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvspdpn v2, v2
; CHECK-BE-NEXT: xscvspdpn v3, v3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mfvsrwz r11, f1
; CHECK-BE-NEXT: mfvsrwz r12, f0
; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r7, f6
; CHECK-BE-NEXT: mfvsrwz r8, f7
; CHECK-BE-NEXT: mfvsrwz r9, f8
; CHECK-BE-NEXT: mfvsrwz r10, f9
; CHECK-BE-NEXT: mfvsrwz r0, f10
; CHECK-BE-NEXT: mfvsrwz r30, f11
; CHECK-BE-NEXT: mfvsrwz r29, f12
; CHECK-BE-NEXT: mfvsrwz r28, f13
; CHECK-BE-NEXT: mfvsrwz r27, v2
; CHECK-BE-NEXT: mfvsrwz r26, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r11, r11, 56
; CHECK-BE-NEXT: sldi r12, r12, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: sldi r0, r0, 56
; CHECK-BE-NEXT: sldi r30, r30, 56
; CHECK-BE-NEXT: sldi r29, r29, 56
; CHECK-BE-NEXT: sldi r28, r28, 56
; CHECK-BE-NEXT: sldi r27, r27, 56
; CHECK-BE-NEXT: sldi r26, r26, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v10, r11
; CHECK-BE-NEXT: mtvsrd v14, r12
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v0, r7
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: mtvsrd v8, r0
; CHECK-BE-NEXT: mtvsrd v9, r30
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v12, r28
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v13, r27
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v15, r26
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghb v4, v5, v4 ; CHECK-BE-NEXT: vmrghb v4, v5, v4
; CHECK-BE-NEXT: vmrghb v2, v2, v0 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: vmrghb v5, v6, v1 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v3, v3, v7 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v0, v9, v8 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: vmrghb v1, v10, v11 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v6, v13, v12 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v7, v14, v15 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghh v3, v3, v5 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: vmrghh v4, v1, v0
; CHECK-BE-NEXT: vmrghh v5, v7, v6
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i8> %1 = fptoui <16 x float> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }
Show All 22 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 1 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptosi <2 x float> %0 to <2 x i8> %1 = fptosi <2 x float> %0 to <2 x i8>
Show All 32 Lines
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xxswapd vs1, v2
; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f3, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v3, v4, v5
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xxswapd vs1, v2
; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1
; CHECK-BE-NEXT: xscvspdpn f3, v2
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: mfvsrwz r6, f2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v4, v2
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <4 x float> %a to <4 x i8> %0 = fptosi <4 x float> %a to <4 x i8>
%1 = bitcast <4 x i8> %0 to i32 %1 = bitcast <4 x i8> %0 to i32
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs3, vs1
; CHECK-P9-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs6, vs0
; CHECK-P9-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r9, f0
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mfvsrwz r7, f5 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: mfvsrwz r8, f6 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: mfvsrwz r10, f7 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f6, r9 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: mtvsrd f4, r7 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v1, vs5 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xxswapd v7, vs7 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v4, v1, v0 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglb v5, v6, v7
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xxsldwi vs4, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd vs6, vs0
; CHECK-BE-NEXT: xxsldwi vs7, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5
; CHECK-BE-NEXT: xscvspdpn f6, vs6
; CHECK-BE-NEXT: xscvspdpn f7, vs7
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: mfvsrwz r6, f4 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r7, f5 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: mtvsrd v1, r8 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: mtvsrd v7, r10 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: vmrghb v4, v1, v0 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
%1 = fptosi <8 x float> %a to <8 x i8> %1 = fptosi <8 x float> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v7, v6 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 0(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-P9-NEXT: xxswapd vs5, vs3
; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-P9-NEXT: xxswapd vs8, vs2
; CHECK-P9-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-P9-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-P9-NEXT: xxswapd vs11, vs1
; CHECK-P9-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-P9-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs2, 48(r3)
; CHECK-P9-NEXT: lxv vs3, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvspdpn f4, vs4
; CHECK-P9-NEXT: xscvspdpn f5, vs5
; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f8, vs8
; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvspdpn f11, vs11
; CHECK-P9-NEXT: xscvspdpn f12, vs12
; CHECK-P9-NEXT: xscvspdpn f13, vs13
; CHECK-P9-NEXT: xscvspdpn v2, v2
; CHECK-P9-NEXT: xscvspdpn v3, v3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r11, f1
; CHECK-P9-NEXT: mfvsrwz r12, f0
; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r7, f6
; CHECK-P9-NEXT: mfvsrwz r8, f7
; CHECK-P9-NEXT: mfvsrwz r9, f8
; CHECK-P9-NEXT: mfvsrwz r10, f9
; CHECK-P9-NEXT: mfvsrwz r0, f10
; CHECK-P9-NEXT: mfvsrwz r30, f11
; CHECK-P9-NEXT: mfvsrwz r29, f12
; CHECK-P9-NEXT: mfvsrwz r28, f13
; CHECK-P9-NEXT: mfvsrwz r27, v2
; CHECK-P9-NEXT: mfvsrwz r26, v3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f8, r11
; CHECK-P9-NEXT: mtvsrd f9, r12
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f5, r8
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: mtvsrd f7, r10
; CHECK-P9-NEXT: mtvsrd f10, r0
; CHECK-P9-NEXT: mtvsrd f11, r30
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd f12, r29
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd f13, r28
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd v2, r27
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtvsrd v3, r26
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxsldwi vs0, vs4, vs4, 3
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxswapd v1, vs4 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v6, vs5 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v7, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v8, vs1 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs10
; CHECK-P9-NEXT: xxswapd v11, vs11
; CHECK-P9-NEXT: xxswapd v12, vs8
; CHECK-P9-NEXT: xxswapd v13, vs12
; CHECK-P9-NEXT: xxswapd v14, vs13
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs9
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglb v5, v0, v5
; CHECK-P9-NEXT: vmrglb v4, v4, v1
; CHECK-P9-NEXT: vmrglb v0, v7, v6
; CHECK-P9-NEXT: vmrglb v1, v8, v9
; CHECK-P9-NEXT: vmrglb v6, v11, v10
; CHECK-P9-NEXT: vmrglb v7, v12, v13
; CHECK-P9-NEXT: vmrglb v2, v2, v14
; CHECK-P9-NEXT: vmrglb v3, v15, v3
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglh v5, v1, v0
; CHECK-P9-NEXT: vmrglh v0, v7, v6
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxmrgld v2, v2, v3 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs4
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs3, vs3, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs3
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs2
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs2
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xxswapd vs5, vs3
; CHECK-BE-NEXT: xxsldwi vs6, vs3, vs3, 1
; CHECK-BE-NEXT: xxsldwi vs7, vs2, vs2, 3
; CHECK-BE-NEXT: xxswapd vs8, vs2
; CHECK-BE-NEXT: xxsldwi vs9, vs2, vs2, 1
; CHECK-BE-NEXT: xxsldwi vs10, vs1, vs1, 3
; CHECK-BE-NEXT: xxswapd vs11, vs1
; CHECK-BE-NEXT: xxsldwi vs12, vs1, vs1, 1
; CHECK-BE-NEXT: xxsldwi vs13, vs0, vs0, 3
; CHECK-BE-NEXT: xxswapd v2, vs0
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvspdpn f6, vs6 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f7, vs7 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xscvspdpn f9, vs9 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: xscvspdpn f10, vs10 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f11, vs11 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f12, vs12 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvspdpn f13, vs13 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvspdpn v2, v2
; CHECK-BE-NEXT: xscvspdpn v3, v3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mfvsrwz r11, f1
; CHECK-BE-NEXT: mfvsrwz r12, f0
; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r7, f6
; CHECK-BE-NEXT: mfvsrwz r8, f7
; CHECK-BE-NEXT: mfvsrwz r9, f8
; CHECK-BE-NEXT: mfvsrwz r10, f9
; CHECK-BE-NEXT: mfvsrwz r0, f10
; CHECK-BE-NEXT: mfvsrwz r30, f11
; CHECK-BE-NEXT: mfvsrwz r29, f12
; CHECK-BE-NEXT: mfvsrwz r28, f13
; CHECK-BE-NEXT: mfvsrwz r27, v2
; CHECK-BE-NEXT: mfvsrwz r26, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r11, r11, 56
; CHECK-BE-NEXT: sldi r12, r12, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: sldi r0, r0, 56
; CHECK-BE-NEXT: sldi r30, r30, 56
; CHECK-BE-NEXT: sldi r29, r29, 56
; CHECK-BE-NEXT: sldi r28, r28, 56
; CHECK-BE-NEXT: sldi r27, r27, 56
; CHECK-BE-NEXT: sldi r26, r26, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v10, r11
; CHECK-BE-NEXT: mtvsrd v14, r12
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v0, r7
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: mtvsrd v8, r0
; CHECK-BE-NEXT: mtvsrd v9, r30
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v12, r28
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v13, r27
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v15, r26
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghb v4, v5, v4 ; CHECK-BE-NEXT: vmrghb v4, v5, v4
; CHECK-BE-NEXT: vmrghb v2, v2, v0 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: vmrghb v5, v6, v1 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v3, v3, v7 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v0, v9, v8 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: vmrghb v1, v10, v11 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v6, v13, v12 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v7, v14, v15 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghh v3, v3, v5 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: vmrghh v4, v1, v0
; CHECK-BE-NEXT: vmrghh v5, v7, v6
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptosi <16 x float> %a to <16 x i8> %1 = fptosi <16 x float> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

Show All 22 Lines
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f1, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <2 x double> %a to <2 x i16> %0 = fptoui <2 x double> %a to <2 x i16>
%1 = bitcast <2 x i16> %0 to i32 %1 = bitcast <2 x i16> %0 to i32
ret i32 %1 ret i32 %1
} }
Show All 25 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs3, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r6, f3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs3, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mfvsrwz r6, f3
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
%1 = fptoui <4 x double> %a to <4 x i16> %1 = fptoui <4 x double> %a to <4 x i16>
%2 = bitcast <4 x i16> %1 to i64 %2 = bitcast <4 x i16> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v5, v1 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd vs5, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xxswapd vs6, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: xxswapd vs7, vs0 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r7, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r9, f0 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r10, f7
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: xxswapd v1, vs5
; CHECK-P9-NEXT: xxswapd v7, vs7
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v4, v0, v1 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglh v5, v6, v7
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs5, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r7, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r7, r7, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: mfvsrwz r4, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: mtvsrd v6, r9 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r8, r8, 48 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: vmrghh v4, v0, v1 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghh v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptoui <8 x double> %a to <8 x i16> %1 = fptoui <8 x double> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: xxmrgld v2, v2, v0 ; CHECK-P8-NEXT: xxmrgld v2, v2, v0
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 0(r4)
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs5, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: xscvdpsxws f6, f3
; CHECK-P9-NEXT: lxv vs3, 80(r4) ; CHECK-P9-NEXT: lxv vs0, 64(r4)
; CHECK-P9-NEXT: lxv vs7, 64(r4) ; CHECK-P9-NEXT: xscvdpsxws f7, f2
; CHECK-P9-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxswapd vs8, vs6
; CHECK-P9-NEXT: xxswapd vs9, vs5
; CHECK-P9-NEXT: xxswapd vs10, vs4
; CHECK-P9-NEXT: xxswapd vs11, vs2
; CHECK-P9-NEXT: xxswapd vs12, vs7
; CHECK-P9-NEXT: xxswapd vs13, vs3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: mfvsrwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7
; CHECK-P9-NEXT: mtvsrd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: mtvsrd f3, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvdpsxws f11, f11 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xscvdpsxws f12, f12 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: xscvdpsxws f13, f13 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws v2, v2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xscvdpsxws v3, v3 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mfvsrwz r4, f6 ; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v4, vs7
; CHECK-P9-NEXT: mfvsrwz r7, f2
; CHECK-P9-NEXT: mfvsrwz r12, f7
; CHECK-P9-NEXT: mfvsrwz r0, f3
; CHECK-P9-NEXT: mfvsrwz r30, f1
; CHECK-P9-NEXT: mfvsrwz r29, f0
; CHECK-P9-NEXT: mfvsrwz r8, f8
; CHECK-P9-NEXT: mfvsrwz r9, f9
; CHECK-P9-NEXT: mfvsrwz r10, f10
; CHECK-P9-NEXT: mfvsrwz r11, f11
; CHECK-P9-NEXT: mfvsrwz r28, f12
; CHECK-P9-NEXT: mfvsrwz r27, f13
; CHECK-P9-NEXT: mfvsrwz r26, v2
; CHECK-P9-NEXT: mfvsrwz r25, v3
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtvsrd f1, r5
; CHECK-P9-NEXT: mtvsrd f2, r6 ; CHECK-P9-NEXT: mfvsrwz r5, f0
; CHECK-P9-NEXT: mtvsrd f3, r7 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: mtvsrd f8, r12 ; CHECK-P9-NEXT: xxswapd v1, vs1
; CHECK-P9-NEXT: mtvsrd f9, r0 ; CHECK-P9-NEXT: mtvsrd f0, r5
; CHECK-P9-NEXT: mtvsrd f10, r30 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: mtvsrd f11, r29 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f4, r8 ; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: mtvsrd f5, r9 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: mtvsrd f6, r10 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: mtvsrd f7, r11 ; CHECK-P9-NEXT: mfvsrwz r4, f3
; CHECK-P9-NEXT: mtvsrd f12, r28 ; CHECK-P9-NEXT: mtvsrd f3, r4
; CHECK-P9-NEXT: mtvsrd f13, r27 ; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mtvsrd v2, r26
; CHECK-P9-NEXT: mtvsrd v3, r25
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs2
; CHECK-P9-NEXT: xxswapd v1, vs3
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v6, vs4
; CHECK-P9-NEXT: xxswapd v7, vs5
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v8, vs6
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs8
; CHECK-P9-NEXT: xxswapd v11, vs12
; CHECK-P9-NEXT: xxswapd v12, vs9
; CHECK-P9-NEXT: xxswapd v13, vs13
; CHECK-P9-NEXT: xxswapd v14, vs10
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs11
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglh v4, v4, v6
; CHECK-P9-NEXT: vmrglh v5, v5, v7
; CHECK-P9-NEXT: vmrglh v0, v0, v8
; CHECK-P9-NEXT: vmrglh v1, v1, v9
; CHECK-P9-NEXT: vmrglh v6, v10, v11
; CHECK-P9-NEXT: vmrglh v7, v12, v13
; CHECK-P9-NEXT: vmrglh v2, v14, v2
; CHECK-P9-NEXT: vmrglh v3, v15, v3
; CHECK-P9-NEXT: vmrglw v4, v5, v4
; CHECK-P9-NEXT: vmrglw v5, v1, v0
; CHECK-P9-NEXT: vmrglw v0, v7, v6
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxmrgld vs0, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs1, v2, v0 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vmrglh v0, v0, v1
; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 0(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs4, 16(r4) ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs6, 48(r4) ; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: lxv vs3, 96(r4)
; CHECK-BE-NEXT: lxv vs7, 112(r4)
; CHECK-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxswapd vs8, vs6
; CHECK-BE-NEXT: xxswapd vs9, vs5
; CHECK-BE-NEXT: xxswapd vs10, vs4
; CHECK-BE-NEXT: xxswapd vs11, vs2
; CHECK-BE-NEXT: xxswapd vs12, vs7
; CHECK-BE-NEXT: xxswapd vs13, vs3
; CHECK-BE-NEXT: xxswapd v2, vs1
; CHECK-BE-NEXT: xxswapd v3, vs0
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mfvsrwz r5, f5
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: mfvsrwz r5, f6
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r4, f6
; CHECK-BE-NEXT: mfvsrwz r5, f5
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f2
; CHECK-BE-NEXT: mfvsrwz r12, f7
; CHECK-BE-NEXT: mfvsrwz r0, f3
; CHECK-BE-NEXT: mfvsrwz r30, f1
; CHECK-BE-NEXT: mfvsrwz r29, f0
; CHECK-BE-NEXT: mfvsrwz r8, f8
; CHECK-BE-NEXT: mfvsrwz r9, f9
; CHECK-BE-NEXT: mfvsrwz r10, f10
; CHECK-BE-NEXT: mfvsrwz r11, f11
; CHECK-BE-NEXT: mfvsrwz r28, f12
; CHECK-BE-NEXT: mfvsrwz r27, f13
; CHECK-BE-NEXT: mfvsrwz r26, v2
; CHECK-BE-NEXT: mfvsrwz r25, v3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: sldi r7, r7, 48 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: sldi r12, r12, 48
; CHECK-BE-NEXT: sldi r0, r0, 48
; CHECK-BE-NEXT: sldi r30, r30, 48
; CHECK-BE-NEXT: sldi r29, r29, 48
; CHECK-BE-NEXT: sldi r8, r8, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: sldi r11, r11, 48
; CHECK-BE-NEXT: sldi r28, r28, 48
; CHECK-BE-NEXT: sldi r27, r27, 48
; CHECK-BE-NEXT: sldi r26, r26, 48
; CHECK-BE-NEXT: sldi r25, r25, 48
; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mtvsrd v4, r6 ; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: mtvsrd v5, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: mtvsrd v8, r12 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: mtvsrd v10, r0 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v12, r30 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v0, r8 ; CHECK-BE-NEXT: mfvsrwz r5, f7
; CHECK-BE-NEXT: mtvsrd v1, r9 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v6, r10 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v7, r11 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v9, r28 ; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r27
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v13, r26
; CHECK-BE-NEXT: mtvsrd v14, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v15, r25
; CHECK-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghh v2, v2, v0
; CHECK-BE-NEXT: vmrghh v3, v3, v1
; CHECK-BE-NEXT: vmrghh v4, v4, v6
; CHECK-BE-NEXT: vmrghh v5, v5, v7
; CHECK-BE-NEXT: vmrghh v0, v8, v9
; CHECK-BE-NEXT: vmrghh v1, v10, v11
; CHECK-BE-NEXT: vmrghh v6, v12, v13
; CHECK-BE-NEXT: vmrghh v7, v14, v15
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: vmrghw v4, v1, v0 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: vmrghw v5, v7, v6 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: xxmrghd vs1, v5, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptoui <16 x double> %a to <16 x i16> %1 = fptoui <16 x double> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }
Show All 11 Lines
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f1, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <2 x double> %a to <2 x i16> %0 = fptosi <2 x double> %a to <2 x i16>
%1 = bitcast <2 x i16> %0 to i32 %1 = bitcast <2 x i16> %0 to i32
ret i32 %1 ret i32 %1
} }
Show All 25 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs3, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r6, f3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs3, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: mfvsrwz r6, f3
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r6 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
%1 = fptosi <4 x double> %a to <4 x i16> %1 = fptosi <4 x double> %a to <4 x i16>
%2 = bitcast <4 x i16> %1 to i64 %2 = bitcast <4 x i16> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v5, v5, v1 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd vs5, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xxswapd vs6, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: xxswapd vs7, vs0 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r7, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r9, f0 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r10, f7
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: xxswapd v1, vs5
; CHECK-P9-NEXT: xxswapd v7, vs7
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vmrglh v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v4, v0, v1 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglh v5, v6, v7
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs5, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r7, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r7, r7, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: mfvsrwz r4, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: mtvsrd v6, r9 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r8, r8, 48 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vmrghh v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: vmrghh v4, v0, v1 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghh v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptosi <8 x double> %a to <8 x i16> %1 = fptosi <8 x double> %a to <8 x i16>
ret <8 x i16> %1 ret <8 x i16> %1
} }
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xxmrgld v3, v5, v4 ; CHECK-P8-NEXT: xxmrgld v3, v5, v4
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: xxmrgld v2, v2, v0 ; CHECK-P8-NEXT: xxmrgld v2, v2, v0
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: lxv vs4, 0(r4)
; CHECK-P9-NEXT: lxv vs4, 32(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs5, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 0(r4) ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: xscvdpsxws f6, f3
; CHECK-P9-NEXT: lxv vs3, 80(r4) ; CHECK-P9-NEXT: lxv vs0, 64(r4)
; CHECK-P9-NEXT: lxv vs7, 64(r4) ; CHECK-P9-NEXT: xscvdpsxws f7, f2
; CHECK-P9-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: xxswapd vs8, vs6
; CHECK-P9-NEXT: xxswapd vs9, vs5
; CHECK-P9-NEXT: xxswapd vs10, vs4
; CHECK-P9-NEXT: xxswapd vs11, vs2
; CHECK-P9-NEXT: xxswapd vs12, vs7
; CHECK-P9-NEXT: xxswapd vs13, vs3
; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: mfvsrwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7
; CHECK-P9-NEXT: mtvsrd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: mtvsrd f3, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvdpsxws f11, f11 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xscvdpsxws f12, f12 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: xscvdpsxws f13, f13 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws v2, v2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xscvdpsxws v3, v3 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mfvsrwz r4, f6 ; CHECK-P9-NEXT: mfvsrwz r5, f1
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: xxswapd v4, vs7
; CHECK-P9-NEXT: mfvsrwz r7, f2
; CHECK-P9-NEXT: mfvsrwz r12, f7
; CHECK-P9-NEXT: mfvsrwz r0, f3
; CHECK-P9-NEXT: mfvsrwz r30, f1
; CHECK-P9-NEXT: mfvsrwz r29, f0
; CHECK-P9-NEXT: mfvsrwz r8, f8
; CHECK-P9-NEXT: mfvsrwz r9, f9
; CHECK-P9-NEXT: mfvsrwz r10, f10
; CHECK-P9-NEXT: mfvsrwz r11, f11
; CHECK-P9-NEXT: mfvsrwz r28, f12
; CHECK-P9-NEXT: mfvsrwz r27, f13
; CHECK-P9-NEXT: mfvsrwz r26, v2
; CHECK-P9-NEXT: mfvsrwz r25, v3
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtvsrd f1, r5
; CHECK-P9-NEXT: mtvsrd f2, r6 ; CHECK-P9-NEXT: mfvsrwz r5, f0
; CHECK-P9-NEXT: mtvsrd f3, r7 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: mtvsrd f8, r12 ; CHECK-P9-NEXT: xxswapd v1, vs1
; CHECK-P9-NEXT: mtvsrd f9, r0 ; CHECK-P9-NEXT: mtvsrd f0, r5
; CHECK-P9-NEXT: mtvsrd f10, r30 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: mtvsrd f11, r29 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f4, r8 ; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: mtvsrd f5, r9 ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: mtvsrd f6, r10 ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: mtvsrd f7, r11 ; CHECK-P9-NEXT: mfvsrwz r4, f3
; CHECK-P9-NEXT: mtvsrd f12, r28 ; CHECK-P9-NEXT: mtvsrd f3, r4
; CHECK-P9-NEXT: mtvsrd f13, r27 ; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mtvsrd v2, r26
; CHECK-P9-NEXT: mtvsrd v3, r25
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs2
; CHECK-P9-NEXT: xxswapd v1, vs3
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v6, vs4
; CHECK-P9-NEXT: xxswapd v7, vs5
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v8, vs6
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs8
; CHECK-P9-NEXT: xxswapd v11, vs12
; CHECK-P9-NEXT: xxswapd v12, vs9
; CHECK-P9-NEXT: xxswapd v13, vs13
; CHECK-P9-NEXT: xxswapd v14, vs10
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs11
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglh v4, v4, v6
; CHECK-P9-NEXT: vmrglh v5, v5, v7
; CHECK-P9-NEXT: vmrglh v0, v0, v8
; CHECK-P9-NEXT: vmrglh v1, v1, v9
; CHECK-P9-NEXT: vmrglh v6, v10, v11
; CHECK-P9-NEXT: vmrglh v7, v12, v13
; CHECK-P9-NEXT: vmrglh v2, v14, v2
; CHECK-P9-NEXT: vmrglh v3, v15, v3
; CHECK-P9-NEXT: vmrglw v4, v5, v4
; CHECK-P9-NEXT: vmrglw v5, v1, v0
; CHECK-P9-NEXT: vmrglw v0, v7, v6
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxmrgld vs0, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs1, v2, v0 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vmrglh v0, v0, v1
; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 0(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs4, 16(r4) ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: lxv vs5, 32(r4) ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs6, 48(r4) ; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: lxv vs3, 96(r4)
; CHECK-BE-NEXT: lxv vs7, 112(r4)
; CHECK-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: xxswapd vs8, vs6
; CHECK-BE-NEXT: xxswapd vs9, vs5
; CHECK-BE-NEXT: xxswapd vs10, vs4
; CHECK-BE-NEXT: xxswapd vs11, vs2
; CHECK-BE-NEXT: xxswapd vs12, vs7
; CHECK-BE-NEXT: xxswapd vs13, vs3
; CHECK-BE-NEXT: xxswapd v2, vs1
; CHECK-BE-NEXT: xxswapd v3, vs0
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mfvsrwz r5, f5
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: mfvsrwz r5, f6
; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r4, f6
; CHECK-BE-NEXT: mfvsrwz r5, f5
; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f2
; CHECK-BE-NEXT: mfvsrwz r12, f7
; CHECK-BE-NEXT: mfvsrwz r0, f3
; CHECK-BE-NEXT: mfvsrwz r30, f1
; CHECK-BE-NEXT: mfvsrwz r29, f0
; CHECK-BE-NEXT: mfvsrwz r8, f8
; CHECK-BE-NEXT: mfvsrwz r9, f9
; CHECK-BE-NEXT: mfvsrwz r10, f10
; CHECK-BE-NEXT: mfvsrwz r11, f11
; CHECK-BE-NEXT: mfvsrwz r28, f12
; CHECK-BE-NEXT: mfvsrwz r27, f13
; CHECK-BE-NEXT: mfvsrwz r26, v2
; CHECK-BE-NEXT: mfvsrwz r25, v3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r6, r6, 48 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: sldi r7, r7, 48 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: sldi r12, r12, 48
; CHECK-BE-NEXT: sldi r0, r0, 48
; CHECK-BE-NEXT: sldi r30, r30, 48
; CHECK-BE-NEXT: sldi r29, r29, 48
; CHECK-BE-NEXT: sldi r8, r8, 48
; CHECK-BE-NEXT: sldi r9, r9, 48
; CHECK-BE-NEXT: sldi r10, r10, 48
; CHECK-BE-NEXT: sldi r11, r11, 48
; CHECK-BE-NEXT: sldi r28, r28, 48
; CHECK-BE-NEXT: sldi r27, r27, 48
; CHECK-BE-NEXT: sldi r26, r26, 48
; CHECK-BE-NEXT: sldi r25, r25, 48
; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mtvsrd v4, r6 ; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: mtvsrd v5, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: mtvsrd v8, r12 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: mtvsrd v10, r0 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v12, r30 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v0, r8 ; CHECK-BE-NEXT: mfvsrwz r5, f7
; CHECK-BE-NEXT: mtvsrd v1, r9 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v6, r10 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v7, r11 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v9, r28 ; CHECK-BE-NEXT: mfvsrwz r5, f4
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r27
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v13, r26
; CHECK-BE-NEXT: mtvsrd v14, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v15, r25
; CHECK-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghh v2, v2, v0
; CHECK-BE-NEXT: vmrghh v3, v3, v1
; CHECK-BE-NEXT: vmrghh v4, v4, v6
; CHECK-BE-NEXT: vmrghh v5, v5, v7
; CHECK-BE-NEXT: vmrghh v0, v8, v9
; CHECK-BE-NEXT: vmrghh v1, v10, v11
; CHECK-BE-NEXT: vmrghh v6, v12, v13
; CHECK-BE-NEXT: vmrghh v7, v14, v15
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: mfvsrwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: vmrghw v4, v1, v0 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: vmrghw v5, v7, v6 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: xxmrghd vs1, v5, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i16> %1 = fptosi <16 x double> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Show All 22 Lines
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpuxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpuxws f1, v2 ; CHECK-P9-NEXT: mtvsrws v3, r3
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mtvsrws v3, r4
; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpuxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpuxws f1, v2 ; CHECK-BE-NEXT: mtvsrws v3, r3
; CHECK-BE-NEXT: xscvdpuxws f0, f0 ; CHECK-BE-NEXT: xscvdpuxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrws v3, r4
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <2 x double> %a to <2 x i32> %0 = fptoui <2 x double> %a to <2 x i32>
%1 = bitcast <2 x i32> %0 to i64 %1 = bitcast <2 x i32> %0 to i64
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xxmrgld vs3, vs1, vs0 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xvcvdpuxws v2, vs4 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs4
; CHECK-P9-NEXT: xvcvdpuxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
; CHECK-P9-NEXT: xvcvdpuxws v4, vs3 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xvcvdpuxws v5, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpuxws v4, vs0
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: vmrgew v3, v5, v4 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: vmrgew v3, v4, v3
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xxmrgld vs3, vs1, vs0 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: xvcvdpuxws v2, vs4 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs4
; CHECK-BE-NEXT: xvcvdpuxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
; CHECK-BE-NEXT: xvcvdpuxws v4, vs3 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xvcvdpuxws v5, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpuxws v4, vs0
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: vmrgew v3, v5, v4 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: vmrgew v3, v4, v3
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptoui <8 x double> %a to <8 x i32> %1 = fptoui <8 x double> %a to <8 x i32>
store <8 x i32> %1, <8 x i32>* %agg.result, align 32 store <8 x i32> %1, <8 x i32>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stvx v2, r3, r7
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs4, 96(r4)
; CHECK-P9-NEXT: lxv vs5, 112(r4)
; CHECK-P9-NEXT: lxv vs6, 64(r4)
; CHECK-P9-NEXT: lxv vs7, 80(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xxmrgld vs3, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xxmrgld vs1, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-P9-NEXT: xvcvdpuxws v2, vs8 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs8
; CHECK-P9-NEXT: xvcvdpuxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
; CHECK-P9-NEXT: xvcvdpuxws v4, vs3 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
; CHECK-P9-NEXT: xvcvdpuxws v5, vs0 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
; CHECK-P9-NEXT: xvcvdpuxws v0, vs1 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs7
; CHECK-P9-NEXT: xvcvdpuxws v1, vs6
; CHECK-P9-NEXT: xvcvdpuxws v6, vs7
; CHECK-P9-NEXT: xvcvdpuxws v7, vs4
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: vmrgew v3, v5, v4 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs4
; CHECK-P9-NEXT: vmrgew v4, v1, v0 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: vmrgew v5, v7, v6 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: stxv v5, 48(r3) ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpuxws v0, vs0
; CHECK-P9-NEXT: vmrgew v3, v3, v4
; CHECK-P9-NEXT: xvcvdpuxws v4, vs4
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: vmrgew v4, v5, v4
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
; CHECK-P9-NEXT: vmrgew v5, v0, v5
; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: lxv vs4, 112(r4)
; CHECK-BE-NEXT: lxv vs5, 96(r4)
; CHECK-BE-NEXT: lxv vs6, 80(r4)
; CHECK-BE-NEXT: lxv vs7, 64(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xxmrgld vs3, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xxmrgld vs1, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-BE-NEXT: xvcvdpuxws v2, vs8 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs8
; CHECK-BE-NEXT: xvcvdpuxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
; CHECK-BE-NEXT: xvcvdpuxws v4, vs3 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: xvcvdpuxws v5, vs0 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpuxws v0, vs1 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs7
; CHECK-BE-NEXT: xvcvdpuxws v1, vs6
; CHECK-BE-NEXT: xvcvdpuxws v6, vs7
; CHECK-BE-NEXT: xvcvdpuxws v7, vs4
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: vmrgew v3, v5, v4 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs4
; CHECK-BE-NEXT: vmrgew v4, v1, v0 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: vmrgew v5, v7, v6 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: stxv v3, 16(r3) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: stxv v5, 48(r3) ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpuxws v0, vs0
; CHECK-BE-NEXT: vmrgew v3, v3, v4
; CHECK-BE-NEXT: xvcvdpuxws v4, vs4
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: vmrgew v4, v5, v4
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
; CHECK-BE-NEXT: vmrgew v5, v0, v5
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptoui <16 x double> %a to <16 x i32> %1 = fptoui <16 x double> %a to <16 x i32>
store <16 x i32> %1, <16 x i32>* %agg.result, align 64 store <16 x i32> %1, <16 x i32>* %agg.result, align 64
ret void ret void
} }
Show All 11 Lines
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f1, v2 ; CHECK-P9-NEXT: mtvsrws v3, r3
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mtvsrws v3, r4
; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: mtvsrws v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrws v3, r4
; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <2 x double> %a to <2 x i32> %0 = fptosi <2 x double> %a to <2 x i32>
%1 = bitcast <2 x i32> %0 to i64 %1 = bitcast <2 x i32> %0 to i64
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrgew v2, v3, v2 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
; CHECK-P8-NEXT: vmrgew v3, v5, v4 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: lxv vs2, 0(r4)
; CHECK-P9-NEXT: lxv vs3, 16(r4) ; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xxmrgld vs3, vs1, vs0 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xvcvdpsxws v2, vs4 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs4
; CHECK-P9-NEXT: xvcvdpsxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
; CHECK-P9-NEXT: xvcvdpsxws v4, vs3 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xvcvdpsxws v5, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpsxws v4, vs0
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: vmrgew v3, v5, v4 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: vmrgew v3, v4, v3
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xxmrgld vs3, vs1, vs0 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
; CHECK-BE-NEXT: xvcvdpsxws v2, vs4 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs4
; CHECK-BE-NEXT: xvcvdpsxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
; CHECK-BE-NEXT: xvcvdpsxws v4, vs3 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xvcvdpsxws v5, vs0 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpsxws v4, vs0
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: vmrgew v3, v5, v4 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: vmrgew v3, v4, v3
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptosi <8 x double> %a to <8 x i32> %1 = fptosi <8 x double> %a to <8 x i32>
store <8 x i32> %1, <8 x i32>* %agg.result, align 32 store <8 x i32> %1, <8 x i32>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stvx v2, r3, r7
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs6, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs7, 16(r4)
; CHECK-P9-NEXT: lxv vs2, 0(r4) ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-P9-NEXT: lxv vs3, 16(r4)
; CHECK-P9-NEXT: lxv vs4, 96(r4)
; CHECK-P9-NEXT: lxv vs5, 112(r4)
; CHECK-P9-NEXT: lxv vs6, 64(r4)
; CHECK-P9-NEXT: lxv vs7, 80(r4)
; CHECK-P9-NEXT: xxmrgld vs8, vs3, vs2
; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: xxmrgld vs3, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xxmrgld vs1, vs7, vs6
; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-P9-NEXT: lxv vs4, 32(r4)
; CHECK-P9-NEXT: lxv vs5, 48(r4)
; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-P9-NEXT: xvcvdpsxws v2, vs8 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs8
; CHECK-P9-NEXT: xvcvdpsxws v3, vs2 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs6
; CHECK-P9-NEXT: xvcvdpsxws v4, vs3 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
; CHECK-P9-NEXT: xvcvdpsxws v5, vs0 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
; CHECK-P9-NEXT: xvcvdpsxws v0, vs1 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs7
; CHECK-P9-NEXT: xvcvdpsxws v1, vs6
; CHECK-P9-NEXT: xvcvdpsxws v6, vs7
; CHECK-P9-NEXT: xvcvdpsxws v7, vs4
; CHECK-P9-NEXT: vmrgew v2, v3, v2 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
; CHECK-P9-NEXT: vmrgew v3, v5, v4 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs4
; CHECK-P9-NEXT: vmrgew v4, v1, v0 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-P9-NEXT: vmrgew v5, v7, v6 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-P9-NEXT: stxv v3, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 96(r4)
; CHECK-P9-NEXT: lxv vs1, 112(r4)
; CHECK-P9-NEXT: stxv v2, 0(r3) ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: stxv v5, 48(r3) ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: xvcvdpsxws v0, vs0
; CHECK-P9-NEXT: vmrgew v3, v3, v4
; CHECK-P9-NEXT: xvcvdpsxws v4, vs4
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: vmrgew v4, v5, v4
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
; CHECK-P9-NEXT: vmrgew v5, v0, v5
; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
; CHECK-BE-NEXT: lxv vs3, 0(r4)
; CHECK-BE-NEXT: lxv vs4, 112(r4)
; CHECK-BE-NEXT: lxv vs5, 96(r4)
; CHECK-BE-NEXT: lxv vs6, 80(r4)
; CHECK-BE-NEXT: lxv vs7, 64(r4)
; CHECK-BE-NEXT: xxmrgld vs8, vs3, vs2
; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: xxmrgld vs3, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xxmrgld vs1, vs7, vs6
; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
; CHECK-BE-NEXT: xvcvdpsxws v2, vs8 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs8
; CHECK-BE-NEXT: xvcvdpsxws v3, vs2 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs6
; CHECK-BE-NEXT: xvcvdpsxws v4, vs3 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: xvcvdpsxws v5, vs0 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpsxws v0, vs1 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs7
; CHECK-BE-NEXT: xvcvdpsxws v1, vs6
; CHECK-BE-NEXT: xvcvdpsxws v6, vs7
; CHECK-BE-NEXT: xvcvdpsxws v7, vs4
; CHECK-BE-NEXT: vmrgew v2, v3, v2 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
; CHECK-BE-NEXT: vmrgew v3, v5, v4 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs4
; CHECK-BE-NEXT: vmrgew v4, v1, v0 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
; CHECK-BE-NEXT: vmrgew v5, v7, v6 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
; CHECK-BE-NEXT: stxv v3, 16(r3) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: stxv v5, 48(r3) ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-BE-NEXT: xvcvdpsxws v0, vs0
; CHECK-BE-NEXT: vmrgew v3, v3, v4
; CHECK-BE-NEXT: xvcvdpsxws v4, vs4
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: vmrgew v4, v5, v4
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
; CHECK-BE-NEXT: vmrgew v5, v0, v5
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i32> %1 = fptosi <16 x double> %a to <16 x i32>
store <16 x i32> %1, <16 x i32>* %agg.result, align 64 store <16 x i32> %1, <16 x i32>* %agg.result, align 64
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

Show All 25 Lines
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f1, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <2 x double> %a to <2 x i8> %0 = fptoui <2 x double> %a to <2 x i8>
%1 = bitcast <2 x i8> %0 to i16 %1 = bitcast <2 x i8> %0 to i16
ret i16 %1 ret i16 %1
Show All 27 Lines
; CHECK-P8-NEXT: vmrglb v3, v5, v4 ; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs3, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r6, f3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs3, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r5, r5, 56 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r6, f3 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vmrghb v3, v4, v5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
%1 = fptoui <4 x double> %a to <4 x i8> %1 = fptoui <4 x double> %a to <4 x i8>
%2 = bitcast <4 x i8> %1 to i32 %2 = bitcast <4 x i8> %1 to i32
ret i32 %2 ret i32 %2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd vs5, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xxswapd vs6, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: xxswapd vs7, vs0 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r7, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r9, f0 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r10, f7
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: xxswapd v1, vs5
; CHECK-P9-NEXT: xxswapd v7, vs7
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v4, v0, v1 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglb v5, v6, v7
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v5, v4 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs5, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r7, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: mfvsrwz r4, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: mtvsrd v6, r9 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r6, r6, 56 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r8, r8, 56 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: vmrghb v4, v0, v1 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptoui <8 x double> %a to <8 x i8> %1 = fptoui <8 x double> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v2, v0 ; CHECK-P8-NEXT: vmrglw v2, v2, v0
; CHECK-P8-NEXT: xxmrgld v2, v2, v3 ; CHECK-P8-NEXT: xxmrgld v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 48(r3) ; CHECK-P9-NEXT: lxv vs7, 0(r3)
; CHECK-P9-NEXT: lxv vs3, 32(r3) ; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: lxv vs4, 16(r3) ; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: lxv vs5, 0(r3) ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: lxv vs6, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs7, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: mfvsrwz r3, f8
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: mtvsrd f8, r3
; CHECK-P9-NEXT: xxswapd vs8, vs5 ; CHECK-P9-NEXT: mfvsrwz r3, f7
; CHECK-P9-NEXT: xxswapd vs9, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs8
; CHECK-P9-NEXT: xxswapd vs10, vs3 ; CHECK-P9-NEXT: mtvsrd f7, r3
; CHECK-P9-NEXT: xxswapd vs11, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xxswapd vs12, vs7 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs13, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f7
; CHECK-P9-NEXT: mtvsrd f7, r3
; CHECK-P9-NEXT: mfvsrwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: mfvsrwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: mtvsrd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: mtvsrd f5, r3
; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mfvsrwz r11, f7
; CHECK-P9-NEXT: mfvsrwz r12, f6
; CHECK-P9-NEXT: mfvsrwz r0, f1
; CHECK-P9-NEXT: mfvsrwz r30, f0
; CHECK-P9-NEXT: mfvsrwz r7, f8
; CHECK-P9-NEXT: mfvsrwz r8, f9
; CHECK-P9-NEXT: mfvsrwz r9, f10
; CHECK-P9-NEXT: mfvsrwz r10, f11
; CHECK-P9-NEXT: mfvsrwz r29, f12
; CHECK-P9-NEXT: mfvsrwz r28, f13
; CHECK-P9-NEXT: mfvsrwz r27, v2
; CHECK-P9-NEXT: mfvsrwz r26, v3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: mtvsrd f8, r11
; CHECK-P9-NEXT: mtvsrd f9, r12
; CHECK-P9-NEXT: mtvsrd f10, r0
; CHECK-P9-NEXT: mtvsrd f11, r30
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f5, r8
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: mtvsrd f7, r10
; CHECK-P9-NEXT: mtvsrd f12, r29
; CHECK-P9-NEXT: mtvsrd f13, r28
; CHECK-P9-NEXT: mtvsrd v2, r27
; CHECK-P9-NEXT: mtvsrd v3, r26
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs2 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: xxswapd v1, vs3 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v6, vs4
; CHECK-P9-NEXT: xxswapd v7, vs5
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v8, vs6
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs8
; CHECK-P9-NEXT: xxswapd v11, vs12
; CHECK-P9-NEXT: xxswapd v12, vs9
; CHECK-P9-NEXT: xxswapd v13, vs13
; CHECK-P9-NEXT: xxswapd v14, vs10
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs11
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglb v4, v4, v6
; CHECK-P9-NEXT: vmrglb v5, v5, v7
; CHECK-P9-NEXT: vmrglb v0, v0, v8
; CHECK-P9-NEXT: vmrglb v1, v1, v9
; CHECK-P9-NEXT: vmrglb v6, v10, v11
; CHECK-P9-NEXT: vmrglb v7, v12, v13
; CHECK-P9-NEXT: vmrglb v2, v14, v2
; CHECK-P9-NEXT: vmrglb v3, v15, v3
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglh v5, v1, v0 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: vmrglh v0, v7, v6 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: xxmrgld v2, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 64(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: lxv vs3, 80(r3) ; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: lxv vs4, 96(r3) ; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: lxv vs5, 112(r3) ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs6, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs7, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mfvsrwz r3, f8
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xxswapd vs8, vs5 ; CHECK-BE-NEXT: mfvsrwz r3, f7
; CHECK-BE-NEXT: xxswapd vs9, vs4 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs10, vs3 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: xxswapd vs11, vs2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xxswapd vs12, vs7 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xxswapd vs13, vs6 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xxswapd v2, vs1 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: xxswapd v3, vs0 ; CHECK-BE-NEXT: mfvsrwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f9, f9 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: xscvdpsxws f10, f10 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f11, f11 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f12, f12 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f13, f13 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvdpsxws v2, v2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws v3, v3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: mfvsrwz r4, f4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r6, f2
; CHECK-BE-NEXT: mfvsrwz r11, f7
; CHECK-BE-NEXT: mfvsrwz r12, f6
; CHECK-BE-NEXT: mfvsrwz r0, f1
; CHECK-BE-NEXT: mfvsrwz r30, f0
; CHECK-BE-NEXT: mfvsrwz r7, f8
; CHECK-BE-NEXT: mfvsrwz r8, f9
; CHECK-BE-NEXT: mfvsrwz r9, f10
; CHECK-BE-NEXT: mfvsrwz r10, f11
; CHECK-BE-NEXT: mfvsrwz r29, f12
; CHECK-BE-NEXT: mfvsrwz r28, f13
; CHECK-BE-NEXT: mfvsrwz r27, v2
; CHECK-BE-NEXT: mfvsrwz r26, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r11, r11, 56
; CHECK-BE-NEXT: sldi r12, r12, 56
; CHECK-BE-NEXT: sldi r0, r0, 56
; CHECK-BE-NEXT: sldi r30, r30, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: sldi r29, r29, 56
; CHECK-BE-NEXT: sldi r28, r28, 56
; CHECK-BE-NEXT: sldi r27, r27, 56
; CHECK-BE-NEXT: sldi r26, r26, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v8, r11
; CHECK-BE-NEXT: mtvsrd v10, r12
; CHECK-BE-NEXT: mtvsrd v12, r0
; CHECK-BE-NEXT: mtvsrd v14, r30
; CHECK-BE-NEXT: mtvsrd v0, r7
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v9, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r28
; CHECK-BE-NEXT: mtvsrd v13, r27
; CHECK-BE-NEXT: mtvsrd v15, r26
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghb v2, v2, v0
; CHECK-BE-NEXT: vmrghb v3, v3, v1
; CHECK-BE-NEXT: vmrghb v4, v4, v6
; CHECK-BE-NEXT: vmrghb v5, v5, v7
; CHECK-BE-NEXT: vmrghb v0, v8, v9
; CHECK-BE-NEXT: vmrghb v1, v10, v11
; CHECK-BE-NEXT: vmrghb v6, v12, v13
; CHECK-BE-NEXT: vmrghb v7, v14, v15
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4
; CHECK-BE-NEXT: vmrghh v4, v1, v0
; CHECK-BE-NEXT: vmrghh v5, v7, v6
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptoui <16 x double> %a to <16 x i8> %1 = fptoui <16 x double> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }
Show All 14 Lines
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f1, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mfvsrwz r4, f0
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <2 x double> %a to <2 x i8> %0 = fptosi <2 x double> %a to <2 x i8>
%1 = bitcast <2 x i8> %0 to i16 %1 = bitcast <2 x i8> %0 to i16
ret i16 %1 ret i16 %1
Show All 27 Lines
; CHECK-P8-NEXT: vmrglb v3, v5, v4 ; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs3, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: mfvsrwz r4, f2
; CHECK-P9-NEXT: mfvsrwz r6, f3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: mtvsrd f1, r4
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs3, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: mfvsrwz r5, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r5, r5, 56 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: mfvsrwz r6, f3 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vmrghb v3, v4, v5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
%1 = fptosi <4 x double> %a to <4 x i8> %1 = fptosi <4 x double> %a to <4 x i8>
%2 = bitcast <4 x i8> %1 to i32 %2 = bitcast <4 x i8> %1 to i32
ret i32 %2 ret i32 %2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd vs5, vs2 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xxswapd vs6, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: xxswapd vs7, vs0 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r7, f1 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mfvsrwz r9, f0 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5
; CHECK-P9-NEXT: mfvsrwz r8, f6
; CHECK-P9-NEXT: mfvsrwz r10, f7
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: mtvsrd f3, r6 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: mtvsrd f5, r8 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mtvsrd f7, r10 ; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: xxswapd v0, vs4 ; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v6, vs6 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v5, vs3
; CHECK-P9-NEXT: xxswapd v1, vs5
; CHECK-P9-NEXT: xxswapd v7, vs7
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: vmrglb v3, v4, v5 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v4, v0, v1 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglb v5, v6, v7
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglh v3, v5, v4 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs5, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r7, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: mfvsrwz r4, f4
; CHECK-BE-NEXT: mfvsrwz r6, f5
; CHECK-BE-NEXT: mfvsrwz r8, f6
; CHECK-BE-NEXT: mfvsrwz r10, f7
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mtvsrd v0, r7 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: mtvsrd v6, r9 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r4, r4, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r6, r6, 56 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r8, r8, 56 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vmrghb v3, v4, v5 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: vmrghb v4, v0, v1 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghb v5, v6, v7 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
%1 = fptosi <8 x double> %a to <8 x i8> %1 = fptosi <8 x double> %a to <8 x i8>
%2 = bitcast <8 x i8> %1 to i64 %2 = bitcast <8 x i8> %1 to i64
ret i64 %2 ret i64 %2
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v2, v0 ; CHECK-P8-NEXT: vmrglw v2, v2, v0
; CHECK-P8-NEXT: xxmrgld v2, v2, v3 ; CHECK-P8-NEXT: xxmrgld v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 48(r3) ; CHECK-P9-NEXT: lxv vs7, 0(r3)
; CHECK-P9-NEXT: lxv vs3, 32(r3) ; CHECK-P9-NEXT: xscvdpsxws f8, f7
; CHECK-P9-NEXT: lxv vs4, 16(r3) ; CHECK-P9-NEXT: xxswapd vs7, vs7
; CHECK-P9-NEXT: lxv vs5, 0(r3) ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: lxv vs6, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs7, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: mfvsrwz r3, f8
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: mtvsrd f8, r3
; CHECK-P9-NEXT: xxswapd vs8, vs5 ; CHECK-P9-NEXT: mfvsrwz r3, f7
; CHECK-P9-NEXT: xxswapd vs9, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs8
; CHECK-P9-NEXT: xxswapd vs10, vs3 ; CHECK-P9-NEXT: mtvsrd f7, r3
; CHECK-P9-NEXT: xxswapd vs11, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xxswapd vs12, vs7 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs13, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: mfvsrwz r3, f7
; CHECK-P9-NEXT: mtvsrd f7, r3
; CHECK-P9-NEXT: mfvsrwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: mfvsrwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: mtvsrd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: mtvsrd f5, r3
; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: mtvsrd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpsxws f8, f8 ; CHECK-P9-NEXT: mfvsrwz r3, f1
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: mtvsrd f1, r3
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: mfvsrwz r3, f0
; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mfvsrwz r11, f7
; CHECK-P9-NEXT: mfvsrwz r12, f6
; CHECK-P9-NEXT: mfvsrwz r0, f1
; CHECK-P9-NEXT: mfvsrwz r30, f0
; CHECK-P9-NEXT: mfvsrwz r7, f8
; CHECK-P9-NEXT: mfvsrwz r8, f9
; CHECK-P9-NEXT: mfvsrwz r9, f10
; CHECK-P9-NEXT: mfvsrwz r10, f11
; CHECK-P9-NEXT: mfvsrwz r29, f12
; CHECK-P9-NEXT: mfvsrwz r28, f13
; CHECK-P9-NEXT: mfvsrwz r27, v2
; CHECK-P9-NEXT: mfvsrwz r26, v3
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mtvsrd f3, r6
; CHECK-P9-NEXT: mtvsrd f8, r11
; CHECK-P9-NEXT: mtvsrd f9, r12
; CHECK-P9-NEXT: mtvsrd f10, r0
; CHECK-P9-NEXT: mtvsrd f11, r30
; CHECK-P9-NEXT: mtvsrd f4, r7
; CHECK-P9-NEXT: mtvsrd f5, r8
; CHECK-P9-NEXT: mtvsrd f6, r9
; CHECK-P9-NEXT: mtvsrd f7, r10
; CHECK-P9-NEXT: mtvsrd f12, r29
; CHECK-P9-NEXT: mtvsrd f13, r28
; CHECK-P9-NEXT: mtvsrd v2, r27
; CHECK-P9-NEXT: mtvsrd v3, r26
; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs2 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: xxswapd v1, vs3 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v6, vs4
; CHECK-P9-NEXT: xxswapd v7, vs5
; CHECK-P9-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: xxswapd v8, vs6
; CHECK-P9-NEXT: xxswapd v9, vs7
; CHECK-P9-NEXT: xxswapd v10, vs8
; CHECK-P9-NEXT: xxswapd v11, vs12
; CHECK-P9-NEXT: xxswapd v12, vs9
; CHECK-P9-NEXT: xxswapd v13, vs13
; CHECK-P9-NEXT: xxswapd v14, vs10
; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: xxswapd v15, vs11
; CHECK-P9-NEXT: xxswapd v3, v3
; CHECK-P9-NEXT: vmrglb v4, v4, v6
; CHECK-P9-NEXT: vmrglb v5, v5, v7
; CHECK-P9-NEXT: vmrglb v0, v0, v8
; CHECK-P9-NEXT: vmrglb v1, v1, v9
; CHECK-P9-NEXT: vmrglb v6, v10, v11
; CHECK-P9-NEXT: vmrglb v7, v12, v13
; CHECK-P9-NEXT: vmrglb v2, v14, v2
; CHECK-P9-NEXT: vmrglb v3, v15, v3
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglh v5, v1, v0 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: vmrglh v0, v7, v6 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: xxmrgld v2, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs2, 64(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: lxv vs3, 80(r3) ; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: lxv vs4, 96(r3) ; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: lxv vs5, 112(r3) ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs6, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs7, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mfvsrwz r3, f8
; CHECK-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xxswapd vs8, vs5 ; CHECK-BE-NEXT: mfvsrwz r3, f7
; CHECK-BE-NEXT: xxswapd vs9, vs4 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs10, vs3 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: xxswapd vs11, vs2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xxswapd vs12, vs7 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xxswapd vs13, vs6 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xxswapd v2, vs1 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: xxswapd v3, vs0 ; CHECK-BE-NEXT: mfvsrwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f9, f9 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: xscvdpsxws f10, f10 ; CHECK-BE-NEXT: mfvsrwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f11, f11 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f12, f12 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f13, f13 ; CHECK-BE-NEXT: mfvsrwz r3, f0
; CHECK-BE-NEXT: xscvdpsxws v2, v2 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws v3, v3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: mfvsrwz r4, f4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r6, f2
; CHECK-BE-NEXT: mfvsrwz r11, f7
; CHECK-BE-NEXT: mfvsrwz r12, f6
; CHECK-BE-NEXT: mfvsrwz r0, f1
; CHECK-BE-NEXT: mfvsrwz r30, f0
; CHECK-BE-NEXT: mfvsrwz r7, f8
; CHECK-BE-NEXT: mfvsrwz r8, f9
; CHECK-BE-NEXT: mfvsrwz r9, f10
; CHECK-BE-NEXT: mfvsrwz r10, f11
; CHECK-BE-NEXT: mfvsrwz r29, f12
; CHECK-BE-NEXT: mfvsrwz r28, f13
; CHECK-BE-NEXT: mfvsrwz r27, v2
; CHECK-BE-NEXT: mfvsrwz r26, v3
; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: sldi r4, r4, 56
; CHECK-BE-NEXT: sldi r5, r5, 56
; CHECK-BE-NEXT: sldi r6, r6, 56
; CHECK-BE-NEXT: sldi r11, r11, 56
; CHECK-BE-NEXT: sldi r12, r12, 56
; CHECK-BE-NEXT: sldi r0, r0, 56
; CHECK-BE-NEXT: sldi r30, r30, 56
; CHECK-BE-NEXT: sldi r7, r7, 56
; CHECK-BE-NEXT: sldi r8, r8, 56
; CHECK-BE-NEXT: sldi r9, r9, 56
; CHECK-BE-NEXT: sldi r10, r10, 56
; CHECK-BE-NEXT: sldi r29, r29, 56
; CHECK-BE-NEXT: sldi r28, r28, 56
; CHECK-BE-NEXT: sldi r27, r27, 56
; CHECK-BE-NEXT: sldi r26, r26, 56
; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mtvsrd v5, r6
; CHECK-BE-NEXT: mtvsrd v8, r11
; CHECK-BE-NEXT: mtvsrd v10, r12
; CHECK-BE-NEXT: mtvsrd v12, r0
; CHECK-BE-NEXT: mtvsrd v14, r30
; CHECK-BE-NEXT: mtvsrd v0, r7
; CHECK-BE-NEXT: mtvsrd v1, r8
; CHECK-BE-NEXT: mtvsrd v6, r9
; CHECK-BE-NEXT: mtvsrd v7, r10
; CHECK-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v9, r29
; CHECK-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: mtvsrd v11, r28
; CHECK-BE-NEXT: mtvsrd v13, r27
; CHECK-BE-NEXT: mtvsrd v15, r26
; CHECK-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: vmrghb v2, v2, v0
; CHECK-BE-NEXT: vmrghb v3, v3, v1
; CHECK-BE-NEXT: vmrghb v4, v4, v6
; CHECK-BE-NEXT: vmrghb v5, v5, v7
; CHECK-BE-NEXT: vmrghb v0, v8, v9
; CHECK-BE-NEXT: vmrghb v1, v10, v11
; CHECK-BE-NEXT: vmrghb v6, v12, v13
; CHECK-BE-NEXT: vmrghb v7, v14, v15
; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vmrghh v3, v5, v4
; CHECK-BE-NEXT: vmrghh v4, v1, v0
; CHECK-BE-NEXT: vmrghh v5, v7, v6
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i8> %1 = fptosi <16 x double> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs6, r3, r11 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs7, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: lxv vs4, 112(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: lxv vs5, 96(r4) ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: lxv vs6, 80(r4) ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs7, 64(r4) ; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-P9-NEXT: stxv vs0, 112(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-P9-NEXT: stxv vs1, 96(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-P9-NEXT: stxv vs2, 80(r3)
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4 ; CHECK-P9-NEXT: stxv vs3, 64(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs1, 32(r3) ; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs2, 16(r3) ; CHECK-P9-NEXT: stxv vs6, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 0(r3) ; CHECK-P9-NEXT: stxv vs7, 0(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: stxv vs5, 96(r3)
; CHECK-P9-NEXT: stxv vs6, 80(r3)
; CHECK-P9-NEXT: stxv vs7, 64(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: lxv vs4, 112(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 96(r4) ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: lxv vs6, 80(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs7, 64(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 ; CHECK-BE-NEXT: stxv vs0, 112(r3)
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 ; CHECK-BE-NEXT: stxv vs1, 96(r3)
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4 ; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: stxv vs0, 48(r3) ; CHECK-BE-NEXT: stxv vs4, 48(r3)
; CHECK-BE-NEXT: stxv vs1, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: stxv vs2, 16(r3) ; CHECK-BE-NEXT: stxv vs6, 16(r3)
; CHECK-BE-NEXT: stxv vs3, 0(r3) ; CHECK-BE-NEXT: stxv vs7, 0(r3)
; CHECK-BE-NEXT: stxv vs4, 112(r3)
; CHECK-BE-NEXT: stxv vs5, 96(r3)
; CHECK-BE-NEXT: stxv vs6, 80(r3)
; CHECK-BE-NEXT: stxv vs7, 64(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptoui <16 x double> %a to <16 x i64> %1 = fptoui <16 x double> %a to <16 x i64>
store <16 x i64> %1, <16 x i64>* %agg.result, align 128 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
ret void ret void
} }
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs6, r3, r11 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs7, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 48(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 32(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 16(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 0(r4) ; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: lxv vs4, 112(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: lxv vs5, 96(r4) ; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
; CHECK-P9-NEXT: lxv vs6, 80(r4) ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs7, 64(r4) ; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3 ; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2 ; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1 ; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0 ; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7 ; CHECK-P9-NEXT: stxv vs0, 112(r3)
; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6 ; CHECK-P9-NEXT: stxv vs1, 96(r3)
; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5 ; CHECK-P9-NEXT: stxv vs2, 80(r3)
; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4 ; CHECK-P9-NEXT: stxv vs3, 64(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3) ; CHECK-P9-NEXT: stxv vs4, 48(r3)
; CHECK-P9-NEXT: stxv vs1, 32(r3) ; CHECK-P9-NEXT: stxv vs5, 32(r3)
; CHECK-P9-NEXT: stxv vs2, 16(r3) ; CHECK-P9-NEXT: stxv vs6, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 0(r3) ; CHECK-P9-NEXT: stxv vs7, 0(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: stxv vs5, 96(r3)
; CHECK-P9-NEXT: stxv vs6, 80(r3)
; CHECK-P9-NEXT: stxv vs7, 64(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: lxv vs1, 32(r4) ; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 0(r4) ; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: lxv vs4, 112(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: lxv vs5, 96(r4) ; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
; CHECK-BE-NEXT: lxv vs6, 80(r4) ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs7, 64(r4) ; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3 ; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2 ; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1 ; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0 ; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7 ; CHECK-BE-NEXT: stxv vs0, 112(r3)
; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6 ; CHECK-BE-NEXT: stxv vs1, 96(r3)
; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4 ; CHECK-BE-NEXT: stxv vs3, 64(r3)
; CHECK-BE-NEXT: stxv vs0, 48(r3) ; CHECK-BE-NEXT: stxv vs4, 48(r3)
; CHECK-BE-NEXT: stxv vs1, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: stxv vs2, 16(r3) ; CHECK-BE-NEXT: stxv vs6, 16(r3)
; CHECK-BE-NEXT: stxv vs3, 0(r3) ; CHECK-BE-NEXT: stxv vs7, 0(r3)
; CHECK-BE-NEXT: stxv vs4, 112(r3)
; CHECK-BE-NEXT: stxv vs5, 96(r3)
; CHECK-BE-NEXT: stxv vs6, 80(r3)
; CHECK-BE-NEXT: stxv vs7, 64(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i64> %1 = fptosi <16 x double> %a to <16 x i64>
store <16 x i64> %1, <16 x i64>* %agg.result, align 128 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

Show All 29 Lines
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: li r4, 2
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: vextuhrx r4, r4, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-P9-NEXT: rlwinm r4, r4, 0, 16, 31
; CHECK-P9-NEXT: mtvsrwz f0, r3 ; CHECK-P9-NEXT: mtvsrwz f0, r3
; CHECK-P9-NEXT: mtvsrwz f1, r4 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvuxdsp f1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 2 ; CHECK-BE-NEXT: li r3, 2
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: vextuhlx r4, r4, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-BE-NEXT: rlwinm r4, r4, 0, 16, 31
; CHECK-BE-NEXT: mtvsrwz f0, r3 ; CHECK-BE-NEXT: mtvsrwz f0, r3
; CHECK-BE-NEXT: mtvsrwz f1, r4 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtvsrwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: xscvuxdsp f1, f1
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: xscvdpspn v3, f1 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = uitofp <2 x i16> %0 to <2 x float> %1 = uitofp <2 x i16> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: lxvx v2, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v3, v2
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: vperm v2, v3, v4, v2
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = uitofp <4 x i16> %0 to <4 x float> %1 = uitofp <4 x i16> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 14 Lines
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI2_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v3, v5, v2, v3 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: vperm v2, v5, v2, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI2_1@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v2, v5, v3 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: vperm v2, v5, v2, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <8 x i16> %a to <8 x float> %0 = uitofp <8 x i16> %a to <8 x float>
store <8 x float> %0, <8 x float>* %agg.result, align 32 store <8 x float> %0, <8 x float>* %agg.result, align 32
ret void ret void
} }
define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
Show All 22 Lines
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: stvx v4, 0, r3
; CHECK-P8-NEXT: stvx v2, r3, r6 ; CHECK-P8-NEXT: stvx v2, r3, r6
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: stvx v5, r3, r4
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: xxlxor v0, v0, v0 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI3_1@toc@l ; CHECK-P9-NEXT: lxvx v4, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: lxvx v5, 0, r6 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: vperm v1, v0, v3, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v0, v3, v5 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: vperm v4, v0, v2, v4 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0
; CHECK-P9-NEXT: vperm v2, v0, v2, v5 ; CHECK-P9-NEXT: lxvx v0, 0, r4
; CHECK-P9-NEXT: xvcvuxwsp vs0, v1 ; CHECK-P9-NEXT: vperm v3, v5, v3, v0
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
; CHECK-P9-NEXT: xvcvuxwsp vs2, v4 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
; CHECK-P9-NEXT: vperm v2, v5, v2, v0
; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: xxlxor v0, v0, v0 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: addi r6, r6, .LCPI3_1@toc@l ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: lxvx v5, 0, r6 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: vperm v1, v3, v0, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v0, v3, v5 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: vperm v4, v2, v0, v4 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0
; CHECK-BE-NEXT: vperm v2, v0, v2, v5 ; CHECK-BE-NEXT: lxvx v0, 0, r4
; CHECK-BE-NEXT: xvcvuxwsp vs0, v1 ; CHECK-BE-NEXT: vperm v3, v5, v3, v0
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
; CHECK-BE-NEXT: xvcvuxwsp vs2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
; CHECK-BE-NEXT: vperm v2, v5, v2, v0
; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = uitofp <16 x i16> %a to <16 x float> %1 = uitofp <16 x i16> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }
Show All 18 Lines
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: li r4, 2
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: vextuhrx r4, r4, v2
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-P9-NEXT: extsh r3, r3
; CHECK-P9-NEXT: extsh r4, r4
; CHECK-P9-NEXT: mtvsrwa f0, r3 ; CHECK-P9-NEXT: mtvsrwa f0, r3
; CHECK-P9-NEXT: mtvsrwa f1, r4 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: extsh r3, r3
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrwa f0, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvsxdsp f1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 2 ; CHECK-BE-NEXT: li r3, 2
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: vextuhlx r4, r4, v2
; CHECK-BE-NEXT: extsh r3, r3 ; CHECK-BE-NEXT: extsh r3, r3
; CHECK-BE-NEXT: extsh r4, r4
; CHECK-BE-NEXT: mtvsrwa f0, r3 ; CHECK-BE-NEXT: mtvsrwa f0, r3
; CHECK-BE-NEXT: mtvsrwa f1, r4 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvsxdsp f0, f0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: extsh r3, r3
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtvsrwa f0, r3
; CHECK-BE-NEXT: xscvsxdsp f0, f0 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
; CHECK-BE-NEXT: xscvsxdsp f1, f1
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: xscvdpspn v3, f1 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = sitofp <2 x i16> %0 to <2 x float> %1 = sitofp <2 x i16> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
Show All 33 Lines
; CHECK-P8-NEXT: stvx v4, 0, r3 ; CHECK-P8-NEXT: stvx v4, 0, r3
; CHECK-P8-NEXT: stvx v5, r3, r6 ; CHECK-P8-NEXT: stvx v5, r3, r6
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: vmrglh v4, v3, v3 ; CHECK-P9-NEXT: vmrglh v4, v3, v3
; CHECK-P9-NEXT: vmrghh v3, v3, v3 ; CHECK-P9-NEXT: vmrghh v3, v3, v3
; CHECK-P9-NEXT: vmrglh v5, v2, v2 ; CHECK-P9-NEXT: vextsh2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
; CHECK-P9-NEXT: vmrglh v3, v2, v2
; CHECK-P9-NEXT: vmrghh v2, v2, v2 ; CHECK-P9-NEXT: vmrghh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v4, v4 ; CHECK-P9-NEXT: vextsh2w v4, v4
; CHECK-P9-NEXT: xvcvsxwsp vs0, v4
; CHECK-P9-NEXT: vextsh2w v3, v3 ; CHECK-P9-NEXT: vextsh2w v3, v3
; CHECK-P9-NEXT: vextsh2w v5, v5
; CHECK-P9-NEXT: vextsh2w v2, v2 ; CHECK-P9-NEXT: vextsh2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs0, v4 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
; CHECK-P9-NEXT: xvcvsxwsp vs2, v5
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r5
; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4
; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4
; CHECK-BE-NEXT: vmrghh v3, v3, v3 ; CHECK-BE-NEXT: vmrghh v3, v3, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v5, v0 ; CHECK-BE-NEXT: vextsh2w v0, v0
; CHECK-BE-NEXT: vextsh2w v4, v4 ; CHECK-BE-NEXT: vextsh2w v4, v4
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs0, v5 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v0
; CHECK-BE-NEXT: xvcvsxwsp vs1, v4 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v4
; CHECK-BE-NEXT: xvcvsxwsp vs2, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = sitofp <16 x i16> %a to <16 x float> %1 = sitofp <16 x i16> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Show All 18 Lines
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: lxvx v2, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v3, v2
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: vperm v2, v3, v4, v2
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = uitofp <2 x i16> %0 to <2 x double> %1 = uitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 17 Lines
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI1_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: vperm v2, v5, v4, v2 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v5, v4, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v2 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r6, r6, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: vperm v2, v4, v5, v2 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: vperm v3, v5, v4, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs0, v2 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = uitofp <4 x i16> %0 to <4 x double> %1 = uitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
Show All 32 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: xxlxor v1, v1, v1
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI2_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI2_2@toc@l ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r7, r7, .LCPI2_3@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r5 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: vperm v3, v1, v2, v3
; CHECK-P9-NEXT: vperm v4, v1, v2, v4
; CHECK-P9-NEXT: vperm v5, v1, v2, v5
; CHECK-P9-NEXT: vperm v2, v1, v2, v0
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: xvcvuxddp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvuxddp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI2_3@toc@ha
; CHECK-BE-NEXT: xxlxor v1, v1, v1
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI2_1@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI2_2@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI2_3@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: lxvx v5, 0, r6
; CHECK-BE-NEXT: lxvx v0, 0, r7
; CHECK-BE-NEXT: vperm v3, v2, v1, v3
; CHECK-BE-NEXT: vperm v4, v1, v2, v4
; CHECK-BE-NEXT: vperm v5, v1, v2, v5
; CHECK-BE-NEXT: vperm v2, v1, v2, v0
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: xvcvuxddp vs1, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs2, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v2 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <8 x i16> %a to <8 x double> %0 = uitofp <8 x i16> %a to <8 x double>
store <8 x double> %0, <8 x double>* %agg.result, align 64 store <8 x double> %0, <8 x double>* %agg.result, align 64
ret void ret void
} }
define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: addis r6, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r7, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxv v0, 0(r4) ; CHECK-P9-NEXT: lxvx v4, 0, r4
; CHECK-P9-NEXT: lxv v1, 16(r4) ; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: xxlxor v6, v6, v6 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: addi r7, r7, .LCPI3_2@toc@l ; CHECK-P9-NEXT: xvcvuxddp vs0, v0
; CHECK-P9-NEXT: addi r8, r8, .LCPI3_3@toc@l ; CHECK-P9-NEXT: lxvx v0, 0, r4
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r7 ; CHECK-P9-NEXT: vperm v1, v5, v3, v0
; CHECK-P9-NEXT: lxvx v5, 0, r8 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vperm v7, v6, v0, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v1
; CHECK-P9-NEXT: vperm v8, v6, v0, v3 ; CHECK-P9-NEXT: lxvx v1, 0, r4
; CHECK-P9-NEXT: vperm v9, v6, v0, v4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: vperm v0, v6, v0, v5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v2, v6, v1, v2 ; CHECK-P9-NEXT: vperm v6, v5, v3, v1
; CHECK-P9-NEXT: vperm v3, v6, v1, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vperm v4, v6, v1, v4 ; CHECK-P9-NEXT: xvcvuxddp vs2, v6
; CHECK-P9-NEXT: vperm v5, v6, v1, v5 ; CHECK-P9-NEXT: lxvx v6, 0, r4
; CHECK-P9-NEXT: xvcvuxddp vs0, v7 ; CHECK-P9-NEXT: vperm v3, v5, v3, v6
; CHECK-P9-NEXT: xvcvuxddp vs1, v8 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v9 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
; CHECK-P9-NEXT: xvcvuxddp vs3, v0 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
; CHECK-P9-NEXT: xvcvuxddp vs4, v2 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v0
; CHECK-P9-NEXT: xvcvuxddp vs5, v3 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
; CHECK-P9-NEXT: xvcvuxddp vs6, v4 ; CHECK-P9-NEXT: vperm v3, v5, v2, v1
; CHECK-P9-NEXT: xvcvuxddp vs7, v5 ; CHECK-P9-NEXT: vperm v2, v5, v2, v6
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: addis r6, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r7, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addis r8, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxv v0, 0(r4) ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: lxv v1, 16(r4) ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: xxlxor v6, v6, v6 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: addi r6, r6, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI3_2@toc@l ; CHECK-BE-NEXT: xvcvuxddp vs0, v0
; CHECK-BE-NEXT: addi r8, r8, .LCPI3_3@toc@l ; CHECK-BE-NEXT: lxvx v0, 0, r4
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r7 ; CHECK-BE-NEXT: vperm v1, v5, v3, v0
; CHECK-BE-NEXT: lxvx v5, 0, r8 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vperm v7, v0, v6, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v1
; CHECK-BE-NEXT: vperm v8, v6, v0, v3 ; CHECK-BE-NEXT: lxvx v1, 0, r4
; CHECK-BE-NEXT: vperm v9, v6, v0, v4 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: vperm v0, v6, v0, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v2, v1, v6, v2 ; CHECK-BE-NEXT: vperm v6, v5, v3, v1
; CHECK-BE-NEXT: vperm v3, v6, v1, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vperm v4, v6, v1, v4 ; CHECK-BE-NEXT: xvcvuxddp vs2, v6
; CHECK-BE-NEXT: vperm v5, v6, v1, v5 ; CHECK-BE-NEXT: lxvx v6, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs0, v7 ; CHECK-BE-NEXT: vperm v3, v5, v3, v6
; CHECK-BE-NEXT: xvcvuxddp vs1, v8 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v9 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
; CHECK-BE-NEXT: xvcvuxddp vs3, v0 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
; CHECK-BE-NEXT: xvcvuxddp vs4, v2 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
; CHECK-BE-NEXT: vperm v3, v5, v2, v0
; CHECK-BE-NEXT: xvcvuxddp vs5, v3 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
; CHECK-BE-NEXT: xvcvuxddp vs6, v4 ; CHECK-BE-NEXT: vperm v3, v5, v2, v1
; CHECK-BE-NEXT: xvcvuxddp vs7, v5 ; CHECK-BE-NEXT: vperm v2, v5, v2, v6
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = uitofp <16 x i16> %a to <16 x double> %1 = uitofp <16 x i16> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }
Show All 12 Lines
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsld v2, v2, v3
; CHECK-P8-NEXT: vsrad v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3
; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx v2, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = sitofp <2 x i16> %0 to <2 x double> %1 = sitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 25 Lines
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r6, r6, .LCPI5_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v2, v4, v4, v2 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: vperm v3, v4, v4, v3 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r6, r6, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r6
; CHECK-BE-NEXT: vperm v2, v5, v4, v2
; CHECK-BE-NEXT: vperm v3, v4, v4, v3
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v2 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = sitofp <4 x i16> %0 to <4 x double> %1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI6_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI6_2@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r7, r7, .LCPI6_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v4, v2, v2, v4
; CHECK-P9-NEXT: vperm v5, v2, v2, v5
; CHECK-P9-NEXT: vperm v2, v2, v2, v0
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: vextsh2d v5, v5
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvsxddp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: xxlxor v1, v1, v1
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI6_1@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI6_2@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI6_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: lxvx v5, 0, r6
; CHECK-BE-NEXT: lxvx v0, 0, r7
; CHECK-BE-NEXT: vperm v3, v1, v2, v3
; CHECK-BE-NEXT: vperm v4, v1, v2, v4
; CHECK-BE-NEXT: vperm v5, v2, v2, v5
; CHECK-BE-NEXT: vperm v2, v2, v2, v0
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v5, v5
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvsxddp vs2, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <8 x i16> %a to <8 x double> %0 = sitofp <8 x i16> %a to <8 x double>
store <8 x double> %0, <8 x double>* %agg.result, align 64 store <8 x double> %0, <8 x double>* %agg.result, align 64
ret void ret void
} }
define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: lxv v0, 0(r4)
; CHECK-P9-NEXT: lxv v1, 16(r4)
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI7_1@toc@l ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addi r7, r7, .LCPI7_2@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r5
; CHECK-P9-NEXT: addi r8, r8, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: lxvx v5, 0, r5
; CHECK-P9-NEXT: lxvx v4, 0, r7 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: lxvx v5, 0, r8 ; CHECK-P9-NEXT: vperm v4, v2, v2, v3
; CHECK-P9-NEXT: vperm v6, v0, v0, v2 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vperm v7, v0, v0, v3
; CHECK-P9-NEXT: vperm v8, v0, v0, v4
; CHECK-P9-NEXT: vperm v0, v0, v0, v5
; CHECK-P9-NEXT: vperm v2, v1, v1, v2
; CHECK-P9-NEXT: vperm v3, v1, v1, v3
; CHECK-P9-NEXT: vperm v4, v1, v1, v4
; CHECK-P9-NEXT: vperm v5, v1, v1, v5
; CHECK-P9-NEXT: vextsh2d v1, v6
; CHECK-P9-NEXT: vextsh2d v6, v7
; CHECK-P9-NEXT: vextsh2d v7, v8
; CHECK-P9-NEXT: vextsh2d v0, v0
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: vextsh2d v5, v5 ; CHECK-P9-NEXT: lxvx v0, 0, r5
; CHECK-P9-NEXT: xvcvsxddp vs0, v1 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: xvcvsxddp vs1, v6 ; CHECK-P9-NEXT: xvcvsxddp vs0, v4
; CHECK-P9-NEXT: xvcvsxddp vs2, v7 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5
; CHECK-P9-NEXT: xvcvsxddp vs3, v0 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l
; CHECK-P9-NEXT: xvcvsxddp vs4, v2 ; CHECK-P9-NEXT: lxvx v1, 0, r5
; CHECK-P9-NEXT: xvcvsxddp vs5, v3 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs6, v4 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4
; CHECK-P9-NEXT: xvcvsxddp vs7, v5 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0
; CHECK-P9-NEXT: vperm v2, v2, v2, v1
; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs2, v4
; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v3
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: xvcvsxddp vs4, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v5
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs5, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v0
; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs6, v2
; CHECK-P9-NEXT: vperm v2, v4, v4, v1
; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addis r8, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: xxlxor v6, v6, v6
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r6, r6, .LCPI7_1@toc@l ; CHECK-BE-NEXT: lxvx v2, 0, r5
; CHECK-BE-NEXT: addi r7, r7, .LCPI7_2@toc@l ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addi r8, r8, .LCPI7_3@toc@l ; CHECK-BE-NEXT: lxv v1, 16(r4)
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: lxvx v5, 0, r6 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-BE-NEXT: lxvx v0, 0, r7 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: lxvx v1, 0, r8 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: vperm v7, v6, v3, v4 ; CHECK-BE-NEXT: vperm v0, v5, v4, v2
; CHECK-BE-NEXT: vperm v8, v6, v3, v5 ; CHECK-BE-NEXT: lxvx v3, 0, r5
; CHECK-BE-NEXT: vperm v4, v6, v2, v4 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2
; CHECK-BE-NEXT: vperm v5, v6, v2, v5 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vperm v6, v3, v3, v0 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v3, v1
; CHECK-BE-NEXT: vperm v0, v2, v2, v0
; CHECK-BE-NEXT: vperm v2, v2, v2, v1
; CHECK-BE-NEXT: vextsh2d v1, v7
; CHECK-BE-NEXT: vextsh2d v7, v8
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v5, v5
; CHECK-BE-NEXT: vextsh2d v6, v6
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs2, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs0, v1
; CHECK-BE-NEXT: xvcvsxddp vs1, v7
; CHECK-BE-NEXT: xvcvsxddp vs2, v4
; CHECK-BE-NEXT: xvcvsxddp vs3, v5
; CHECK-BE-NEXT: xvcvsxddp vs4, v6
; CHECK-BE-NEXT: xvcvsxddp vs5, v3
; CHECK-BE-NEXT: xvcvsxddp vs6, v0
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: xvcvsxddp vs0, v0
; CHECK-BE-NEXT: vperm v0, v5, v4, v3
; CHECK-BE-NEXT: vperm v3, v4, v4, v2
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs1, v0
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v1, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs6, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v3
; CHECK-BE-NEXT: vperm v4, v4, v4, v3
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = sitofp <16 x i16> %a to <16 x double> %1 = sitofp <16 x i16> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: xxmrghw v3, vs1, vs1 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxmrglw v4, vs0, vs0 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
; CHECK-P9-NEXT: xxmrghw v5, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: xvcvuxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
; CHECK-P9-NEXT: xvcvuxwdp vs1, v3
; CHECK-P9-NEXT: xvcvuxwdp vs2, v4
; CHECK-P9-NEXT: xvcvuxwdp vs3, v5
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: xxmrglw v3, vs1, vs1 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxmrghw v4, vs0, vs0 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
; CHECK-BE-NEXT: xxmrglw v5, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: xvcvuxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
; CHECK-BE-NEXT: xvcvuxwdp vs1, v3
; CHECK-BE-NEXT: xvcvuxwdp vs2, v4
; CHECK-BE-NEXT: xvcvuxwdp vs3, v5
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x i32>, <8 x i32>* %0, align 32 %a = load <8 x i32>, <8 x i32>* %0, align 32
%1 = uitofp <8 x i32> %a to <8 x double> %1 = uitofp <8 x i32> %a to <8 x double>
store <8 x double> %1, <8 x double>* %agg.result, align 64 store <8 x double> %1, <8 x double>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
; CHECK-P9-NEXT: xxmrghw v3, vs1, vs1 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: xxmrglw v4, vs0, vs0 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: xxmrghw v5, vs0, vs0
; CHECK-P9-NEXT: xxmrglw v0, vs3, vs3
; CHECK-P9-NEXT: xxmrghw v1, vs3, vs3
; CHECK-P9-NEXT: xxmrglw v6, vs2, vs2
; CHECK-P9-NEXT: xxmrghw v7, vs2, vs2
; CHECK-P9-NEXT: xvcvuxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
; CHECK-P9-NEXT: xvcvuxwdp vs1, v3 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvuxwdp vs2, v4 ; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
; CHECK-P9-NEXT: xvcvuxwdp vs3, v5 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvuxwdp vs4, v0 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: xvcvuxwdp vs5, v1 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xvcvuxwdp vs6, v6 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
; CHECK-P9-NEXT: xvcvuxwdp vs7, v7 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: xvcvuxwdp vs6, v2
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 48(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: xvcvuxwdp vs5, v2
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
; CHECK-P9-NEXT: xvcvuxwdp vs7, v2
; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
; CHECK-P9-NEXT: stxv vs6, 64(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: xvcvuxwdp vs4, v2
; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs2, 48(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
; CHECK-BE-NEXT: xxmrglw v3, vs1, vs1 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: xxmrghw v4, vs0, vs0 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrglw v5, vs0, vs0
; CHECK-BE-NEXT: xxmrghw v0, vs3, vs3
; CHECK-BE-NEXT: xxmrglw v1, vs3, vs3
; CHECK-BE-NEXT: xxmrghw v6, vs2, vs2
; CHECK-BE-NEXT: xxmrglw v7, vs2, vs2
; CHECK-BE-NEXT: xvcvuxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
; CHECK-BE-NEXT: xvcvuxwdp vs1, v3 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvuxwdp vs2, v4 ; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
; CHECK-BE-NEXT: xvcvuxwdp vs3, v5 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvuxwdp vs4, v0 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: xvcvuxwdp vs5, v1 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xvcvuxwdp vs6, v6 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
; CHECK-BE-NEXT: xvcvuxwdp vs7, v7 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: xvcvuxwdp vs6, v2
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xxmrglw v2, vs5, vs5
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: xvcvuxwdp vs5, v2
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
; CHECK-BE-NEXT: xvcvuxwdp vs7, v2
; CHECK-BE-NEXT: xxmrglw v2, vs4, vs4
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: xvcvuxwdp vs4, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs4, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i32>, <16 x i32>* %0, align 64 %a = load <16 x i32>, <16 x i32>* %0, align 64
%1 = uitofp <16 x i32> %a to <16 x double> %1 = uitofp <16 x i32> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: lxv vs1, 0(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
; CHECK-P9-NEXT: xxmrghw v3, vs1, vs1 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
; CHECK-P9-NEXT: xxmrglw v4, vs0, vs0 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
; CHECK-P9-NEXT: xxmrghw v5, vs0, vs0 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: xvcvsxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
; CHECK-P9-NEXT: xvcvsxwdp vs1, v3
; CHECK-P9-NEXT: xvcvsxwdp vs2, v4
; CHECK-P9-NEXT: xvcvsxwdp vs3, v5
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
; CHECK-BE-NEXT: xxmrglw v3, vs1, vs1 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
; CHECK-BE-NEXT: xxmrghw v4, vs0, vs0 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
; CHECK-BE-NEXT: xxmrglw v5, vs0, vs0 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: xvcvsxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
; CHECK-BE-NEXT: xvcvsxwdp vs1, v3
; CHECK-BE-NEXT: xvcvsxwdp vs2, v4
; CHECK-BE-NEXT: xvcvsxwdp vs3, v5
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x i32>, <8 x i32>* %0, align 32 %a = load <8 x i32>, <8 x i32>* %0, align 32
%1 = sitofp <8 x i32> %a to <8 x double> %1 = sitofp <8 x i32> %a to <8 x double>
store <8 x double> %1, <8 x double>* %agg.result, align 64 store <8 x double> %1, <8 x double>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r7 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r7
; CHECK-P8-NEXT: stxvd2x vs3, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs0, 16(r4) ; CHECK-P9-NEXT: lxv vs0, 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
; CHECK-P9-NEXT: lxv vs2, 48(r4) ; CHECK-P9-NEXT: lxv vs2, 16(r4)
; CHECK-P9-NEXT: lxv vs3, 32(r4) ; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
; CHECK-P9-NEXT: xxmrghw v3, vs1, vs1 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
; CHECK-P9-NEXT: xxmrglw v4, vs0, vs0 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: xxmrghw v5, vs0, vs0
; CHECK-P9-NEXT: xxmrglw v0, vs3, vs3
; CHECK-P9-NEXT: xxmrghw v1, vs3, vs3
; CHECK-P9-NEXT: xxmrglw v6, vs2, vs2
; CHECK-P9-NEXT: xxmrghw v7, vs2, vs2
; CHECK-P9-NEXT: xvcvsxwdp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
; CHECK-P9-NEXT: xvcvsxwdp vs1, v3 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvsxwdp vs2, v4 ; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
; CHECK-P9-NEXT: xvcvsxwdp vs3, v5 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
; CHECK-P9-NEXT: xvcvsxwdp vs4, v0 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
; CHECK-P9-NEXT: xvcvsxwdp vs5, v1 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: xvcvsxwdp vs6, v6 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
; CHECK-P9-NEXT: xvcvsxwdp vs7, v7 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: xvcvsxwdp vs6, v2
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs3, 32(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 48(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: xvcvsxwdp vs5, v2
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
; CHECK-P9-NEXT: xvcvsxwdp vs7, v2
; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
; CHECK-P9-NEXT: stxv vs6, 64(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: xvcvsxwdp vs4, v2
; CHECK-P9-NEXT: stxv vs7, 96(r3)
; CHECK-P9-NEXT: stxv vs4, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs0, 16(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: lxv vs2, 48(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
; CHECK-BE-NEXT: xxmrglw v3, vs1, vs1 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
; CHECK-BE-NEXT: xxmrghw v4, vs0, vs0 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: xxmrglw v5, vs0, vs0
; CHECK-BE-NEXT: xxmrghw v0, vs3, vs3
; CHECK-BE-NEXT: xxmrglw v1, vs3, vs3
; CHECK-BE-NEXT: xxmrghw v6, vs2, vs2
; CHECK-BE-NEXT: xxmrglw v7, vs2, vs2
; CHECK-BE-NEXT: xvcvsxwdp vs0, v2 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
; CHECK-BE-NEXT: xvcvsxwdp vs1, v3 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvsxwdp vs2, v4 ; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
; CHECK-BE-NEXT: xvcvsxwdp vs3, v5 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
; CHECK-BE-NEXT: xvcvsxwdp vs4, v0 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: xvcvsxwdp vs5, v1 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: xvcvsxwdp vs6, v6 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
; CHECK-BE-NEXT: xvcvsxwdp vs7, v7 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: xvcvsxwdp vs6, v2
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xxmrglw v2, vs5, vs5
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 48(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: xvcvsxwdp vs5, v2
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
; CHECK-BE-NEXT: xvcvsxwdp vs7, v2
; CHECK-BE-NEXT: xxmrglw v2, vs4, vs4
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: xvcvsxwdp vs4, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: stxv vs4, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i32>, <16 x i32>* %0, align 64 %a = load <16 x i32>, <16 x i32>* %0, align 64
%1 = sitofp <16 x i32> %a to <16 x double> %1 = sitofp <16 x i32> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

Show All 22 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxlor vs1, v2, v2
; CHECK-P9-NEXT: xscvuxdsp f1, f1
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xxlor vs0, v2, v2
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xxlor vs1, v2, v2 ; CHECK-BE-NEXT: xxlor vs1, v2, v2
; CHECK-BE-NEXT: xscvuxdsp f1, f1 ; CHECK-BE-NEXT: xscvuxdsp f1, f1
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; CHECK-P8-NEXT: xvcvuxdsp vs0, v2 ; CHECK-P8-NEXT: xvcvuxdsp vs0, v2
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: vpkudum v2, v2, v3 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: xvcvuxdsp vs1, v2 ; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: lxv v3, 16(r3) ; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: xvcvuxdsp vs1, v2 ; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x i64>, <4 x i64>* %0, align 32 %a = load <4 x i64>, <4 x i64>* %0, align 32
%1 = uitofp <4 x i64> %a to <4 x float> %1 = uitofp <4 x i64> %a to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 {
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; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
; CHECK-P9-NEXT: xvcvuxdsp vs1, v4 ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs2, v3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: vpkudum v3, v4, v5
; CHECK-P9-NEXT: stxv v3, 0(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
; CHECK-P9-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P9-NEXT: stxv v2, 16(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: vpkudum v3, v5, v4
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
; CHECK-BE-NEXT: xvcvuxdsp vs1, v4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs2, v3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs3, v2 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: vpkudum v3, v4, v5
; CHECK-BE-NEXT: stxv v3, 0(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
; CHECK-BE-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-BE-NEXT: stxv v2, 16(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: vpkudum v3, v5, v4
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x i64>, <8 x i64>* %0, align 64 %a = load <8 x i64>, <8 x i64>* %0, align 64
%1 = uitofp <8 x i64> %a to <8 x float> %1 = uitofp <8 x i64> %a to <8 x float>
store <8 x float> %1, <8 x float>* %agg.result, align 32 store <8 x float> %1, <8 x float>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stvx v2, r3, r7
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: xvcvuxdsp vs0, v7
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-P9-NEXT: lxv v0, 112(r4) ; CHECK-P9-NEXT: xvcvuxdsp vs0, v6
; CHECK-P9-NEXT: lxv v1, 96(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 80(r4) ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: lxv v7, 64(r4) ; CHECK-P9-NEXT: xvcvuxdsp vs0, v1
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: vpkudum v1, v6, v7
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v0
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
; CHECK-P9-NEXT: xvcvuxdsp vs1, v4 ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs2, v3 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
; CHECK-P9-NEXT: xvcvuxdsp vs3, v2 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs4, v7 ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: xvcvuxdsp vs5, v6 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
; CHECK-P9-NEXT: xvcvuxdsp vs6, v1 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs7, v0 ; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: stxv v0, 16(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
; CHECK-P9-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-P9-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-P9-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-P9-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: vpkudum v3, v5, v4
; CHECK-P9-NEXT: vpkudum v4, v1, v0
; CHECK-P9-NEXT: vpkudum v5, v7, v6
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvuxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: stxv v2, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 32(r4) ; CHECK-BE-NEXT: lxv v7, 16(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: xvcvuxdsp vs0, v7
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v6, 0(r4)
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-BE-NEXT: lxv v0, 96(r4) ; CHECK-BE-NEXT: xvcvuxdsp vs0, v6
; CHECK-BE-NEXT: lxv v1, 112(r4) ; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: lxv v6, 64(r4) ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: lxv v7, 80(r4) ; CHECK-BE-NEXT: xvcvuxdsp vs0, v1
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: vpkudum v1, v6, v7
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v0
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
; CHECK-BE-NEXT: xvcvuxdsp vs1, v4 ; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs2, v3 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
; CHECK-BE-NEXT: xvcvuxdsp vs3, v2 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs4, v7 ; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: xvcvuxdsp vs5, v6 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
; CHECK-BE-NEXT: xvcvuxdsp vs6, v1 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs7, v0 ; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: stxv v0, 16(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
; CHECK-BE-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-BE-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-BE-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-BE-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: vpkudum v3, v5, v4
; CHECK-BE-NEXT: vpkudum v4, v1, v0
; CHECK-BE-NEXT: vpkudum v5, v7, v6
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvuxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: stxv v2, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i64>, <16 x i64>* %0, align 128 %a = load <16 x i64>, <16 x i64>* %0, align 128
%1 = uitofp <16 x i64> %a to <16 x float> %1 = uitofp <16 x i64> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }
Show All 11 Lines
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xxlor vs1, v2, v2
; CHECK-P9-NEXT: xscvsxdsp f1, f1
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: xxlor vs0, v2, v2
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: xxlor vs1, v2, v2 ; CHECK-BE-NEXT: xxlor vs1, v2, v2
; CHECK-BE-NEXT: xscvsxdsp f1, f1 ; CHECK-BE-NEXT: xscvsxdsp f1, f1
Show All 21 Lines
; CHECK-P8-NEXT: xvcvsxdsp vs0, v2 ; CHECK-P8-NEXT: xvcvsxdsp vs0, v2
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P8-NEXT: vpkudum v2, v2, v3 ; CHECK-P8-NEXT: vpkudum v2, v2, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: xvcvsxdsp vs1, v2 ; CHECK-P9-NEXT: lxv v2, 16(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: lxv v3, 16(r3) ; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: xvcvsxdsp vs1, v2 ; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x i64>, <4 x i64>* %0, align 32 %a = load <4 x i64>, <4 x i64>* %0, align 32
%1 = sitofp <4 x i64> %a to <4 x float> %1 = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 {
Show All 21 Lines
; CHECK-P8-NEXT: vpkudum v2, v3, v2 ; CHECK-P8-NEXT: vpkudum v2, v3, v2
; CHECK-P8-NEXT: vpkudum v3, v4, v5 ; CHECK-P8-NEXT: vpkudum v3, v4, v5
; CHECK-P8-NEXT: stvx v2, r3, r5 ; CHECK-P8-NEXT: stvx v2, r3, r5
; CHECK-P8-NEXT: stvx v3, 0, r3 ; CHECK-P8-NEXT: stvx v3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 0(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
; CHECK-P9-NEXT: xvcvsxdsp vs1, v4 ; CHECK-P9-NEXT: lxv v4, 16(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs2, v3 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
; CHECK-P9-NEXT: lxv v3, 32(r4)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: lxv v2, 48(r4)
; CHECK-P9-NEXT: vpkudum v3, v4, v5
; CHECK-P9-NEXT: stxv v3, 0(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: vpkudum v2, v2, v4
; CHECK-P9-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P9-NEXT: stxv v2, 16(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: vpkudum v3, v5, v4
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
; CHECK-BE-NEXT: xvcvsxdsp vs1, v4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs2, v3 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs3, v2 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
; CHECK-BE-NEXT: lxv v3, 48(r4)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: lxv v2, 32(r4)
; CHECK-BE-NEXT: vpkudum v3, v4, v5
; CHECK-BE-NEXT: stxv v3, 0(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: vpkudum v2, v2, v4
; CHECK-BE-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-BE-NEXT: stxv v2, 16(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs3, vs3, 3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: vpkudum v3, v5, v4
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x i64>, <8 x i64>* %0, align 64 %a = load <8 x i64>, <8 x i64>* %0, align 64
%1 = sitofp <8 x i64> %a to <8 x float> %1 = sitofp <8 x i64> %a to <8 x float>
store <8 x float> %1, <8 x float>* %agg.result, align 32 store <8 x float> %1, <8 x float>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stvx v2, r3, r7 ; CHECK-P8-NEXT: stvx v2, r3, r7
; CHECK-P8-NEXT: stvx v3, r3, r5 ; CHECK-P8-NEXT: stvx v3, r3, r5
; CHECK-P8-NEXT: stvx v4, r3, r6 ; CHECK-P8-NEXT: stvx v4, r3, r6
; CHECK-P8-NEXT: stvx v5, 0, r3 ; CHECK-P8-NEXT: stvx v5, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: xvcvsxdsp vs0, v7
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-P9-NEXT: lxv v0, 112(r4) ; CHECK-P9-NEXT: xvcvsxdsp vs0, v6
; CHECK-P9-NEXT: lxv v1, 96(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 80(r4) ; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: lxv v7, 64(r4) ; CHECK-P9-NEXT: xvcvsxdsp vs0, v1
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: vpkudum v1, v6, v7
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v0
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
; CHECK-P9-NEXT: xvcvsxdsp vs1, v4 ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs2, v3 ; CHECK-P9-NEXT: vpkudum v0, v0, v6
; CHECK-P9-NEXT: xvcvsxdsp vs3, v2 ; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs4, v7 ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: xvcvsxdsp vs5, v6 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
; CHECK-P9-NEXT: xvcvsxdsp vs6, v1 ; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs7, v0 ; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-P9-NEXT: stxv v0, 16(r3)
; CHECK-P9-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-P9-NEXT: stxv v1, 0(r3)
; CHECK-P9-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-P9-NEXT: vpkudum v4, v4, v5
; CHECK-P9-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-P9-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-P9-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-P9-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-P9-NEXT: vpkudum v2, v3, v2
; CHECK-P9-NEXT: vpkudum v3, v5, v4
; CHECK-P9-NEXT: vpkudum v4, v1, v0
; CHECK-P9-NEXT: vpkudum v5, v7, v6
; CHECK-P9-NEXT: stxv v3, 16(r3)
; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: stxv v5, 48(r3)
; CHECK-P9-NEXT: stxv v4, 32(r3) ; CHECK-P9-NEXT: stxv v4, 32(r3)
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-P9-NEXT: xvcvsxdsp vs0, v2
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-P9-NEXT: vpkudum v2, v2, v3
; CHECK-P9-NEXT: stxv v2, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 32(r4) ; CHECK-BE-NEXT: lxv v7, 16(r4)
; CHECK-BE-NEXT: lxv v3, 48(r4) ; CHECK-BE-NEXT: xvcvsxdsp vs0, v7
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v6, 0(r4)
; CHECK-BE-NEXT: lxv v5, 16(r4) ; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3
; CHECK-BE-NEXT: lxv v0, 96(r4) ; CHECK-BE-NEXT: xvcvsxdsp vs0, v6
; CHECK-BE-NEXT: lxv v1, 112(r4) ; CHECK-BE-NEXT: lxv v1, 48(r4)
; CHECK-BE-NEXT: lxv v6, 64(r4) ; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: lxv v7, 80(r4) ; CHECK-BE-NEXT: xvcvsxdsp vs0, v1
; CHECK-BE-NEXT: lxv v0, 32(r4)
; CHECK-BE-NEXT: vpkudum v1, v6, v7
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v0
; CHECK-BE-NEXT: lxv v5, 80(r4)
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
; CHECK-BE-NEXT: xvcvsxdsp vs1, v4 ; CHECK-BE-NEXT: lxv v4, 64(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs2, v3 ; CHECK-BE-NEXT: vpkudum v0, v0, v6
; CHECK-BE-NEXT: xvcvsxdsp vs3, v2 ; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs4, v7 ; CHECK-BE-NEXT: lxv v3, 112(r4)
; CHECK-BE-NEXT: xvcvsxdsp vs5, v6 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
; CHECK-BE-NEXT: xvcvsxdsp vs6, v1 ; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs7, v0 ; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 ; CHECK-BE-NEXT: lxv v2, 96(r4)
; CHECK-BE-NEXT: xxsldwi v3, vs1, vs1, 3 ; CHECK-BE-NEXT: stxv v0, 16(r3)
; CHECK-BE-NEXT: xxsldwi v4, vs2, vs2, 3 ; CHECK-BE-NEXT: stxv v1, 0(r3)
; CHECK-BE-NEXT: xxsldwi v5, vs3, vs3, 3 ; CHECK-BE-NEXT: vpkudum v4, v4, v5
; CHECK-BE-NEXT: xxsldwi v0, vs4, vs4, 3
; CHECK-BE-NEXT: xxsldwi v1, vs5, vs5, 3
; CHECK-BE-NEXT: xxsldwi v6, vs6, vs6, 3
; CHECK-BE-NEXT: xxsldwi v7, vs7, vs7, 3
; CHECK-BE-NEXT: vpkudum v2, v3, v2
; CHECK-BE-NEXT: vpkudum v3, v5, v4
; CHECK-BE-NEXT: vpkudum v4, v1, v0
; CHECK-BE-NEXT: vpkudum v5, v7, v6
; CHECK-BE-NEXT: stxv v3, 16(r3)
; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: stxv v4, 32(r3) ; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
; CHECK-BE-NEXT: xvcvsxdsp vs0, v2
; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3
; CHECK-BE-NEXT: vpkudum v2, v2, v3
; CHECK-BE-NEXT: stxv v2, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i64>, <16 x i64>* %0, align 128 %a = load <16 x i64>, <16 x i64>* %0, align 128
%1 = sitofp <16 x i64> %a to <16 x float> %1 = sitofp <16 x i64> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

Show All 29 Lines
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: li r4, 1
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: vextubrx r4, r4, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-P9-NEXT: rlwinm r4, r4, 0, 24, 31
; CHECK-P9-NEXT: mtvsrwz f0, r3 ; CHECK-P9-NEXT: mtvsrwz f0, r3
; CHECK-P9-NEXT: mtvsrwz f1, r4 ; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvuxdsp f1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 1 ; CHECK-BE-NEXT: li r3, 1
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: vextublx r3, r3, v2 ; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: vextublx r4, r4, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-BE-NEXT: rlwinm r4, r4, 0, 24, 31
; CHECK-BE-NEXT: mtvsrwz f0, r3 ; CHECK-BE-NEXT: mtvsrwz f0, r3
; CHECK-BE-NEXT: mtvsrwz f1, r4 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtvsrwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: xscvuxdsp f1, f1
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: xscvdpspn v3, f1 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = uitofp <2 x i8> %0 to <2 x float> %1 = uitofp <2 x i8> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: lxvx v2, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v3, v2
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: vperm v2, v3, v4, v2
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = uitofp <4 x i8> %0 to <4 x float> %1 = uitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 15 Lines
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI2_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: vperm v2, v5, v4, v2 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v5, v4, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r6, r6, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: vperm v2, v4, v5, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: vperm v3, v5, v4, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxwsp vs0, v2 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = uitofp <8 x i8> %0 to <8 x float> %1 = uitofp <8 x i8> %0 to <8 x float>
store <8 x float> %1, <8 x float>* %agg.result, align 32 store <8 x float> %1, <8 x float>* %agg.result, align 32
ret void ret void
} }
Show All 28 Lines
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: stvx v5, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: xxlxor v1, v1, v1
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r7, r7, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r5 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: vperm v3, v1, v2, v3
; CHECK-P9-NEXT: vperm v4, v1, v2, v4
; CHECK-P9-NEXT: vperm v5, v1, v2, v5
; CHECK-P9-NEXT: vperm v2, v1, v2, v0
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: xvcvuxwsp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvuxwsp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: xxlxor v1, v1, v1
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: lxvx v5, 0, r6
; CHECK-BE-NEXT: lxvx v0, 0, r7
; CHECK-BE-NEXT: vperm v3, v2, v1, v3
; CHECK-BE-NEXT: vperm v4, v1, v2, v4
; CHECK-BE-NEXT: vperm v5, v1, v2, v5
; CHECK-BE-NEXT: vperm v2, v1, v2, v0
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: xvcvuxwsp vs1, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxwsp vs2, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <16 x i8> %a to <16 x float> %0 = uitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
ret void ret void
} }
define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
Show All 17 Lines
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: li r4, 1
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: vextubrx r4, r4, v2
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-P9-NEXT: extsb r3, r3
; CHECK-P9-NEXT: extsb r4, r4
; CHECK-P9-NEXT: mtvsrwa f0, r3 ; CHECK-P9-NEXT: mtvsrwa f0, r3
; CHECK-P9-NEXT: mtvsrwa f1, r4 ; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: extsb r3, r3
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtvsrwa f0, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvsxdsp f1, f1
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xscvdpspn vs1, f1
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 1 ; CHECK-BE-NEXT: li r3, 1
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: vextublx r3, r3, v2 ; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: vextublx r4, r4, v2
; CHECK-BE-NEXT: extsb r3, r3 ; CHECK-BE-NEXT: extsb r3, r3
; CHECK-BE-NEXT: extsb r4, r4
; CHECK-BE-NEXT: mtvsrwa f0, r3 ; CHECK-BE-NEXT: mtvsrwa f0, r3
; CHECK-BE-NEXT: mtvsrwa f1, r4 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvsxdsp f0, f0
; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: extsb r3, r3
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtvsrwa f0, r3
; CHECK-BE-NEXT: xscvsxdsp f0, f0 ; CHECK-BE-NEXT: xscvsxdsp f0, f0
; CHECK-BE-NEXT: xscvsxdsp f1, f1
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: xscvdpspn v3, f1 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = sitofp <2 x i8> %0 to <2 x float> %1 = sitofp <2 x i8> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
Show All 11 Lines
; CHECK-P8-NEXT: vadduwm v3, v3, v3 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
; CHECK-P8-NEXT: vslw v2, v2, v3 ; CHECK-P8-NEXT: vslw v2, v2, v3
; CHECK-P8-NEXT: vsraw v2, v2, v3 ; CHECK-P8-NEXT: vsraw v2, v2, v3
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v2, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp v2, v2 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = sitofp <4 x i8> %0 to <4 x float> %1 = sitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 21 Lines
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r6, r6, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v2, v4, v4, v2 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: vperm v3, v4, v4, v3 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r6, r6, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r6
; CHECK-BE-NEXT: vperm v2, v5, v4, v2
; CHECK-BE-NEXT: vperm v3, v4, v4, v3
; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v2 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = sitofp <8 x i8> %0 to <8 x float> %1 = sitofp <8 x i8> %0 to <8 x float>
store <8 x float> %1, <8 x float>* %agg.result, align 32 store <8 x float> %1, <8 x float>* %agg.result, align 32
ret void ret void
} }
Show All 38 Lines
; CHECK-P8-NEXT: stvx v5, r3, r4 ; CHECK-P8-NEXT: stvx v5, r3, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r7, r7, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v4, v2, v2, v4
; CHECK-P9-NEXT: vperm v5, v2, v2, v5
; CHECK-P9-NEXT: vperm v2, v2, v2, v0
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: vextsb2w v4, v4
; CHECK-P9-NEXT: vextsb2w v5, v5
; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvsxwsp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: xxlxor v1, v1, v1
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI7_2@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: lxvx v5, 0, r6
; CHECK-BE-NEXT: lxvx v0, 0, r7
; CHECK-BE-NEXT: vperm v3, v1, v2, v3
; CHECK-BE-NEXT: vperm v4, v1, v2, v4
; CHECK-BE-NEXT: vperm v5, v2, v2, v5
; CHECK-BE-NEXT: vperm v2, v2, v2, v0
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: vextsb2w v4, v4
; CHECK-BE-NEXT: vextsb2w v5, v5
; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvsxwsp vs2, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x float> %0 = sitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

Show All 18 Lines
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: lxvx v2, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v3, v2
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: lxvx v2, 0, r4
; CHECK-BE-NEXT: vperm v2, v3, v4, v2
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = uitofp <2 x i8> %0 to <2 x double> %1 = uitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 17 Lines
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r4
; CHECK-P9-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: mtvsrws v4, r4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r6, r6, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: vperm v2, v5, v4, v2 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: vperm v3, v5, v4, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvuxddp vs0, v2 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: mtvsrws v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r6, r6, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: vperm v2, v4, v5, v2 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: vperm v3, v5, v4, v3 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs0, v2 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = uitofp <4 x i8> %0 to <4 x double> %1 = uitofp <4 x i8> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
Show All 33 Lines
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: xxlxor v1, v1, v1 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: addi r6, r6, .LCPI2_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r7, r7, .LCPI2_2@toc@l ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: addi r8, r8, .LCPI2_3@toc@l ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: lxvx v4, 0, r7 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v5, 0, r8 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v1, v0, v2 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: vperm v3, v1, v0, v3 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v4, v1, v0, v4 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: vperm v5, v1, v0, v5 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs0, v2
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: xvcvuxddp vs2, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvuxddp vs3, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: addis r8, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: mtvsrd v0, r4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: xxlxor v1, v1, v1 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: addi r6, r6, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: addi r7, r7, .LCPI2_2@toc@l ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: addi r8, r8, .LCPI2_3@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r7 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: lxvx v5, 0, r8 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vperm v2, v0, v1, v2
; CHECK-BE-NEXT: vperm v3, v1, v0, v3
; CHECK-BE-NEXT: vperm v4, v1, v0, v4
; CHECK-BE-NEXT: vperm v5, v1, v0, v5
; CHECK-BE-NEXT: xvcvuxddp vs0, v2
; CHECK-BE-NEXT: xvcvuxddp vs1, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: xvcvuxddp vs2, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs3, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = uitofp <8 x i8> %0 to <8 x double> %1 = uitofp <8 x i8> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %agg.result, align 64 store <8 x double> %1, <8 x double>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI3_4@toc@ha
; CHECK-P9-NEXT: addis r9, r2, .LCPI3_5@toc@ha
; CHECK-P9-NEXT: addis r10, r2, .LCPI3_6@toc@ha
; CHECK-P9-NEXT: addis r11, r2, .LCPI3_7@toc@ha
; CHECK-P9-NEXT: xxlxor v9, v9, v9
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r7, r7, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r8, r8, .LCPI3_4@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: addi r9, r9, .LCPI3_5@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: addi r10, r10, .LCPI3_6@toc@l
; CHECK-P9-NEXT: addi r11, r11, .LCPI3_7@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: lxvx v1, 0, r8
; CHECK-P9-NEXT: lxvx v6, 0, r9
; CHECK-P9-NEXT: lxvx v7, 0, r10
; CHECK-P9-NEXT: lxvx v8, 0, r11
; CHECK-P9-NEXT: vperm v3, v9, v2, v3
; CHECK-P9-NEXT: vperm v4, v9, v2, v4
; CHECK-P9-NEXT: vperm v5, v9, v2, v5
; CHECK-P9-NEXT: vperm v0, v9, v2, v0
; CHECK-P9-NEXT: vperm v1, v9, v2, v1
; CHECK-P9-NEXT: vperm v6, v9, v2, v6
; CHECK-P9-NEXT: vperm v7, v9, v2, v7
; CHECK-P9-NEXT: vperm v2, v9, v2, v8
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: xvcvuxddp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvuxddp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: xvcvuxddp vs3, v0 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: xvcvuxddp vs4, v1 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs5, v6
; CHECK-P9-NEXT: xvcvuxddp vs6, v7
; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: xvcvuxddp vs4, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: xvcvuxddp vs5, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addis r8, r2, .LCPI3_4@toc@ha
; CHECK-BE-NEXT: addis r9, r2, .LCPI3_5@toc@ha
; CHECK-BE-NEXT: addis r10, r2, .LCPI3_6@toc@ha
; CHECK-BE-NEXT: addis r11, r2, .LCPI3_7@toc@ha
; CHECK-BE-NEXT: xxlxor v9, v9, v9
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI3_1@toc@l ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI3_2@toc@l ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r7, r7, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r8, r8, .LCPI3_4@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: addi r9, r9, .LCPI3_5@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: addi r10, r10, .LCPI3_6@toc@l
; CHECK-BE-NEXT: addi r11, r11, .LCPI3_7@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: lxvx v4, 0, r5
; CHECK-BE-NEXT: lxvx v5, 0, r6
; CHECK-BE-NEXT: lxvx v0, 0, r7
; CHECK-BE-NEXT: lxvx v1, 0, r8
; CHECK-BE-NEXT: lxvx v6, 0, r9
; CHECK-BE-NEXT: lxvx v7, 0, r10
; CHECK-BE-NEXT: lxvx v8, 0, r11
; CHECK-BE-NEXT: vperm v3, v2, v9, v3
; CHECK-BE-NEXT: vperm v4, v9, v2, v4
; CHECK-BE-NEXT: vperm v5, v9, v2, v5
; CHECK-BE-NEXT: vperm v0, v9, v2, v0
; CHECK-BE-NEXT: vperm v1, v9, v2, v1
; CHECK-BE-NEXT: vperm v6, v9, v2, v6
; CHECK-BE-NEXT: vperm v7, v9, v2, v7
; CHECK-BE-NEXT: vperm v2, v9, v2, v8
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: xvcvuxddp vs1, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvuxddp vs2, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: xvcvuxddp vs3, v0 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: xvcvuxddp vs4, v1 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: xvcvuxddp vs5, v6
; CHECK-BE-NEXT: xvcvuxddp vs6, v7
; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: xvcvuxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: xvcvuxddp vs5, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <16 x i8> %a to <16 x double> %0 = uitofp <16 x i8> %a to <16 x double>
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
ret void ret void
} }
define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
Show All 11 Lines
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: vsld v2, v2, v3 ; CHECK-P8-NEXT: vsld v2, v2, v3
; CHECK-P8-NEXT: vsrad v2, v2, v3 ; CHECK-P8-NEXT: vsrad v2, v2, v3
; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx v2, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: mtvsrws v3, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = sitofp <2 x i8> %0 to <2 x double> %1 = sitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 25 Lines
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: mtvsrws v2, r4
; CHECK-P9-NEXT: addis r6, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: mtvsrws v4, r4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI5_1@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v2, v4, v4, v2
; CHECK-P9-NEXT: vperm v3, v4, v4, v3
; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: mtvsrws v4, r4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r6, r6, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: lxvx v3, 0, r6
; CHECK-BE-NEXT: vperm v2, v5, v4, v2
; CHECK-BE-NEXT: vperm v3, v4, v4, v3
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v2 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = sitofp <4 x i8> %0 to <4 x double> %1 = sitofp <4 x i8> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r6, r6, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: addi r7, r7, .LCPI6_2@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r8, r8, .LCPI6_3@toc@l ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: lxvx v2, 0, r5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: lxvx v3, 0, r6 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r7 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: lxvx v5, 0, r8 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: vperm v2, v0, v0, v2 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v3, v0, v0, v3 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: vperm v4, v0, v0, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-P9-NEXT: vperm v5, v0, v0, v5 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: vextsb2d v4, v4
; CHECK-P9-NEXT: vextsb2d v5, v5
; CHECK-P9-NEXT: xvcvsxddp vs0, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvsxddp vs3, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r6, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: addis r8, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: mtvsrd v0, r4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: xxlxor v1, v1, v1 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r6, r6, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: addi r7, r7, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: addi r8, r8, .LCPI6_3@toc@l ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: lxvx v3, 0, r6 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: lxvx v4, 0, r7 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: lxvx v5, 0, r8 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vperm v2, v1, v0, v2 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vperm v3, v1, v0, v3
; CHECK-BE-NEXT: vperm v4, v0, v0, v4
; CHECK-BE-NEXT: vperm v5, v0, v0, v5
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: vextsb2d v5, v5
; CHECK-BE-NEXT: xvcvsxddp vs0, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v4 ; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: xvcvsxddp vs3, v5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = sitofp <8 x i8> %0 to <8 x double> %1 = sitofp <8 x i8> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %agg.result, align 64 store <8 x double> %1, <8 x double>* %agg.result, align 64
ret void ret void
} }
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addis r6, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addis r7, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addis r8, r2, .LCPI7_4@toc@ha
; CHECK-P9-NEXT: addis r9, r2, .LCPI7_5@toc@ha
; CHECK-P9-NEXT: addis r10, r2, .LCPI7_6@toc@ha
; CHECK-P9-NEXT: addis r11, r2, .LCPI7_7@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addi r6, r6, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r7, r7, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P9-NEXT: addi r8, r8, .LCPI7_4@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: addi r9, r9, .LCPI7_5@toc@l ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: addi r10, r10, .LCPI7_6@toc@l
; CHECK-P9-NEXT: addi r11, r11, .LCPI7_7@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: lxvx v4, 0, r5
; CHECK-P9-NEXT: lxvx v5, 0, r6
; CHECK-P9-NEXT: lxvx v0, 0, r7
; CHECK-P9-NEXT: lxvx v1, 0, r8
; CHECK-P9-NEXT: lxvx v6, 0, r9
; CHECK-P9-NEXT: lxvx v7, 0, r10
; CHECK-P9-NEXT: lxvx v8, 0, r11
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vperm v4, v2, v2, v4
; CHECK-P9-NEXT: vperm v5, v2, v2, v5
; CHECK-P9-NEXT: vperm v0, v2, v2, v0
; CHECK-P9-NEXT: vperm v1, v2, v2, v1
; CHECK-P9-NEXT: vperm v6, v2, v2, v6
; CHECK-P9-NEXT: vperm v7, v2, v2, v7
; CHECK-P9-NEXT: vperm v2, v2, v2, v8
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: vextsb2d v4, v4
; CHECK-P9-NEXT: vextsb2d v5, v5
; CHECK-P9-NEXT: vextsb2d v0, v0
; CHECK-P9-NEXT: vextsb2d v1, v1
; CHECK-P9-NEXT: vextsb2d v6, v6
; CHECK-P9-NEXT: vextsb2d v7, v7
; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xvcvsxddp vs2, v5 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: xvcvsxddp vs3, v0 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-P9-NEXT: xvcvsxddp vs4, v1 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: xvcvsxddp vs5, v6
; CHECK-P9-NEXT: xvcvsxddp vs6, v7
; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs3, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs4, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs5, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs6, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addis r6, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addis r7, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addis r8, r2, .LCPI7_4@toc@ha
; CHECK-BE-NEXT: addis r9, r2, .LCPI7_5@toc@ha
; CHECK-BE-NEXT: addis r10, r2, .LCPI7_6@toc@ha
; CHECK-BE-NEXT: addis r11, r2, .LCPI7_7@toc@ha
; CHECK-BE-NEXT: xxlxor v9, v9, v9
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: addi r6, r6, .LCPI7_2@toc@l ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r7, r7, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: addi r8, r8, .LCPI7_4@toc@l ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r9, r9, .LCPI7_5@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: addi r10, r10, .LCPI7_6@toc@l ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: addi r11, r11, .LCPI7_7@toc@l ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: lxvx v4, 0, r5 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: lxvx v5, 0, r6 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: lxvx v0, 0, r7 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: lxvx v1, 0, r8 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: lxvx v6, 0, r9
; CHECK-BE-NEXT: lxvx v7, 0, r10
; CHECK-BE-NEXT: lxvx v8, 0, r11
; CHECK-BE-NEXT: vperm v3, v9, v2, v3
; CHECK-BE-NEXT: vperm v4, v9, v2, v4
; CHECK-BE-NEXT: vperm v5, v9, v2, v5
; CHECK-BE-NEXT: vperm v0, v9, v2, v0
; CHECK-BE-NEXT: vperm v1, v2, v2, v1
; CHECK-BE-NEXT: vperm v6, v2, v2, v6
; CHECK-BE-NEXT: vperm v7, v2, v2, v7
; CHECK-BE-NEXT: vperm v2, v2, v2, v8
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: vextsb2d v5, v5
; CHECK-BE-NEXT: vextsb2d v0, v0
; CHECK-BE-NEXT: vextsb2d v1, v1
; CHECK-BE-NEXT: vextsb2d v6, v6
; CHECK-BE-NEXT: vextsb2d v7, v7
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4
; CHECK-BE-NEXT: xvcvsxddp vs2, v5 ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: xvcvsxddp vs3, v0 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: xvcvsxddp vs4, v1 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: xvcvsxddp vs5, v6 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: xvcvsxddp vs6, v7
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: xvcvsxddp vs2, v4
; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: lxvx v4, 0, r4
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs3, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs5, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x double> %0 = sitofp <16 x i8> %a to <16 x double>
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs6, r3, r11 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs7, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: lxv v0, 112(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: lxv v1, 96(r4) ; CHECK-P9-NEXT: xvcvuxddp vs3, v0
; CHECK-P9-NEXT: lxv v6, 80(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v7, 64(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: xvcvuxddp vs0, v5 ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvuxddp vs1, v4 ; CHECK-P9-NEXT: xvcvuxddp vs0, v7
; CHECK-P9-NEXT: xvcvuxddp vs2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v6
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs2, v1
; CHECK-P9-NEXT: xvcvuxddp vs4, v7 ; CHECK-P9-NEXT: xvcvuxddp vs4, v5
; CHECK-P9-NEXT: xvcvuxddp vs5, v6 ; CHECK-P9-NEXT: xvcvuxddp vs5, v4
; CHECK-P9-NEXT: xvcvuxddp vs6, v1 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: xvcvuxddp vs7, v0 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 48(r4) ; CHECK-BE-NEXT: lxv v2, 112(r4)
; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 16(r4) ; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 0(r4) ; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: lxv v0, 112(r4) ; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: lxv v1, 96(r4) ; CHECK-BE-NEXT: xvcvuxddp vs3, v0
; CHECK-BE-NEXT: lxv v6, 80(r4) ; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v7, 64(r4) ; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: xvcvuxddp vs0, v5 ; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvuxddp vs1, v4 ; CHECK-BE-NEXT: xvcvuxddp vs0, v7
; CHECK-BE-NEXT: xvcvuxddp vs2, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v6
; CHECK-BE-NEXT: xvcvuxddp vs3, v2 ; CHECK-BE-NEXT: xvcvuxddp vs2, v1
; CHECK-BE-NEXT: xvcvuxddp vs4, v7 ; CHECK-BE-NEXT: xvcvuxddp vs4, v5
; CHECK-BE-NEXT: xvcvuxddp vs5, v6 ; CHECK-BE-NEXT: xvcvuxddp vs5, v4
; CHECK-BE-NEXT: xvcvuxddp vs6, v1 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: xvcvuxddp vs7, v0 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i64>, <16 x i64>* %0, align 128 %a = load <16 x i64>, <16 x i64>* %0, align 128
%1 = uitofp <16 x i64> %a to <16 x double> %1 = uitofp <16 x i64> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs6, r3, r11 ; CHECK-P8-NEXT: stxvd2x vs6, r3, r11
; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
; CHECK-P8-NEXT: stxvd2x vs7, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs7, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 48(r4) ; CHECK-P9-NEXT: lxv v2, 112(r4)
; CHECK-P9-NEXT: lxv v3, 32(r4) ; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 0(r4) ; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: lxv v0, 112(r4) ; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: lxv v1, 96(r4) ; CHECK-P9-NEXT: xvcvsxddp vs3, v0
; CHECK-P9-NEXT: lxv v6, 80(r4) ; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v7, 64(r4) ; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: xvcvsxddp vs0, v5 ; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: xvcvsxddp vs0, v7
; CHECK-P9-NEXT: xvcvsxddp vs2, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v6
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs2, v1
; CHECK-P9-NEXT: xvcvsxddp vs4, v7 ; CHECK-P9-NEXT: xvcvsxddp vs4, v5
; CHECK-P9-NEXT: xvcvsxddp vs5, v6 ; CHECK-P9-NEXT: xvcvsxddp vs5, v4
; CHECK-P9-NEXT: xvcvsxddp vs6, v1 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
; CHECK-P9-NEXT: xvcvsxddp vs7, v0 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 48(r4) ; CHECK-BE-NEXT: lxv v2, 112(r4)
; CHECK-BE-NEXT: lxv v3, 32(r4) ; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 16(r4) ; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 0(r4) ; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: lxv v0, 112(r4) ; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: lxv v1, 96(r4) ; CHECK-BE-NEXT: xvcvsxddp vs3, v0
; CHECK-BE-NEXT: lxv v6, 80(r4) ; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v7, 64(r4) ; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: xvcvsxddp vs0, v5 ; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvsxddp vs1, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v7
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v6
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs2, v1
; CHECK-BE-NEXT: xvcvsxddp vs4, v7 ; CHECK-BE-NEXT: xvcvsxddp vs4, v5
; CHECK-BE-NEXT: xvcvsxddp vs5, v6 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: xvcvsxddp vs6, v1 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: xvcvsxddp vs7, v0 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i64>, <16 x i64>* %0, align 128 %a = load <16 x i64>, <16 x i64>* %0, align 128
%1 = sitofp <16 x i64> %a to <16 x double> %1 = sitofp <16 x i64> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll

Show All 31 Lines
define void @_Z4testv() { define void @_Z4testv() {
entry: entry:
; CHECK-LABEL: @_Z4testv ; CHECK-LABEL: @_Z4testv
%0 = load <16 x i8>, <16 x i8>* @uca, align 16 %0 = load <16 x i8>, <16 x i8>* @uca, align 16
%1 = load <16 x i8>, <16 x i8>* @ucb, align 16 %1 = load <16 x i8>, <16 x i8>* @ucb, align 16
%add.i = add <16 x i8> %1, %0 %add.i = add <16 x i8> %1, %0
tail call void (...) @sink(<16 x i8> %add.i) tail call void (...) @sink(<16 x i8> %add.i)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vaddubm 2, 3, 2 ; CHECK: vaddubm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%2 = load <16 x i8>, <16 x i8>* @sca, align 16 %2 = load <16 x i8>, <16 x i8>* @sca, align 16
%3 = load <16 x i8>, <16 x i8>* @scb, align 16 %3 = load <16 x i8>, <16 x i8>* @scb, align 16
%add.i22 = add <16 x i8> %3, %2 %add.i22 = add <16 x i8> %3, %2
tail call void (...) @sink(<16 x i8> %add.i22) tail call void (...) @sink(<16 x i8> %add.i22)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vaddubm 2, 3, 2 ; CHECK: vaddubm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%4 = load <8 x i16>, <8 x i16>* @usa, align 16 %4 = load <8 x i16>, <8 x i16>* @usa, align 16
%5 = load <8 x i16>, <8 x i16>* @usb, align 16 %5 = load <8 x i16>, <8 x i16>* @usb, align 16
%add.i21 = add <8 x i16> %5, %4 %add.i21 = add <8 x i16> %5, %4
tail call void (...) @sink(<8 x i16> %add.i21) tail call void (...) @sink(<8 x i16> %add.i21)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduhm 2, 3, 2 ; CHECK: vadduhm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%6 = load <8 x i16>, <8 x i16>* @ssa, align 16 %6 = load <8 x i16>, <8 x i16>* @ssa, align 16
%7 = load <8 x i16>, <8 x i16>* @ssb, align 16 %7 = load <8 x i16>, <8 x i16>* @ssb, align 16
%add.i20 = add <8 x i16> %7, %6 %add.i20 = add <8 x i16> %7, %6
tail call void (...) @sink(<8 x i16> %add.i20) tail call void (...) @sink(<8 x i16> %add.i20)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduhm 2, 3, 2 ; CHECK: vadduhm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%8 = load <4 x i32>, <4 x i32>* @uia, align 16 %8 = load <4 x i32>, <4 x i32>* @uia, align 16
%9 = load <4 x i32>, <4 x i32>* @uib, align 16 %9 = load <4 x i32>, <4 x i32>* @uib, align 16
%add.i19 = add <4 x i32> %9, %8 %add.i19 = add <4 x i32> %9, %8
tail call void (...) @sink(<4 x i32> %add.i19) tail call void (...) @sink(<4 x i32> %add.i19)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduwm 2, 3, 2 ; CHECK: vadduwm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%10 = load <4 x i32>, <4 x i32>* @sia, align 16 %10 = load <4 x i32>, <4 x i32>* @sia, align 16
%11 = load <4 x i32>, <4 x i32>* @sib, align 16 %11 = load <4 x i32>, <4 x i32>* @sib, align 16
%add.i18 = add <4 x i32> %11, %10 %add.i18 = add <4 x i32> %11, %10
tail call void (...) @sink(<4 x i32> %add.i18) tail call void (...) @sink(<4 x i32> %add.i18)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduwm 2, 3, 2 ; CHECK: vadduwm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%12 = load <2 x i64>, <2 x i64>* @ulla, align 16 %12 = load <2 x i64>, <2 x i64>* @ulla, align 16
%13 = load <2 x i64>, <2 x i64>* @ullb, align 16 %13 = load <2 x i64>, <2 x i64>* @ullb, align 16
%add.i17 = add <2 x i64> %13, %12 %add.i17 = add <2 x i64> %13, %12
tail call void (...) @sink(<2 x i64> %add.i17) tail call void (...) @sink(<2 x i64> %add.i17)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vaddudm 2, 3, 2 ; CHECK: vaddudm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%14 = load <2 x i64>, <2 x i64>* @slla, align 16 %14 = load <2 x i64>, <2 x i64>* @slla, align 16
%15 = load <2 x i64>, <2 x i64>* @sllb, align 16 %15 = load <2 x i64>, <2 x i64>* @sllb, align 16
%add.i16 = add <2 x i64> %15, %14 %add.i16 = add <2 x i64> %15, %14
tail call void (...) @sink(<2 x i64> %add.i16) tail call void (...) @sink(<2 x i64> %add.i16)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vaddudm 2, 3, 2 ; CHECK: vaddudm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%16 = load <1 x i128>, <1 x i128>* @uxa, align 16 %16 = load <1 x i128>, <1 x i128>* @uxa, align 16
%17 = load <1 x i128>, <1 x i128>* @uxb, align 16 %17 = load <1 x i128>, <1 x i128>* @uxb, align 16
%add.i15 = add <1 x i128> %17, %16 %add.i15 = add <1 x i128> %17, %16
tail call void (...) @sink(<1 x i128> %add.i15) tail call void (...) @sink(<1 x i128> %add.i15)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduqm 2, 3, 2 ; CHECK: vadduqm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%18 = load <1 x i128>, <1 x i128>* @sxa, align 16 %18 = load <1 x i128>, <1 x i128>* @sxa, align 16
%19 = load <1 x i128>, <1 x i128>* @sxb, align 16 %19 = load <1 x i128>, <1 x i128>* @sxb, align 16
%add.i14 = add <1 x i128> %19, %18 %add.i14 = add <1 x i128> %19, %18
tail call void (...) @sink(<1 x i128> %add.i14) tail call void (...) @sink(<1 x i128> %add.i14)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxvx 34, 0, 3
; CHECK: lxvx 35, 0, 4 ; CHECK: lxvx 35, 0, 3
; CHECK: vadduqm 2, 3, 2 ; CHECK: vadduqm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%20 = load <4 x float>, <4 x float>* @vfa, align 16 %20 = load <4 x float>, <4 x float>* @vfa, align 16
%21 = load <4 x float>, <4 x float>* @vfb, align 16 %21 = load <4 x float>, <4 x float>* @vfb, align 16
%add.i13 = fadd <4 x float> %20, %21 %add.i13 = fadd <4 x float> %20, %21
tail call void (...) @sink(<4 x float> %add.i13) tail call void (...) @sink(<4 x float> %add.i13)
; CHECK: lxvx 0, 0, 3 ; CHECK: lxvx 0, 0, 3
; CHECK: lxvx 1, 0, 4 ; CHECK: lxvx 1, 0, 3
; CHECK: xvaddsp 34, 0, 1 ; CHECK: xvaddsp 34, 0, 1
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%22 = load <2 x double>, <2 x double>* @vda, align 16 %22 = load <2 x double>, <2 x double>* @vda, align 16
%23 = load <2 x double>, <2 x double>* @vdb, align 16 %23 = load <2 x double>, <2 x double>* @vdb, align 16
%add.i12 = fadd <2 x double> %22, %23 %add.i12 = fadd <2 x double> %22, %23
tail call void (...) @sink(<2 x double> %add.i12) tail call void (...) @sink(<2 x double> %add.i12)
; CHECK: lxvx 0, 0, 3 ; CHECK: lxvx 0, 0, 3
; CHECK: lxvx 1, 0, 4 ; CHECK: lxvx 1, 0, 3
; CHECK: xvadddp 0, 0, 1 ; CHECK: xvadddp 0, 0, 1
; CHECK: stxv 0, ; CHECK: stxv 0,
; CHECK: bl sink ; CHECK: bl sink
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) { define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) {
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llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll

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; CHECK: @foo3 ; CHECK: @foo3
; CHECK: stxsdx f1, r1, r3 ; CHECK: stxsdx f1, r1, r3
; CHECK: lxsdx f0, r1, r3 ; CHECK: lxsdx f0, r1, r3
; CHECK: xsadddp f1, f0, f0 ; CHECK: xsadddp f1, f0, f0
; CHECK: blr ; CHECK: blr
; CHECK-P9-REG-LABEL: foo3 ; CHECK-P9-REG-LABEL: foo3
; CHECK-P9-REG: stdu r1, -400(r1) ; CHECK-P9-REG: stdu r1, -400(r1)
; CHECK-P9-REG: lfd f30, 384(r1) ; CHECK-P9-REG-DAG: lfd f30, 384(r1)
; CHECK-P9-REG: xsadddp f1, f0, f0 ; CHECK-P9-REG-DAG: xsadddp f1, f0, f0
; CHECK-P9-FISL-LABEL: foo3 ; CHECK-P9-FISL-LABEL: foo3
; CHECK-P9-FISL: stdu r1, -400(r1) ; CHECK-P9-FISL: stdu r1, -400(r1)
; CHECK-P9-FISL: lfd f0, 56(r1) ; CHECK-P9-FISL: lfd f0, 56(r1)
; CHECK-P9-FISL: xsadddp f1, f0, f0 ; CHECK-P9-FISL: xsadddp f1, f0, f0
return: ; preds = %entry return: ; preds = %entry
%b = fadd double %a, %a %b = fadd double %a, %a
ret double %b ret double %b
} }

llvm/trunk/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

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; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4 ; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4
; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0 ; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0
; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0 ; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
; CHECK-P9-VECTOR-NEXT: xxpermdi v2, vs0, vs1, 1 ; CHECK-P9-VECTOR-NEXT: xxpermdi v2, vs0, vs1, 1
; CHECK-P9-VECTOR-NEXT: blr ; CHECK-P9-VECTOR-NEXT: blr
; ;
; CHECK-P9-LABEL: testi0: ; CHECK-P9-LABEL: testi0:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lfd f0, 0(r4) ; CHECK-P9-NEXT: lfd [[REG:f[0-9]+]], 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv [[REG1:vs[0-9]+]], 0(r3)
; CHECK-P9-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-P9-NEXT: xxpermdi [[REG2:vs[0-9]+]], [[REG]], [[REG]], 2
; CHECK-P9-NEXT: xxpermdi v2, vs1, vs0, 1 ; CHECK-P9-NEXT: xxpermdi v2, [[REG1]], [[REG2]], 1
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%s = load double, double* %p2 %s = load double, double* %p2
%r = insertelement <2 x double> %v, double %s, i32 0 %r = insertelement <2 x double> %v, double %s, i32 0
ret <2 x double> %r ret <2 x double> %r
} }
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; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4 ; CHECK-P9-VECTOR-NEXT: lfdx f1, 0, r4
; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0 ; CHECK-P9-VECTOR-NEXT: xxspltd vs1, vs1, 0
; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0 ; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
; CHECK-P9-VECTOR-NEXT: xxmrgld v2, vs1, vs0 ; CHECK-P9-VECTOR-NEXT: xxmrgld v2, vs1, vs0
; CHECK-P9-VECTOR-NEXT: blr ; CHECK-P9-VECTOR-NEXT: blr
; ;
; CHECK-P9-LABEL: testi1: ; CHECK-P9-LABEL: testi1:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: lfd f0, 0(r4) ; CHECK-P9-NEXT: lfd [[REG:f[0-9]+]], 0(r4)
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv [[REG1:vs[0-9]+]], 0(r3)
; CHECK-P9-NEXT: xxpermdi vs0, f0, f0, 2 ; CHECK-P9-NEXT: xxpermdi [[REG2:vs[0-9]+]], [[REG]], [[REG]], 2
; CHECK-P9-NEXT: xxmrgld v2, vs0, vs1 ; CHECK-P9-NEXT: xxmrgld v2, [[REG2]], [[REG1]]
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%s = load double, double* %p2 %s = load double, double* %p2
%r = insertelement <2 x double> %v, double %s, i32 1 %r = insertelement <2 x double> %v, double %s, i32 1
ret <2 x double> %r ret <2 x double> %r
} }
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