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[Power9] Enable the Out-of-Order scheduling model for P9 hw
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Authored by steven.zhang on Dec 17 2018, 11:21 PM.

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Summary

When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact.

This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

  • x264_r: +6.95%
  • cactuBSSN_r: +6.94%
  • lbm_r: +4.11%
  • xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. The root cause of the deg of xz_r has been addressed and it is another issue that exposed by this change.

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rL LLVM

Event Timeline

steven.zhang created this revision.Dec 17 2018, 11:21 PM
nemanjai accepted this revision.Dec 29 2018, 1:35 PM

LGTM. We definitely want to go ahead with this.

This revision is now accepted and ready to land.Dec 29 2018, 1:35 PM
This revision was automatically updated to reflect the committed changes.