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Differential D55362

[MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR
ClosedPublic

Authored by Petar.Avramovic on Dec 6 2018, 3:08 AM.

Details

Reviewers
atanasyan
petarj
dsanders
Commits
rG150fd430f66b: [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR
rL349475: [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR
Summary

Add narrowScalar for G_AND and G_XOR.
Legalize G_AND G_OR and G_XOR for types other then s32 with clampScalar on MIPS32.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Dec 6 2018, 3:08 AM
Herald added subscribers: arichardson, kristof.beyls, rovka, sdardis. · View Herald TranscriptDec 6 2018, 3:08 AM
Petar.Avramovic updated this revision to Diff 178209.Dec 14 2018, 2:47 AM

Rebased.

atanasyan accepted this revision.Dec 17 2018, 1:40 PM

LGTM

This revision is now accepted and ready to land.Dec 17 2018, 1:40 PM
Closed by commit rL349475: [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR (authored by Petar.Avramovic). · Explain WhyDec 18 2018, 3:39 AM
This revision was automatically updated to reflect the committed changes.
Herald added subscribers: llvm-commits, jrtc27. · View Herald TranscriptDec 18 2018, 3:39 AM

Revision Contents

PathSize
lib/
CodeGen/
GlobalISel/
7 lines
Target/
Mips/
6 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
18 lines
irtranslator/
42 lines
legalizer/
378 lines
llvm-ir/
148 lines
regbankselect/
18 lines

Diff 178209

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines case TargetOpcode::G_CONSTANT: {
unsigned DstReg = MI.getOperand(0).getReg(); unsigned DstReg = MI.getOperand(0).getReg();
if(MRI.getType(DstReg).isVector()) if(MRI.getType(DstReg).isVector())
MIRBuilder.buildBuildVector(DstReg, DstRegs); MIRBuilder.buildBuildVector(DstReg, DstRegs);
else else
MIRBuilder.buildMerge(DstReg, DstRegs); MIRBuilder.buildMerge(DstReg, DstRegs);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case TargetOpcode::G_OR: { case TargetOpcode::G_AND:
case TargetOpcode::G_OR:
case TargetOpcode::G_XOR: {
// Legalize bitwise operation: // Legalize bitwise operation:
// A = BinOp<Ty> B, C // A = BinOp<Ty> B, C
// into: // into:
// B1, ..., BN = G_UNMERGE_VALUES B // B1, ..., BN = G_UNMERGE_VALUES B
// C1, ..., CN = G_UNMERGE_VALUES C // C1, ..., CN = G_UNMERGE_VALUES C
// A1 = BinOp<Ty/N> B1, C2 // A1 = BinOp<Ty/N> B1, C2
// ... // ...
// AN = BinOp<Ty/N> BN, CN // AN = BinOp<Ty/N> BN, CN
Show All 22 Lines for (int i = 0; i < NumParts; ++i) {
SrcsReg2.push_back(SrcReg2); SrcsReg2.push_back(SrcReg2);
} }
// Explode the big arguments into smaller chunks. // Explode the big arguments into smaller chunks.
MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg()); MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg()); MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
// Do the operation on each small part. // Do the operation on each small part.
for (int i = 0; i < NumParts; ++i) for (int i = 0; i < NumParts; ++i)
MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]); MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]},
{SrcsReg1[i], SrcsReg2[i]});
// Gather the destination registers into the final destination. // Gather the destination registers into the final destination.
unsigned DstReg = MI.getOperand(0).getReg(); unsigned DstReg = MI.getOperand(0).getReg();
if(MRI.getType(DstReg).isVector()) if(MRI.getType(DstReg).isVector())
MIRBuilder.buildBuildVector(DstReg, DstRegs); MIRBuilder.buildBuildVector(DstReg, DstRegs);
else else
MIRBuilder.buildMerge(DstReg, DstRegs); MIRBuilder.buildMerge(DstReg, DstRegs);
MI.eraseFromParent(); MI.eraseFromParent();
▲ Show 20 Lines • Show All 646 Lines • Show Last 20 Lines

lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 26 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_ADD) getActionDefinitionsBuilder(G_ADD)
.legalFor({s32}) .legalFor({s32})
.minScalar(0, s32) .minScalar(0, s32)
.customFor({s64}); .customFor({s64});
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0}); .legalForCartesianProduct({p0, s32}, {p0});
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({s32})
.clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
.legalFor({s32}); .legalFor({s32});
getActionDefinitionsBuilder(G_ICMP) getActionDefinitionsBuilder(G_ICMP)
.legalFor({{s32, s32}}) .legalFor({{s32, s32}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({s32}) .legalFor({s32})
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @and(i32, i32) {entry: ret void} define void @and_i32() {entry: ret void}
define void @or(i32, i32) {entry: ret void} define void @or_i32() {entry: ret void}
define void @xor(i32, i32) {entry: ret void} define void @xor_i32() {entry: ret void}
define void @shl(i32) {entry: ret void} define void @shl(i32) {entry: ret void}
define void @ashr(i32) {entry: ret void} define void @ashr(i32) {entry: ret void}
define void @lshr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void}
define void @shlv(i32, i32) {entry: ret void} define void @shlv(i32, i32) {entry: ret void}
define void @ashrv(i32, i32) {entry: ret void} define void @ashrv(i32, i32) {entry: ret void}
define void @lshrv(i32, i32) {entry: ret void} define void @lshrv(i32, i32) {entry: ret void}
... ...
--- ---
name: and name: and_i32
alignment: 2 alignment: 2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: and ; MIPS32-LABEL: name: and_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]] ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[AND]] ; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0 %0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1 %1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_AND %1, %0 %2:gprb(s32) = G_AND %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: or name: or_i32
alignment: 2 alignment: 2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: or ; MIPS32-LABEL: name: or_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]] ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[OR]] ; MIPS32: $v0 = COPY [[OR]]
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0 %0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1 %1:gprb(s32) = COPY $a1
%2:gprb(s32) = G_OR %1, %0 %2:gprb(s32) = G_OR %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: xor name: xor_i32
alignment: 2 alignment: 2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: xor ; MIPS32-LABEL: name: xor_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]] ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[XOR]] ; MIPS32: $v0 = COPY [[XOR]]
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0 %0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1 %1:gprb(s32) = COPY $a1
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
define i32 @and(i32 %a, i32 %b) {
; MIPS32-LABEL: name: and
; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
entry:
%and = and i32 %b, %a
ret i32 %and
}
define i32 @or(i32 %a, i32 %b) {
; MIPS32-LABEL: name: or
; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0
entry:
%or = or i32 %b, %a
ret i32 %or
}
define i32 @xor(i32 %a, i32 %b) {
; MIPS32-LABEL: name: xor
; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0
entry:
%xor = xor i32 %b, %a
ret i32 %xor
}
define i32 @shl(i32 %a) { define i32 @shl(i32 %a) {
; MIPS32-LABEL: name: shl ; MIPS32-LABEL: name: shl
; MIPS32: bb.1.entry: ; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
; MIPS32: $v0 = COPY [[SHL]](s32) ; MIPS32: $v0 = COPY [[SHL]](s32)
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @and(i32, i32) {entry: ret void} define void @and_i1() {entry: ret void}
define void @or(i32, i32) {entry: ret void} define void @and_i8() {entry: ret void}
define void @xor(i32, i32) {entry: ret void} define void @and_i16() {entry: ret void}
define void @and_i32() {entry: ret void}
define void @and_i64() {entry: ret void}
define void @or_i1() {entry: ret void}
define void @or_i8() {entry: ret void}
define void @or_i16() {entry: ret void}
define void @or_i32() {entry: ret void}
define void @or_i64() {entry: ret void}
define void @xor_i1() {entry: ret void}
define void @xor_i8() {entry: ret void}
define void @xor_i16() {entry: ret void}
define void @xor_i32() {entry: ret void}
define void @xor_i64() {entry: ret void}
define void @shl(i32) {entry: ret void} define void @shl(i32) {entry: ret void}
define void @ashr(i32) {entry: ret void} define void @ashr(i32) {entry: ret void}
define void @lshr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void}
define void @shlv(i32, i32) {entry: ret void} define void @shlv(i32, i32) {entry: ret void}
define void @ashrv(i32, i32) {entry: ret void} define void @ashrv(i32, i32) {entry: ret void}
define void @lshrv(i32, i32) {entry: ret void} define void @lshrv(i32, i32) {entry: ret void}
... ...
--- ---
name: and name: and_i1
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: and ; MIPS32-LABEL: name: and_i1
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: and_i8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: and_i8
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: and_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: and_i16
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_AND %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: and_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: and_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_AND %1, %0 %2:_(s32) = G_AND %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: or name: and_i64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: and_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: $v1 = COPY [[AND1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s32) = COPY $a2
%5:_(s32) = COPY $a3
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_AND %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$v0 = COPY %7(s32)
$v1 = COPY %8(s32)
RetRA implicit $v0, implicit $v1
...
---
name: or_i1
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: or_i1
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: or_i8
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: or ; MIPS32-LABEL: name: or_i8
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: or_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: or_i16
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_OR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: or_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: or_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]] ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[OR]](s32) ; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_OR %1, %0 %2:_(s32) = G_OR %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: xor name: or_i64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: or_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: $v1 = COPY [[OR1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s32) = COPY $a2
%5:_(s32) = COPY $a3
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_OR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$v0 = COPY %7(s32)
$v1 = COPY %8(s32)
RetRA implicit $v0, implicit $v1
...
---
name: xor_i1
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: xor_i1
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s1) = G_TRUNC %3(s32)
%4:_(s1) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s1)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: xor_i8
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: xor ; MIPS32-LABEL: name: xor_i8
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: xor_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: xor_i16
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_XOR %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: xor_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: xor_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]] ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[XOR]](s32) ; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_XOR %1, %0 %2:_(s32) = G_XOR %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: xor_i64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: xor_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: $v1 = COPY [[XOR1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%4:_(s32) = COPY $a2
%5:_(s32) = COPY $a3
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
%6:_(s64) = G_XOR %1, %0
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$v0 = COPY %7(s32)
$v1 = COPY %8(s32)
RetRA implicit $v0, implicit $v1
...
---
name: shl name: shl
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: shl ; MIPS32-LABEL: name: shl
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @and(i32 %a, i32 %b) { define i1 @and_i1(i1 %a, i1 %b) {
; MIPS32-LABEL: and: ; MIPS32-LABEL: and_i1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: and $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%and = and i1 %b, %a
ret i1 %and
}
define i8 @and_i8(i8 %a, i8 %b) {
; MIPS32-LABEL: and_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: and $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%and = and i8 %b, %a
ret i8 %and
}
define i16 @and_i16(i16 %a, i16 %b) {
; MIPS32-LABEL: and_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: and $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%and = and i16 %b, %a
ret i16 %and
}
define i32 @and_i32(i32 %a, i32 %b) {
; MIPS32-LABEL: and_i32:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: and $2, $5, $4 ; MIPS32-NEXT: and $2, $5, $4
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%and = and i32 %b, %a %and = and i32 %b, %a
ret i32 %and ret i32 %and
} }
define i32 @or(i32 %a, i32 %b) { define i64 @and_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: or: ; MIPS32-LABEL: and_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: and $2, $6, $4
; MIPS32-NEXT: and $3, $7, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%and = and i64 %b, %a
ret i64 %and
}
define i1 @or_i1(i1 %a, i1 %b) {
; MIPS32-LABEL: or_i1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: or $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%or = or i1 %b, %a
ret i1 %or
}
define i8 @or_i8(i8 %a, i8 %b) {
; MIPS32-LABEL: or_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: or $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%or = or i8 %b, %a
ret i8 %or
}
define i16 @or_i16(i16 %a, i16 %b) {
; MIPS32-LABEL: or_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: or $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%or = or i16 %b, %a
ret i16 %or
}
define i32 @or_i32(i32 %a, i32 %b) {
; MIPS32-LABEL: or_i32:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: or $2, $5, $4 ; MIPS32-NEXT: or $2, $5, $4
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%or = or i32 %b, %a %or = or i32 %b, %a
ret i32 %or ret i32 %or
} }
define i32 @xor(i32 %a, i32 %b) { define i64 @or_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: xor: ; MIPS32-LABEL: or_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: or $2, $6, $4
; MIPS32-NEXT: or $3, $7, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%or = or i64 %b, %a
ret i64 %or
}
define i1 @xor_i1(i1 %a, i1 %b) {
; MIPS32-LABEL: xor_i1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%xor = xor i1 %b, %a
ret i1 %xor
}
define i8 @xor_i8(i8 %a, i8 %b) {
; MIPS32-LABEL: xor_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%xor = xor i8 %b, %a
ret i8 %xor
}
define i16 @xor_i16(i16 %a, i16 %b) {
; MIPS32-LABEL: xor_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%xor = xor i16 %b, %a
ret i16 %xor
}
define i32 @xor_i32(i32 %a, i32 %b) {
; MIPS32-LABEL: xor_i32:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $2, $5, $4 ; MIPS32-NEXT: xor $2, $5, $4
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%xor = xor i32 %b, %a %xor = xor i32 %b, %a
ret i32 %xor ret i32 %xor
} }
define i64 @xor_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: xor_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $2, $6, $4
; MIPS32-NEXT: xor $3, $7, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%xor = xor i64 %b, %a
ret i64 %xor
}
define i32 @shl(i32 %a) { define i32 @shl(i32 %a) {
; MIPS32-LABEL: shl: ; MIPS32-LABEL: shl:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $4, 1 ; MIPS32-NEXT: sll $2, $4, 1
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%shl = shl i32 %a, 1 %shl = shl i32 %a, 1
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @and(i32, i32) {entry: ret void} define void @and_i32() {entry: ret void}
define void @or(i32, i32) {entry: ret void} define void @or_i32() {entry: ret void}
define void @xor(i32, i32) {entry: ret void} define void @xor_i32() {entry: ret void}
define void @shl(i32) {entry: ret void} define void @shl(i32) {entry: ret void}
define void @ashr(i32) {entry: ret void} define void @ashr(i32) {entry: ret void}
define void @lshr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void}
define void @shlv(i32, i32) {entry: ret void} define void @shlv(i32, i32) {entry: ret void}
define void @ashrv(i32, i32) {entry: ret void} define void @ashrv(i32, i32) {entry: ret void}
define void @lshrv(i32, i32) {entry: ret void} define void @lshrv(i32, i32) {entry: ret void}
... ...
--- ---
name: and name: and_i32
alignment: 2 alignment: 2
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: and ; MIPS32-LABEL: name: and_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]] ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_AND %1, %0 %2:_(s32) = G_AND %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: or name: or_i32
alignment: 2 alignment: 2
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: or ; MIPS32-LABEL: name: or_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]] ; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[OR]](s32) ; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_OR %1, %0 %2:_(s32) = G_OR %1, %0
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: xor name: xor_i32
alignment: 2 alignment: 2
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: xor ; MIPS32-LABEL: name: xor_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]] ; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]
; MIPS32: $v0 = COPY [[XOR]](s32) ; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
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