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Differential D54906

[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.
ClosedPublic

Authored by craig.topper on Nov 26 2018, 9:58 AM.

Details

Reviewers
RKSimon
spatel
efriedma
jmolloy
t.p.northover
Commits
rGb955bf382cf3: [LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use…
rL347593: [LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use…
Summary

SplitVecOp_TruncateHelper tries to promote the result type while splitting FP_TO_SINT/UINT. It then concatenates the result and introduces a truncate to the original result type. But it does this without inserting the AssertZExt/AssertSExt that the regular result type promotion would insert. Nor does it turn FP_TO_UINT into FP_TO_SINT the way normal result type promotion for these operations does. This is bad on X86 which doesn't support FP_TO_SINT until AVX512.

This patch disables the use of SplitVecOp_TruncateHelper for these operations and just lets normal promotion handle it. I've tweaked a couple things in X86ISelLowering to avoid a few obvious regressions there. I believe all the changes on X86 are improvements. Not sure about the other targets, but it doesn't look obviously worse.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 26 2018, 9:58 AM
Herald added subscribers: jsji, chrib, kristof.beyls and 2 others. · View Herald TranscriptNov 26 2018, 9:58 AM
Harbormaster completed remote builds in B25334: Diff 175285.Nov 26 2018, 9:59 AM
nemanjai added a comment.Nov 26 2018, 10:26 AM

The PPC changes seem to be neutral, so no objection from me. Would you mind adding a comment to https://reviews.llvm.org/D54663 if this gets committed before that one as I'll have to update the patch? I'll do the same if I commit mine first.

craig.topper added reviewers: jmolloy, t.p.northover.Nov 26 2018, 12:15 PM
efriedma added a comment.Nov 26 2018, 12:31 PM

AArch64 changes look fine.

spatel accepted this revision.Nov 26 2018, 12:57 PM

x86 diffs look like wins, so LGTM.

This revision is now accepted and ready to land.Nov 26 2018, 12:57 PM
craig.topper mentioned this in D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion.Nov 26 2018, 1:16 PM
Closed by commit rL347593: [LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use… (authored by ctopper). · Explain WhyNov 26 2018, 1:16 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
SelectionDAG/
9 lines
Target/
X86/
14 lines
test/
CodeGen/
AArch64/
36 lines
14 lines
ARM/
10 lines
PowerPC/
144 lines
96 lines
X86/
2 lines
199 lines
248 lines

Diff 175285

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Show First 20 Lines • Show All 1,688 Lines • ▼ Show 20 Lines case ISD::MSCATTER:
Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo); Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
break; break;
case ISD::MGATHER: case ISD::MGATHER:
Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo); Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
break; break;
case ISD::VSELECT: case ISD::VSELECT:
Res = SplitVecOp_VSELECT(N, OpNo); Res = SplitVecOp_VSELECT(N, OpNo);
break; break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
Res = SplitVecOp_TruncateHelper(N);
else
Res = SplitVecOp_UnaryOp(N);
break;
case ISD::SINT_TO_FP: case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: case ISD::UINT_TO_FP:
if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType())) if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
Res = SplitVecOp_TruncateHelper(N); Res = SplitVecOp_TruncateHelper(N);
else else
Res = SplitVecOp_UnaryOp(N); Res = SplitVecOp_UnaryOp(N);
break; break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::CTTZ: case ISD::CTTZ:
case ISD::CTLZ: case ISD::CTLZ:
case ISD::CTPOP: case ISD::CTPOP:
case ISD::FP_EXTEND: case ISD::FP_EXTEND:
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND: case ISD::ANY_EXTEND:
case ISD::FTRUNC: case ISD::FTRUNC:
▲ Show 20 Lines • Show All 2,780 Lines • Show Last 20 Lines

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 903 Lines • ▼ Show 20 Lines if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
setOperationAction(ISD::FP_TO_SINT, MVT::v2i16, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::v2i16, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v2i8, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::v2i8, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i8, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::v4i8, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v8i8, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::v8i8, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v2i16, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::v2i16, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
// By marking FP_TO_SINT v8i16 as Custom, will trick type legalization into
// promoting v8i8 FP_TO_UINT into FP_TO_SINT. When the v8i16 FP_TO_SINT is
// split again based on the input type, this will cause an AssertSExt i16 to
// be emitted instead of an AssertZExt. This will allow packssdw followed by
// packuswb to be used to truncate to v8i8. This is necessary since packusdw
// isn't available until sse4.1.
setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
// Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion. // Fast v2f32 UINT_TO_FP( v2i32 ) custom conversion.
setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
▲ Show 20 Lines • Show All 25,533 Lines • ▼ Show 20 Lines case ISD::FP_TO_UINT: {
if (VT.isVector() && VT.getScalarSizeInBits() < 32) { if (VT.isVector() && VT.getScalarSizeInBits() < 32) {
if (getTypeAction(*DAG.getContext(), VT) != TypeWidenVector) if (getTypeAction(*DAG.getContext(), VT) != TypeWidenVector)
return; return;
// Try to create a 128 bit vector, but don't exceed a 32 bit element. // Try to create a 128 bit vector, but don't exceed a 32 bit element.
unsigned NewEltWidth = std::min(128 / VT.getVectorNumElements(), 32U); unsigned NewEltWidth = std::min(128 / VT.getVectorNumElements(), 32U);
MVT PromoteVT = MVT::getVectorVT(MVT::getIntegerVT(NewEltWidth), MVT PromoteVT = MVT::getVectorVT(MVT::getIntegerVT(NewEltWidth),
VT.getVectorNumElements()); VT.getVectorNumElements());
unsigned Opc = N->getOpcode(); SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, PromoteVT, Src);
if (PromoteVT == MVT::v2i32 || PromoteVT == MVT::v4i32)
Opc = ISD::FP_TO_SINT;
SDValue Res = DAG.getNode(Opc, dl, PromoteVT, Src);
// Preserve what we know about the size of the original result. Except // Preserve what we know about the size of the original result. Except
// when the result is v2i32 since we can't widen the assert. // when the result is v2i32 since we can't widen the assert.
if (PromoteVT != MVT::v2i32) if (PromoteVT != MVT::v2i32)
Res = DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext Res = DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
: ISD::AssertSext, : ISD::AssertSext,
dl, PromoteVT, Res, dl, PromoteVT, Res,
DAG.getValueType(VT.getVectorElementType())); DAG.getValueType(VT.getVectorElementType()));
▲ Show 20 Lines • Show All 15,685 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-convert-v4f64.ll

; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) {
; CHECK: fptosi_v4f64_to_v4i16 ; CHECK-LABEL: fptosi_v4f64_to_v4i16
; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d ; CHECK-DAG: xtn v[[XTN0:[0-9]+]].2s, v[[LHS]].2d
; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d ; CHECK-DAG: xtn v[[XTN1:[0-9]+]].2s, v[[RHS]].2d
; CHECK: xtn v0.4h, v[[MID]].4s ; CHECK: uzp1 v0.4h, v[[XTN1]].4h, v[[XTN0]].4h
%tmp1 = load <4 x double>, <4 x double>* %ptr %tmp1 = load <4 x double>, <4 x double>* %ptr
%tmp2 = fptosi <4 x double> %tmp1 to <4 x i16> %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16>
ret <4 x i16> %tmp2 ret <4 x i16> %tmp2
} }
define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) {
; CHECK: fptosi_v4f64_to_v4i8 ; CHECK-LABEL: fptosi_v4f64_to_v4i8
; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d ; CHECK-DAG: xtn v[[XTN0:[0-9]+]].2s, v[[CONV0]].2d
; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d ; CHECK-DAG: xtn v[[XTN1:[0-9]+]].2s, v[[CONV1]].2d
; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d ; CHECK-DAG: xtn v[[XTN2:[0-9]+]].2s, v[[CONV2]].2d
; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d ; CHECK-DAG: xtn v[[XTN3:[0-9]+]].2s, v[[CONV3]].2d
; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA2]].4s ; CHECK-DAG: uzp1 v[[UZP0:[0-9]+]].4h, v[[XTN1]].4h, v[[XTN0]].4h
; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA0]].4s ; CHECK-DAG: uzp1 v[[UZP1:[0-9]+]].4h, v[[XTN3]].4h, v[[XTN2]].4h
; CHECK: xtn v0.8b, v[[TMP1]].8h ; CHECK: uzp1 v0.8b, v[[UZP1:[0-9]+]].8b, v[[UZP0:[0-9]+]].8b
%tmp1 = load <8 x double>, <8 x double>* %ptr %tmp1 = load <8 x double>, <8 x double>* %ptr
%tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8>
ret <8 x i8> %tmp2 ret <8 x i8> %tmp2
} }
define <4 x half> @uitofp_v4i64_to_v4f16(<4 x i64>* %ptr) { define <4 x half> @uitofp_v4i64_to_v4f16(<4 x i64>* %ptr) {
; CHECK: uitofp_v4i64_to_v4f16 ; CHECK: uitofp_v4i64_to_v4f16
; CHECK-DAG: ucvtf v[[LHS:[0-9]+]].2d, v0.2d ; CHECK-DAG: ucvtf v[[LHS:[0-9]+]].2d, v0.2d
Show All 12 Lines
; CHECK: xtn2 ; CHECK: xtn2
; CHECK: xtn ; CHECK: xtn
%tmp1 = load <4 x i64>, <4 x i64>* %ptr %tmp1 = load <4 x i64>, <4 x i64>* %ptr
%tmp2 = trunc <4 x i64> %tmp1 to <4 x i16> %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16>
ret <4 x i16> %tmp2 ret <4 x i16> %tmp2
} }
define <4 x i16> @fptoui_v4f64_to_v4i16(<4 x double>* %ptr) { define <4 x i16> @fptoui_v4f64_to_v4i16(<4 x double>* %ptr) {
; CHECK: fptoui_v4f64_to_v4i16 ; CHECK-LABEL: fptoui_v4f64_to_v4i16
; CHECK-DAG: fcvtzu v[[LHS:[0-9]+]].2d, v0.2d ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
; CHECK-DAG: fcvtzu v[[RHS:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d ; CHECK-DAG: xtn v[[XTN0:[0-9]+]].2s, v[[LHS]].2d
; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d ; CHECK-DAG: xtn v[[XTN1:[0-9]+]].2s, v[[RHS]].2d
; CHECK: xtn v0.4h, v[[MID]].4s ; CHECK: uzp1 v0.4h, v[[XTN1]].4h, v[[XTN0]].4h
%tmp1 = load <4 x double>, <4 x double>* %ptr %tmp1 = load <4 x double>, <4 x double>* %ptr
%tmp2 = fptoui <4 x double> %tmp1 to <4 x i16> %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16>
ret <4 x i16> %tmp2 ret <4 x i16> %tmp2
} }

test/CodeGen/AArch64/vcvt-oversize.ll

; RUN: llc -mtriple=aarch64 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
define <8 x i8> @float_to_i8(<8 x float>* %in) { define <8 x i8> @float_to_i8(<8 x float>* %in) {
; CHECK-LABEL: float_to_i8: ; CHECK-LABEL: float_to_i8:
; CHECK: ldp q1, q0, [x0] ; CHECK: ldp q0, q1, [x0]
; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v1.4s, v1.4s ; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s
; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v0.4s, v0.4s ; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s
; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s ; CHECK-DAG: fcvtzs v[[LSB2:[0-9]+]].4s, v[[LSB]].4s
; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s ; CHECK-DAG: fcvtzs v[[MSB2:[0-9]+]].4s, v[[MSB]].4s
; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s ; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s
; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s ; CHECK-DAG: xtn v[[TMP2:[0-9]+]].4h, v[[MSB]].4s
; CHECK-DAG: xtn v0.8b, v[[TMP]].8h ; CHECK-DAG: uzp1 v0.8b, v[[TMP]].8b, v[[TMP2]].8b
%l = load <8 x float>, <8 x float>* %in %l = load <8 x float>, <8 x float>* %in
%scale = fmul <8 x float> %l, <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0> %scale = fmul <8 x float> %l, <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>
%conv = fptoui <8 x float> %scale to <8 x i8> %conv = fptoui <8 x float> %scale to <8 x i8>
ret <8 x i8> %conv ret <8 x i8> %conv
} }

test/CodeGen/ARM/vcvt.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
define <4 x i16> @fix_double_to_i16(<4 x double> %in) { define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
; CHECK-LABEL: fix_double_to_i16: ; CHECK-LABEL: fix_double_to_i16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d18, r0, r1 ; CHECK-NEXT: vmov d18, r0, r1
; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: mov r12, sp
; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
; CHECK-NEXT: vmov d19, r2, r3 ; CHECK-NEXT: vmov d19, r2, r3
; CHECK-NEXT: vadd.f64 d18, d18, d18 ; CHECK-NEXT: vadd.f64 d18, d18, d18
; CHECK-NEXT: vcvt.u32.f64 s0, d18 ; CHECK-NEXT: vcvt.s32.f64 s0, d18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vadd.f64 d20, d16, d16 ; CHECK-NEXT: vadd.f64 d20, d16, d16
; CHECK-NEXT: vadd.f64 d19, d19, d19 ; CHECK-NEXT: vadd.f64 d19, d19, d19
; CHECK-NEXT: vadd.f64 d16, d17, d17 ; CHECK-NEXT: vadd.f64 d16, d17, d17
; CHECK-NEXT: vcvt.u32.f64 s2, d20 ; CHECK-NEXT: vcvt.s32.f64 s2, d20
; CHECK-NEXT: vcvt.u32.f64 s4, d19 ; CHECK-NEXT: vcvt.s32.f64 s4, d19
; CHECK-NEXT: vcvt.u32.f64 s6, d16 ; CHECK-NEXT: vcvt.s32.f64 s6, d16
; CHECK-NEXT: vmov.32 d16[0], r0 ; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.32 d17[0], r0 ; CHECK-NEXT: vmov.32 d17[0], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.32 d16[1], r0 ; CHECK-NEXT: vmov.32 d16[1], r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.32 d17[1], r0 ; CHECK-NEXT: vmov.32 d17[1], r0
; CHECK-NEXT: vmovn.i32 d16, q8 ; CHECK-NEXT: vuzp.16 d16, d17
; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
%scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0> %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0>
%conv = fptoui <4 x double> %scale to <4 x i16> %conv = fptoui <4 x double> %scale to <4 x i16>
ret <4 x i16> %conv ret <4 x i16> %conv
} }
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: li r4, 32 ; CHECK-P8-NEXT: li r4, 32
; CHECK-P8-NEXT: lxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f4, f0 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpuxws f5, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpuxws f6, f2 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpuxws f7, f3 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpuxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpuxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mfvsrwz r3, f4
; CHECK-P8-NEXT: xscvdpuxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpuxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mfvsrwz r4, f5
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtvsrd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f6 ; CHECK-P8-NEXT: mfvsrwz r3, f6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtvsrd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4 ; CHECK-P8-NEXT: xxswapd v2, vs4
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mfvsrwz r4, f7
; CHECK-P8-NEXT: mtvsrd f6, r3 ; CHECK-P8-NEXT: mtvsrd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
Show All 26 Lines
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xxswapd vs4, vs3 ; CHECK-P9-NEXT: xxswapd vs4, vs3
; CHECK-P9-NEXT: xxswapd vs5, vs2 ; CHECK-P9-NEXT: xxswapd vs5, vs2
; CHECK-P9-NEXT: xxswapd vs6, vs1 ; CHECK-P9-NEXT: xxswapd vs6, vs1
; CHECK-P9-NEXT: xxswapd vs7, vs0 ; CHECK-P9-NEXT: xxswapd vs7, vs0
; CHECK-P9-NEXT: xscvdpuxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpuxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpuxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpuxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpuxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpuxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpuxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mfvsrwz r3, f3
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mfvsrwz r5, f2
; CHECK-P9-NEXT: mfvsrwz r7, f1 ; CHECK-P9-NEXT: mfvsrwz r7, f1
; CHECK-P9-NEXT: mfvsrwz r9, f0 ; CHECK-P9-NEXT: mfvsrwz r9, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mtvsrd f2, r5
; CHECK-P9-NEXT: mfvsrwz r4, f4 ; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r6, f5 ; CHECK-P9-NEXT: mfvsrwz r6, f5
Show All 27 Lines
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: xxswapd vs5, vs2 ; CHECK-BE-NEXT: xxswapd vs5, vs2
; CHECK-BE-NEXT: xxswapd vs6, vs1 ; CHECK-BE-NEXT: xxswapd vs6, vs1
; CHECK-BE-NEXT: xxswapd vs7, vs0 ; CHECK-BE-NEXT: xxswapd vs7, vs0
; CHECK-BE-NEXT: xscvdpuxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpuxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpuxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpuxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpuxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpuxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpuxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpuxws f7, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mfvsrwz r3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mfvsrwz r5, f2
; CHECK-BE-NEXT: mfvsrwz r7, f1 ; CHECK-BE-NEXT: mfvsrwz r7, f1
; CHECK-BE-NEXT: mfvsrwz r9, f0 ; CHECK-BE-NEXT: mfvsrwz r9, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: sldi r7, r7, 48 ; CHECK-BE-NEXT: sldi r7, r7, 48
; CHECK-BE-NEXT: sldi r9, r9, 48 ; CHECK-BE-NEXT: sldi r9, r9, 48
Show All 33 Lines
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: li r5, 16 ; CHECK-P8-NEXT: li r5, 16
; CHECK-P8-NEXT: li r6, 32 ; CHECK-P8-NEXT: li r6, 32
; CHECK-P8-NEXT: lxvd2x vs1, r4, r5 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r5
; CHECK-P8-NEXT: lxvd2x vs2, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: lxvd2x vs3, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r6
; CHECK-P8-NEXT: li r6, 64 ; CHECK-P8-NEXT: li r6, 64
; CHECK-P8-NEXT: xscvdpuxws f4, f0 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
; CHECK-P8-NEXT: lxvd2x vs5, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
; CHECK-P8-NEXT: li r6, 80 ; CHECK-P8-NEXT: li r6, 80
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpuxws f6, f1 ; CHECK-P8-NEXT: xscvdpsxws f6, f1
; CHECK-P8-NEXT: lxvd2x vs7, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs7, r4, r6
; CHECK-P8-NEXT: li r6, 96 ; CHECK-P8-NEXT: li r6, 96
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpuxws f8, f2 ; CHECK-P8-NEXT: xscvdpsxws f8, f2
; CHECK-P8-NEXT: lxvd2x vs9, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs9, r4, r6
; CHECK-P8-NEXT: li r6, 112 ; CHECK-P8-NEXT: li r6, 112
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpuxws f10, f3 ; CHECK-P8-NEXT: xscvdpsxws f10, f3
; CHECK-P8-NEXT: lxvd2x vs11, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpuxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpuxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpuxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mfvsrwz r4, f4
; CHECK-P8-NEXT: xscvdpuxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: xscvdpuxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r6, f6 ; CHECK-P8-NEXT: mfvsrwz r6, f6
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtvsrd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f8 ; CHECK-P8-NEXT: mfvsrwz r4, f8
; CHECK-P8-NEXT: xscvdpuxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: xscvdpuxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: mtvsrd f6, r6 ; CHECK-P8-NEXT: mtvsrd f6, r6
; CHECK-P8-NEXT: mfvsrwz r6, f10 ; CHECK-P8-NEXT: mfvsrwz r6, f10
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtvsrd f8, r4
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f12 ; CHECK-P8-NEXT: mfvsrwz r4, f12
; CHECK-P8-NEXT: xscvdpuxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r6 ; CHECK-P8-NEXT: mtvsrd f10, r6
; CHECK-P8-NEXT: mfvsrwz r6, f13 ; CHECK-P8-NEXT: mfvsrwz r6, f13
; CHECK-P8-NEXT: mtvsrd f12, r4 ; CHECK-P8-NEXT: mtvsrd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mfvsrwz r4, v2 ; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xscvdpuxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xscvdpuxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: mtvsrd f13, r6 ; CHECK-P8-NEXT: mtvsrd f13, r6
; CHECK-P8-NEXT: mfvsrwz r6, v3 ; CHECK-P8-NEXT: mfvsrwz r6, v3
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mfvsrwz r4, f0
; CHECK-P8-NEXT: xscvdpuxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpuxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r6 ; CHECK-P8-NEXT: mtvsrd v3, r6
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mfvsrwz r6, f1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mfvsrwz r4, f2
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtvsrd f1, r6
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtvsrd f2, r4
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xxswapd vs8, vs6 ; CHECK-P9-NEXT: xxswapd vs8, vs6
; CHECK-P9-NEXT: xxswapd vs9, vs5 ; CHECK-P9-NEXT: xxswapd vs9, vs5
; CHECK-P9-NEXT: xxswapd vs10, vs4 ; CHECK-P9-NEXT: xxswapd vs10, vs4
; CHECK-P9-NEXT: xxswapd vs11, vs2 ; CHECK-P9-NEXT: xxswapd vs11, vs2
; CHECK-P9-NEXT: xxswapd vs12, vs7 ; CHECK-P9-NEXT: xxswapd vs12, vs7
; CHECK-P9-NEXT: xxswapd vs13, vs3 ; CHECK-P9-NEXT: xxswapd vs13, vs3
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xscvdpuxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpuxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpuxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpuxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpuxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpuxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpuxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpuxws f8, f8 ; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xscvdpuxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpuxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpuxws f11, f11 ; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpuxws f12, f12 ; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpuxws f13, f13 ; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpuxws v2, v2 ; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpuxws v3, v3 ; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r4, f6 ; CHECK-P9-NEXT: mfvsrwz r4, f6
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: mfvsrwz r5, f5
; CHECK-P9-NEXT: mfvsrwz r6, f4 ; CHECK-P9-NEXT: mfvsrwz r6, f4
; CHECK-P9-NEXT: mfvsrwz r7, f2 ; CHECK-P9-NEXT: mfvsrwz r7, f2
; CHECK-P9-NEXT: mfvsrwz r12, f7 ; CHECK-P9-NEXT: mfvsrwz r12, f7
; CHECK-P9-NEXT: mfvsrwz r0, f3 ; CHECK-P9-NEXT: mfvsrwz r0, f3
; CHECK-P9-NEXT: mfvsrwz r30, f1 ; CHECK-P9-NEXT: mfvsrwz r30, f1
; CHECK-P9-NEXT: mfvsrwz r29, f0 ; CHECK-P9-NEXT: mfvsrwz r29, f0
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: xxswapd vs8, vs6 ; CHECK-BE-NEXT: xxswapd vs8, vs6
; CHECK-BE-NEXT: xxswapd vs9, vs5 ; CHECK-BE-NEXT: xxswapd vs9, vs5
; CHECK-BE-NEXT: xxswapd vs10, vs4 ; CHECK-BE-NEXT: xxswapd vs10, vs4
; CHECK-BE-NEXT: xxswapd vs11, vs2 ; CHECK-BE-NEXT: xxswapd vs11, vs2
; CHECK-BE-NEXT: xxswapd vs12, vs7 ; CHECK-BE-NEXT: xxswapd vs12, vs7
; CHECK-BE-NEXT: xxswapd vs13, vs3 ; CHECK-BE-NEXT: xxswapd vs13, vs3
; CHECK-BE-NEXT: xxswapd v2, vs1 ; CHECK-BE-NEXT: xxswapd v2, vs1
; CHECK-BE-NEXT: xxswapd v3, vs0 ; CHECK-BE-NEXT: xxswapd v3, vs0
; CHECK-BE-NEXT: xscvdpuxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpuxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpuxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpuxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpuxws f7, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpuxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpuxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpuxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpuxws f8, f8 ; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpuxws f9, f9 ; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpuxws f10, f10 ; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpuxws f11, f11 ; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpuxws f12, f12 ; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpuxws f13, f13 ; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpuxws v2, v2 ; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpuxws v3, v3 ; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r4, f6 ; CHECK-BE-NEXT: mfvsrwz r4, f6
; CHECK-BE-NEXT: mfvsrwz r5, f5 ; CHECK-BE-NEXT: mfvsrwz r5, f5
; CHECK-BE-NEXT: mfvsrwz r6, f4 ; CHECK-BE-NEXT: mfvsrwz r6, f4
; CHECK-BE-NEXT: mfvsrwz r7, f2 ; CHECK-BE-NEXT: mfvsrwz r7, f2
; CHECK-BE-NEXT: mfvsrwz r12, f7 ; CHECK-BE-NEXT: mfvsrwz r12, f7
; CHECK-BE-NEXT: mfvsrwz r0, f3 ; CHECK-BE-NEXT: mfvsrwz r0, f3
; CHECK-BE-NEXT: mfvsrwz r30, f1 ; CHECK-BE-NEXT: mfvsrwz r30, f1
; CHECK-BE-NEXT: mfvsrwz r29, f0 ; CHECK-BE-NEXT: mfvsrwz r29, f0
▲ Show 20 Lines • Show All 716 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

Show First 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: li r4, 32 ; CHECK-P8-NEXT: li r4, 32
; CHECK-P8-NEXT: lxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs2, r3, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs3, r3, r4
; CHECK-P8-NEXT: li r4, 64 ; CHECK-P8-NEXT: li r4, 64
; CHECK-P8-NEXT: xscvdpuxws f4, f0 ; CHECK-P8-NEXT: xscvdpsxws f4, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: lxvd2x vs5, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs5, r3, r4
; CHECK-P8-NEXT: li r4, 80 ; CHECK-P8-NEXT: li r4, 80
; CHECK-P8-NEXT: xscvdpuxws f6, f1 ; CHECK-P8-NEXT: xscvdpsxws f6, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: lxvd2x vs7, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs7, r3, r4
; CHECK-P8-NEXT: li r4, 96 ; CHECK-P8-NEXT: li r4, 96
; CHECK-P8-NEXT: xscvdpuxws f8, f2 ; CHECK-P8-NEXT: xscvdpsxws f8, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: lxvd2x vs9, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs9, r3, r4
; CHECK-P8-NEXT: li r4, 112 ; CHECK-P8-NEXT: li r4, 112
; CHECK-P8-NEXT: xscvdpuxws f10, f3 ; CHECK-P8-NEXT: xscvdpsxws f10, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: lxvd2x vs11, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs11, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpuxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpuxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mfvsrwz r3, f4
; CHECK-P8-NEXT: xscvdpuxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: mfvsrwz r4, f6 ; CHECK-P8-NEXT: mfvsrwz r4, f6
; CHECK-P8-NEXT: xscvdpuxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtvsrd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f8 ; CHECK-P8-NEXT: mfvsrwz r3, f8
; CHECK-P8-NEXT: xscvdpuxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: mtvsrd f6, r4 ; CHECK-P8-NEXT: mtvsrd f6, r4
; CHECK-P8-NEXT: mfvsrwz r4, f10 ; CHECK-P8-NEXT: mfvsrwz r4, f10
; CHECK-P8-NEXT: xscvdpuxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mtvsrd f8, r3 ; CHECK-P8-NEXT: mtvsrd f8, r3
; CHECK-P8-NEXT: mfvsrwz r3, f12 ; CHECK-P8-NEXT: mfvsrwz r3, f12
; CHECK-P8-NEXT: xscvdpuxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r4 ; CHECK-P8-NEXT: mtvsrd f10, r4
; CHECK-P8-NEXT: mfvsrwz r4, f13 ; CHECK-P8-NEXT: mfvsrwz r4, f13
; CHECK-P8-NEXT: xscvdpuxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mtvsrd f12, r3 ; CHECK-P8-NEXT: mtvsrd f12, r3
; CHECK-P8-NEXT: mfvsrwz r3, v2 ; CHECK-P8-NEXT: mfvsrwz r3, v2
; CHECK-P8-NEXT: xscvdpuxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: mtvsrd f13, r4 ; CHECK-P8-NEXT: mtvsrd f13, r4
; CHECK-P8-NEXT: mfvsrwz r4, v3 ; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mfvsrwz r3, f0
; CHECK-P8-NEXT: xscvdpuxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpuxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mfvsrwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mfvsrwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtvsrd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mfvsrwz r4, f3
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; CHECK-P9-NEXT: xxswapd vs8, vs5 ; CHECK-P9-NEXT: xxswapd vs8, vs5
; CHECK-P9-NEXT: xxswapd vs9, vs4 ; CHECK-P9-NEXT: xxswapd vs9, vs4
; CHECK-P9-NEXT: xxswapd vs10, vs3 ; CHECK-P9-NEXT: xxswapd vs10, vs3
; CHECK-P9-NEXT: xxswapd vs11, vs2 ; CHECK-P9-NEXT: xxswapd vs11, vs2
; CHECK-P9-NEXT: xxswapd vs12, vs7 ; CHECK-P9-NEXT: xxswapd vs12, vs7
; CHECK-P9-NEXT: xxswapd vs13, vs6 ; CHECK-P9-NEXT: xxswapd vs13, vs6
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xscvdpuxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: xscvdpuxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpuxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpuxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpuxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpuxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: xscvdpuxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xscvdpuxws f8, f8 ; CHECK-P9-NEXT: xscvdpsxws f8, f8
; CHECK-P9-NEXT: xscvdpuxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpuxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: xscvdpuxws f11, f11 ; CHECK-P9-NEXT: xscvdpsxws f11, f11
; CHECK-P9-NEXT: xscvdpuxws f12, f12 ; CHECK-P9-NEXT: xscvdpsxws f12, f12
; CHECK-P9-NEXT: xscvdpuxws f13, f13 ; CHECK-P9-NEXT: xscvdpsxws f13, f13
; CHECK-P9-NEXT: xscvdpuxws v2, v2 ; CHECK-P9-NEXT: xscvdpsxws v2, v2
; CHECK-P9-NEXT: xscvdpuxws v3, v3 ; CHECK-P9-NEXT: xscvdpsxws v3, v3
; CHECK-P9-NEXT: mfvsrwz r3, f5 ; CHECK-P9-NEXT: mfvsrwz r3, f5
; CHECK-P9-NEXT: mfvsrwz r4, f4 ; CHECK-P9-NEXT: mfvsrwz r4, f4
; CHECK-P9-NEXT: mfvsrwz r5, f3 ; CHECK-P9-NEXT: mfvsrwz r5, f3
; CHECK-P9-NEXT: mfvsrwz r6, f2 ; CHECK-P9-NEXT: mfvsrwz r6, f2
; CHECK-P9-NEXT: mfvsrwz r11, f7 ; CHECK-P9-NEXT: mfvsrwz r11, f7
; CHECK-P9-NEXT: mfvsrwz r12, f6 ; CHECK-P9-NEXT: mfvsrwz r12, f6
; CHECK-P9-NEXT: mfvsrwz r0, f1 ; CHECK-P9-NEXT: mfvsrwz r0, f1
; CHECK-P9-NEXT: mfvsrwz r30, f0 ; CHECK-P9-NEXT: mfvsrwz r30, f0
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; CHECK-BE-NEXT: xxswapd vs8, vs5 ; CHECK-BE-NEXT: xxswapd vs8, vs5
; CHECK-BE-NEXT: xxswapd vs9, vs4 ; CHECK-BE-NEXT: xxswapd vs9, vs4
; CHECK-BE-NEXT: xxswapd vs10, vs3 ; CHECK-BE-NEXT: xxswapd vs10, vs3
; CHECK-BE-NEXT: xxswapd vs11, vs2 ; CHECK-BE-NEXT: xxswapd vs11, vs2
; CHECK-BE-NEXT: xxswapd vs12, vs7 ; CHECK-BE-NEXT: xxswapd vs12, vs7
; CHECK-BE-NEXT: xxswapd vs13, vs6 ; CHECK-BE-NEXT: xxswapd vs13, vs6
; CHECK-BE-NEXT: xxswapd v2, vs1 ; CHECK-BE-NEXT: xxswapd v2, vs1
; CHECK-BE-NEXT: xxswapd v3, vs0 ; CHECK-BE-NEXT: xxswapd v3, vs0
; CHECK-BE-NEXT: xscvdpuxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: xscvdpuxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvdpuxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpuxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpuxws f7, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: xscvdpuxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: xscvdpuxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvdpuxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: xscvdpuxws f8, f8 ; CHECK-BE-NEXT: xscvdpsxws f8, f8
; CHECK-BE-NEXT: xscvdpuxws f9, f9 ; CHECK-BE-NEXT: xscvdpsxws f9, f9
; CHECK-BE-NEXT: xscvdpuxws f10, f10 ; CHECK-BE-NEXT: xscvdpsxws f10, f10
; CHECK-BE-NEXT: xscvdpuxws f11, f11 ; CHECK-BE-NEXT: xscvdpsxws f11, f11
; CHECK-BE-NEXT: xscvdpuxws f12, f12 ; CHECK-BE-NEXT: xscvdpsxws f12, f12
; CHECK-BE-NEXT: xscvdpuxws f13, f13 ; CHECK-BE-NEXT: xscvdpsxws f13, f13
; CHECK-BE-NEXT: xscvdpuxws v2, v2 ; CHECK-BE-NEXT: xscvdpsxws v2, v2
; CHECK-BE-NEXT: xscvdpuxws v3, v3 ; CHECK-BE-NEXT: xscvdpsxws v3, v3
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: mfvsrwz r3, f5
; CHECK-BE-NEXT: mfvsrwz r4, f4 ; CHECK-BE-NEXT: mfvsrwz r4, f4
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mfvsrwz r5, f3
; CHECK-BE-NEXT: mfvsrwz r6, f2 ; CHECK-BE-NEXT: mfvsrwz r6, f2
; CHECK-BE-NEXT: mfvsrwz r11, f7 ; CHECK-BE-NEXT: mfvsrwz r11, f7
; CHECK-BE-NEXT: mfvsrwz r12, f6 ; CHECK-BE-NEXT: mfvsrwz r12, f6
; CHECK-BE-NEXT: mfvsrwz r0, f1 ; CHECK-BE-NEXT: mfvsrwz r0, f1
; CHECK-BE-NEXT: mfvsrwz r30, f0 ; CHECK-BE-NEXT: mfvsrwz r30, f0
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test/CodeGen/X86/vec_cast2.ll

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; CHECK-WIDE-LABEL: cvt_v8f32_v8u8: ; CHECK-WIDE-LABEL: cvt_v8f32_v8u8:
; CHECK-WIDE: ## %bb.0: ; CHECK-WIDE: ## %bb.0:
; CHECK-WIDE-NEXT: vcvttps2dq %ymm0, %ymm0 ; CHECK-WIDE-NEXT: vcvttps2dq %ymm0, %ymm0
; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm1 ; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm1
; CHECK-WIDE-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ; CHECK-WIDE-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; CHECK-WIDE-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 ; CHECK-WIDE-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; CHECK-WIDE-NEXT: vzeroupper ; CHECK-WIDE-NEXT: vzeroupper
; CHECK-WIDE-NEXT: retl ; CHECK-WIDE-NEXT: retl
%res = fptoui <8 x float> %src to <8 x i8> %res = fptoui <8 x float> %src to <8 x i8>
ret <8 x i8> %res ret <8 x i8> %res
} }
define <8 x i16> @cvt_v8f32_v8u16(<8 x float> %src) { define <8 x i16> @cvt_v8f32_v8u16(<8 x float> %src) {
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test/CodeGen/X86/vec_fp_to_int-widen.ll

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; AVX-NEXT: retq ; AVX-NEXT: retq
%cvt = fptoui <2 x double> %a to <2 x i16> %cvt = fptoui <2 x double> %a to <2 x i16>
ret <2 x i16> %cvt ret <2 x i16> %cvt
} }
define <8 x i16> @fptosi_8f64_to_8i16(<8 x double> %a) { define <8 x i16> @fptosi_8f64_to_8i16(<8 x double> %a) {
; SSE-LABEL: fptosi_8f64_to_8i16: ; SSE-LABEL: fptosi_8f64_to_8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttpd2dq %xmm3, %xmm3
; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE-NEXT: cvttpd2dq %xmm1, %xmm1 ; SSE-NEXT: cvttpd2dq %xmm1, %xmm1
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE-NEXT: packssdw %xmm2, %xmm0
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,1,3,4,5,6,7]
; SSE-NEXT: cvttpd2dq %xmm3, %xmm0
; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,2,0]
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,4,7,5]
; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_8f64_to_8i16: ; VEX-LABEL: fptosi_8f64_to_8i16:
; AVX1: # %bb.0: ; VEX: # %bb.0:
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1 ; VEX-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; VEX-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; VEX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0 ; VEX-NEXT: vzeroupper
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; VEX-NEXT: retq
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: fptosi_8f64_to_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX2-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: fptosi_8f64_to_8i16: ; AVX512F-LABEL: fptosi_8f64_to_8i16:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0 ; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 21 Lines
; AVX512VLDQ-NEXT: retq ; AVX512VLDQ-NEXT: retq
%cvt = fptosi <8 x double> %a to <8 x i16> %cvt = fptosi <8 x double> %a to <8 x i16>
ret <8 x i16> %cvt ret <8 x i16> %cvt
} }
define <8 x i16> @fptoui_8f64_to_8i16(<8 x double> %a) { define <8 x i16> @fptoui_8f64_to_8i16(<8 x double> %a) {
; SSE-LABEL: fptoui_8f64_to_8i16: ; SSE-LABEL: fptoui_8f64_to_8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttsd2si %xmm3, %rax ; SSE-NEXT: cvttpd2dq %xmm3, %xmm3
; SSE-NEXT: movd %eax, %xmm4 ; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1] ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE-NEXT: cvttsd2si %xmm3, %rax ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: movd %eax, %xmm3 ; SSE-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; SSE-NEXT: cvttsd2si %xmm2, %rax ; SSE-NEXT: cvttpd2dq %xmm1, %xmm1
; SSE-NEXT: movd %eax, %xmm3 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: cvttsd2si %xmm2, %rax ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; SSE-NEXT: movd %eax, %xmm2 ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movd %eax, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: cvttsd2si %xmm1, %rax
; SSE-NEXT: movd %eax, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: movd %eax, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttsd2si %xmm0, %rax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_8f64_to_8i16: ; VEX-LABEL: fptoui_8f64_to_8i16:
; AVX1: # %bb.0: ; VEX: # %bb.0:
; AVX1-NEXT: vmovapd {{.*#+}} ymm2 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9] ; VEX-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm2, %ymm1, %ymm3 ; VEX-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; VEX-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackssdw %xmm4, %xmm3, %xmm3 ; VEX-NEXT: vzeroupper
; AVX1-NEXT: vsubpd %ymm2, %ymm1, %ymm4 ; VEX-NEXT: retq
; AVX1-NEXT: vcvttpd2dq %ymm4, %xmm4
; AVX1-NEXT: vmovapd {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
; AVX1-NEXT: vxorpd %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm2, %ymm0, %ymm4
; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm6
; AVX1-NEXT: vpackssdw %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vsubpd %ymm2, %ymm0, %ymm2
; AVX1-NEXT: vcvttpd2dq %ymm2, %xmm2
; AVX1-NEXT: vxorpd %xmm5, %xmm2, %xmm2
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vblendvps %xmm4, %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: fptoui_8f64_to_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
; AVX2-NEXT: vcmpltpd %ymm2, %ymm1, %ymm3
; AVX2-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpackssdw %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vsubpd %ymm2, %ymm1, %ymm4
; AVX2-NEXT: vcvttpd2dq %ymm4, %xmm4
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
; AVX2-NEXT: vxorpd %xmm5, %xmm4, %xmm4
; AVX2-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX2-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm1
; AVX2-NEXT: vcmpltpd %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpackssdw %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vsubpd %ymm2, %ymm0, %ymm2
; AVX2-NEXT: vcvttpd2dq %ymm2, %xmm2
; AVX2-NEXT: vxorpd %xmm5, %xmm2, %xmm2
; AVX2-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: fptoui_8f64_to_8i16: ; AVX512F-LABEL: fptoui_8f64_to_8i16:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0 ; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 22 Lines; AVX512VLDQ-NEXT: retq
%cvt = fptoui <8 x double> %a to <8 x i16> %cvt = fptoui <8 x double> %a to <8 x i16>
ret <8 x i16> %cvt ret <8 x i16> %cvt
} }
define <16 x i8> @fptosi_16f32_to_16i8(<16 x float> %a) { define <16 x i8> @fptosi_16f32_to_16i8(<16 x float> %a) {
; SSE-LABEL: fptosi_16f32_to_16i8: ; SSE-LABEL: fptosi_16f32_to_16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm3, %xmm3 ; SSE-NEXT: cvttps2dq %xmm3, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255]
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: cvttps2dq %xmm2, %xmm2 ; SSE-NEXT: cvttps2dq %xmm2, %xmm2
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: packssdw %xmm3, %xmm2
; SSE-NEXT: packuswb %xmm3, %xmm2
; SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: pand %xmm4, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm1, %xmm0 ; SSE-NEXT: packsswb %xmm2, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_16f32_to_16i8: ; AVX1-LABEL: fptosi_16f32_to_16i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: fptosi_16f32_to_16i8: ; AVX2-LABEL: fptosi_16f32_to_16i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: fptosi_16f32_to_16i8: ; AVX512-LABEL: fptosi_16f32_to_16i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0 ; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%cvt = fptosi <16 x float> %a to <16 x i8> %cvt = fptosi <16 x float> %a to <16 x i8>
ret <16 x i8> %cvt ret <16 x i8> %cvt
} }
define <16 x i8> @fptoui_16f32_to_16i8(<16 x float> %a) { define <16 x i8> @fptoui_16f32_to_16i8(<16 x float> %a) {
; SSE-LABEL: fptoui_16f32_to_16i8: ; SSE-LABEL: fptoui_16f32_to_16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm3, %xmm3 ; SSE-NEXT: cvttps2dq %xmm3, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255]
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: cvttps2dq %xmm2, %xmm2 ; SSE-NEXT: cvttps2dq %xmm2, %xmm2
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: packssdw %xmm3, %xmm2
; SSE-NEXT: packuswb %xmm3, %xmm2
; SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: pand %xmm4, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0 ; SSE-NEXT: packuswb %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_16f32_to_16i8: ; AVX1-LABEL: fptoui_16f32_to_16i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpackusdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: fptoui_16f32_to_16i8: ; AVX2-LABEL: fptoui_16f32_to_16i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackusdw %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackusdw %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: fptoui_16f32_to_16i8: ; AVX512-LABEL: fptoui_16f32_to_16i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0 ; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%cvt = fptoui <16 x float> %a to <16 x i8> %cvt = fptoui <16 x float> %a to <16 x i8>
ret <16 x i8> %cvt ret <16 x i8> %cvt
} }

test/CodeGen/X86/vec_fp_to_int.ll

Show First 20 Lines • Show All 2,720 Lines • ▼ Show 20 Lines
; AVX512VLDQ-NEXT: retq ; AVX512VLDQ-NEXT: retq
%cvt = fptoui <2 x double> %a to <2 x i16> %cvt = fptoui <2 x double> %a to <2 x i16>
ret <2 x i16> %cvt ret <2 x i16> %cvt
} }
define <8 x i16> @fptosi_8f64_to_8i16(<8 x double> %a) { define <8 x i16> @fptosi_8f64_to_8i16(<8 x double> %a) {
; SSE-LABEL: fptosi_8f64_to_8i16: ; SSE-LABEL: fptosi_8f64_to_8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttpd2dq %xmm3, %xmm3
; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE-NEXT: cvttpd2dq %xmm1, %xmm1 ; SSE-NEXT: cvttpd2dq %xmm1, %xmm1
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE-NEXT: packssdw %xmm2, %xmm0
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,1,3,4,5,6,7]
; SSE-NEXT: cvttpd2dq %xmm3, %xmm0
; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,2,0]
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,4,7,5]
; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_8f64_to_8i16: ; VEX-LABEL: fptosi_8f64_to_8i16:
; AVX1: # %bb.0: ; VEX: # %bb.0:
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1 ; VEX-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; VEX-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; VEX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0 ; VEX-NEXT: vzeroupper
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; VEX-NEXT: retq
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: fptosi_8f64_to_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX2-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: fptosi_8f64_to_8i16: ; AVX512F-LABEL: fptosi_8f64_to_8i16:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0 ; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 21 Lines
; AVX512VLDQ-NEXT: retq ; AVX512VLDQ-NEXT: retq
%cvt = fptosi <8 x double> %a to <8 x i16> %cvt = fptosi <8 x double> %a to <8 x i16>
ret <8 x i16> %cvt ret <8 x i16> %cvt
} }
define <8 x i16> @fptoui_8f64_to_8i16(<8 x double> %a) { define <8 x i16> @fptoui_8f64_to_8i16(<8 x double> %a) {
; SSE-LABEL: fptoui_8f64_to_8i16: ; SSE-LABEL: fptoui_8f64_to_8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm4 = mem[0],zero ; SSE-NEXT: cvttpd2dq %xmm3, %xmm3
; SSE-NEXT: movapd %xmm1, %xmm5 ; SSE-NEXT: cvttpd2dq %xmm2, %xmm2
; SSE-NEXT: subsd %xmm4, %xmm5 ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE-NEXT: cvttsd2si %xmm5, %rcx ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; SSE-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
; SSE-NEXT: xorq %rax, %rcx ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; SSE-NEXT: cvttsd2si %xmm1, %rdx ; SSE-NEXT: cvttpd2dq %xmm1, %xmm1
; SSE-NEXT: ucomisd %xmm4, %xmm1 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: cmovaeq %rcx, %rdx ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: movq %rdx, %xmm5 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE-NEXT: movapd %xmm1, %xmm6
; SSE-NEXT: subsd %xmm4, %xmm6
; SSE-NEXT: cvttsd2si %xmm6, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm1, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm1
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm1[0]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,2,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm1[0,2,2,3,4,5,6,7]
; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: subsd %xmm4, %xmm1
; SSE-NEXT: cvttsd2si %xmm1, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm0, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm0
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: movapd %xmm0, %xmm6
; SSE-NEXT: subsd %xmm4, %xmm6
; SSE-NEXT: cvttsd2si %xmm6, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm0, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm0
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1]
; SSE-NEXT: movapd %xmm3, %xmm0
; SSE-NEXT: subsd %xmm4, %xmm0
; SSE-NEXT: cvttsd2si %xmm0, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm3, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm3
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: movapd %xmm3, %xmm5
; SSE-NEXT: subsd %xmm4, %xmm5
; SSE-NEXT: cvttsd2si %xmm5, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm3, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm3
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm3
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm0[0,1,0,2,4,5,6,7]
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: subsd %xmm4, %xmm0
; SSE-NEXT: cvttsd2si %xmm0, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm2, %rdx
; SSE-NEXT: ucomisd %xmm4, %xmm2
; SSE-NEXT: cmovaeq %rcx, %rdx
; SSE-NEXT: movq %rdx, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movapd %xmm2, %xmm5
; SSE-NEXT: subsd %xmm4, %xmm5
; SSE-NEXT: cvttsd2si %xmm5, %rcx
; SSE-NEXT: xorq %rax, %rcx
; SSE-NEXT: cvttsd2si %xmm2, %rax
; SSE-NEXT: ucomisd %xmm4, %xmm2
; SSE-NEXT: cmovaeq %rcx, %rax
; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_8f64_to_8i16: ; VEX-LABEL: fptoui_8f64_to_8i16:
; AVX1: # %bb.0: ; VEX: # %bb.0:
; AVX1-NEXT: vmovapd {{.*#+}} ymm2 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9] ; VEX-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm2, %ymm1, %ymm3 ; VEX-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; VEX-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackssdw %xmm4, %xmm3, %xmm3 ; VEX-NEXT: vzeroupper
; AVX1-NEXT: vsubpd %ymm2, %ymm1, %ymm4 ; VEX-NEXT: retq
; AVX1-NEXT: vcvttpd2dq %ymm4, %xmm4
; AVX1-NEXT: vmovapd {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
; AVX1-NEXT: vxorpd %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX1-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vcmpltpd %ymm2, %ymm0, %ymm4
; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm6
; AVX1-NEXT: vpackssdw %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vsubpd %ymm2, %ymm0, %ymm2
; AVX1-NEXT: vcvttpd2dq %ymm2, %xmm2
; AVX1-NEXT: vxorpd %xmm5, %xmm2, %xmm2
; AVX1-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX1-NEXT: vblendvps %xmm4, %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: fptoui_8f64_to_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
; AVX2-NEXT: vcmpltpd %ymm2, %ymm1, %ymm3
; AVX2-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpackssdw %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vsubpd %ymm2, %ymm1, %ymm4
; AVX2-NEXT: vcvttpd2dq %ymm4, %xmm4
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
; AVX2-NEXT: vxorpd %xmm5, %xmm4, %xmm4
; AVX2-NEXT: vcvttpd2dq %ymm1, %xmm1
; AVX2-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm1
; AVX2-NEXT: vcmpltpd %ymm2, %ymm0, %ymm3
; AVX2-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpackssdw %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vsubpd %ymm2, %ymm0, %ymm2
; AVX2-NEXT: vcvttpd2dq %ymm2, %xmm2
; AVX2-NEXT: vxorpd %xmm5, %xmm2, %xmm2
; AVX2-NEXT: vcvttpd2dq %ymm0, %xmm0
; AVX2-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: fptoui_8f64_to_8i16: ; AVX512F-LABEL: fptoui_8f64_to_8i16:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0 ; AVX512F-NEXT: vcvttpd2dq %zmm0, %ymm0
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
Show All 22 Lines; AVX512VLDQ-NEXT: retq
%cvt = fptoui <8 x double> %a to <8 x i16> %cvt = fptoui <8 x double> %a to <8 x i16>
ret <8 x i16> %cvt ret <8 x i16> %cvt
} }
define <16 x i8> @fptosi_16f32_to_16i8(<16 x float> %a) { define <16 x i8> @fptosi_16f32_to_16i8(<16 x float> %a) {
; SSE-LABEL: fptosi_16f32_to_16i8: ; SSE-LABEL: fptosi_16f32_to_16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm3, %xmm3 ; SSE-NEXT: cvttps2dq %xmm3, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255]
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: cvttps2dq %xmm2, %xmm2 ; SSE-NEXT: cvttps2dq %xmm2, %xmm2
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: packssdw %xmm3, %xmm2
; SSE-NEXT: packuswb %xmm3, %xmm2
; SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: pand %xmm4, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm1, %xmm0 ; SSE-NEXT: packsswb %xmm2, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptosi_16f32_to_16i8: ; AVX1-LABEL: fptosi_16f32_to_16i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: fptosi_16f32_to_16i8: ; AVX2-LABEL: fptosi_16f32_to_16i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: fptosi_16f32_to_16i8: ; AVX512-LABEL: fptosi_16f32_to_16i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0 ; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%cvt = fptosi <16 x float> %a to <16 x i8> %cvt = fptosi <16 x float> %a to <16 x i8>
ret <16 x i8> %cvt ret <16 x i8> %cvt
} }
define <16 x i8> @fptoui_16f32_to_16i8(<16 x float> %a) { define <16 x i8> @fptoui_16f32_to_16i8(<16 x float> %a) {
; SSE-LABEL: fptoui_16f32_to_16i8: ; SSE-LABEL: fptoui_16f32_to_16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: cvttps2dq %xmm3, %xmm3 ; SSE-NEXT: cvttps2dq %xmm3, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255]
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: cvttps2dq %xmm2, %xmm2 ; SSE-NEXT: cvttps2dq %xmm2, %xmm2
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: packssdw %xmm3, %xmm2
; SSE-NEXT: packuswb %xmm3, %xmm2
; SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; SSE-NEXT: cvttps2dq %xmm1, %xmm1
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: pand %xmm4, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm1, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0 ; SSE-NEXT: packuswb %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fptoui_16f32_to_16i8: ; AVX1-LABEL: fptoui_16f32_to_16i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX1-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX1-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpackusdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: fptoui_16f32_to_16i8: ; AVX2-LABEL: fptoui_16f32_to_16i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1 ; AVX2-NEXT: vcvttps2dq %ymm1, %ymm1
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpackusdw %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0 ; AVX2-NEXT: vcvttps2dq %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpackusdw %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: fptoui_16f32_to_16i8: ; AVX512-LABEL: fptoui_16f32_to_16i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0 ; AVX512-NEXT: vcvttps2dq %zmm0, %zmm0
; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
; AVX512-NEXT: vzeroupper ; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%cvt = fptoui <16 x float> %a to <16 x i8> %cvt = fptoui <16 x float> %a to <16 x i8>
ret <16 x i8> %cvt ret <16 x i8> %cvt
} }