[AArch64] Allow -mattr=tpidr-el[1|2|3]

[philip.derrin]

Summary

Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base register, rather than the default TPIDR_EL0.

[• ryank]

Ping

[olista01]

What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?

lib/Target/AArch64/AArch64.td

244 ↗

(On Diff #174561)

Is this likely to be used for anything other than the TPIDR registers? I think it would be better to make the name more specific, unless we are also going to gate all system registers in the assembler on these features.

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

938 ↗

(On Diff #174561)

Why can SP_EL3 not be used?

[philip.derrin]

I will take over this patch; it was submitted by an intern at my employer who has since finished his internship.

In D54685#1343499, @olista01 wrote:

What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?

This is not useful, and I will remove it. It was based on the observation that in some kernels, SP_ELx is left pointing at a thread-local exception context while the kernel switches to SP_EL0, so SP_ELx could double as a TLS pointer, leaving TPIDR_ELx free for other uses. However, SP_ELx is not accessible via the MRS instruction at ELx; it can only be accessed at higher levels. This is also presumably the reason SP_EL3 was left out — it is never accessible to MRS so AArch64SysReg::SP_EL3 does not exist.

As for the naming of use-el*, would tpidr-el* be acceptable?

[olista01]

LGTM. Do you have commit access? If not, I can commit this for you.

[philip.derrin]

I don't have commit access; please go ahead and commit it.

llvm/trunk/lib/Target/AArch64/AArch64.td

 
 //===----------------------------------------------------------------------===//
 // Named operands for MRS/MSR/TLBI/...
 //===----------------------------------------------------------------------===//
 
 include "AArch64SystemOperands.td"
 
 //===----------------------------------------------------------------------===//
+// Access to privileged registers
+//===----------------------------------------------------------------------===//
+
+foreach i = 1-3 in
+def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
+  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
+
+//===----------------------------------------------------------------------===//
 // AArch64 Processors supported.
 //
 include "AArch64SchedA53.td"
 include "AArch64SchedA57.td"
 include "AArch64SchedCyclone.td"
 include "AArch64SchedFalkor.td"
 include "AArch64SchedKryo.td"
 include "AArch64SchedExynosM1.td"

llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
 
   case AArch64::MOVbaseTLS: {
     unsigned DstReg = MI.getOperand(0).getReg();
     auto SysReg = AArch64SysReg::TPIDR_EL0;
     MachineFunction *MF = MBB.getParent();
     if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
         MF->getTarget().getCodeModel() == CodeModel::Kernel)
       SysReg = AArch64SysReg::TPIDR_EL1;
+    else if (MF->getSubtarget<AArch64Subtarget>().useEL3ForTP())
+      SysReg = AArch64SysReg::TPIDR_EL3;
+    else if (MF->getSubtarget<AArch64Subtarget>().useEL2ForTP())
+      SysReg = AArch64SysReg::TPIDR_EL2;
+    else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
+      SysReg = AArch64SysReg::TPIDR_EL1;
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
         .addImm(SysReg);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::MOVi32imm:
     return expandMOVImm(MBB, MBBI, 32);

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasFuseAES = false;
   bool HasFuseArithmeticLogic = false;
   bool HasFuseCCSelect = false;
   bool HasFuseCryptoEOR = false;
   bool HasFuseLiterals = false;
   bool DisableLatencySchedHeuristic = false;
   bool UseRSqrt = false;
   bool Force32BitJumpTables = false;
+  bool UseEL1ForTP = false;
+  bool UseEL2ForTP = false;
+  bool UseEL3ForTP = false;
   uint8_t MaxInterleaveFactor = 2;
   uint8_t VectorInsertExtractBaseCost = 3;
   uint16_t CacheLineSize = 0;
   uint16_t PrefetchDistance = 0;
   uint16_t MinPrefetchStride = 1;
   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
   unsigned PrefFunctionAlignment = 0;
   unsigned PrefLoopAlignment = 0;
public:
 
   /// Return true if the CPU supports any kind of instruction fusion.
   bool hasFusion() const {
     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
            hasFuseAES() || hasFuseArithmeticLogic() ||
            hasFuseCCSelect() || hasFuseLiterals();
   }
 
+  bool useEL1ForTP() const { return UseEL1ForTP; }
+  bool useEL2ForTP() const { return UseEL2ForTP; }
+  bool useEL3ForTP() const { return UseEL3ForTP; }
+
   bool useRSqrt() const { return UseRSqrt; }
   bool force32BitJumpTables() const { return Force32BitJumpTables; }
   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
   unsigned getVectorInsertExtractBaseCost() const {
     return VectorInsertExtractBaseCost;
   }
   unsigned getCacheLineSize() const { return CacheLineSize; }
   unsigned getPrefetchDistance() const { return PrefetchDistance; }

llvm/trunk/test/CodeGen/AArch64/arm64-builtins-linux.ll

 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el1 | FileCheck --check-prefix=USEEL1 %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el2 | FileCheck --check-prefix=USEEL2 %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el3 | FileCheck --check-prefix=USEEL3 %s
 
 ; Function Attrs: nounwind readnone
 declare i8* @llvm.thread.pointer() #1
 
 define i8* @thread_pointer() {
 ; CHECK: thread_pointer:
 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
 ; FUCHSIA-KERNEL: thread_pointer:
 ; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
+; USEEL1: thread_pointer:
+; USEEL1: mrs {{x[0-9]+}}, TPIDR_EL1
+; USEEL2: thread_pointer:
+; USEEL2: mrs {{x[0-9]+}}, TPIDR_EL2
+; USEEL3: thread_pointer:
+; USEEL3: mrs {{x[0-9]+}}, TPIDR_EL3
   %1 = tail call i8* @llvm.thread.pointer()
   ret i8* %1
 }