Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base register, rather than the default TPIDR_EL0.
What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?
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Is this likely to be used for anything other than the TPIDR registers? I think it would be better to make the name more specific, unless we are also going to gate all system registers in the assembler on these features.
|938 ↗||(On Diff #174561)|
Why can SP_EL3 not be used?
I will take over this patch; it was submitted by an intern at my employer who has since finished his internship.
This is not useful, and I will remove it. It was based on the observation that in some kernels, SP_ELx is left pointing at a thread-local exception context while the kernel switches to SP_EL0, so SP_ELx could double as a TLS pointer, leaving TPIDR_ELx free for other uses. However, SP_ELx is not accessible via the MRS instruction at ELx; it can only be accessed at higher levels. This is also presumably the reason SP_EL3 was left out — it is never accessible to MRS so AArch64SysReg::SP_EL3 does not exist.
As for the naming of use-el*, would tpidr-el* be acceptable?