[AArch64] Allow -mattr=tpidr-el[1|2|3]

[philip.derrin]

Summary

Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base register, rather than the default TPIDR_EL0.

[• ryank]

Ping

[olista01]

What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?

lib/Target/AArch64/AArch64.td

244

Is this likely to be used for anything other than the TPIDR registers? I think it would be better to make the name more specific, unless we are also going to gate all system registers in the assembler on these features.

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

938

Why can SP_EL3 not be used?

[philip.derrin]

I will take over this patch; it was submitted by an intern at my employer who has since finished his internship.

In D54685#1343499, @olista01 wrote:

What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?

This is not useful, and I will remove it. It was based on the observation that in some kernels, SP_ELx is left pointing at a thread-local exception context while the kernel switches to SP_EL0, so SP_ELx could double as a TLS pointer, leaving TPIDR_ELx free for other uses. However, SP_ELx is not accessible via the MRS instruction at ELx; it can only be accessed at higher levels. This is also presumably the reason SP_EL3 was left out — it is never accessible to MRS so AArch64SysReg::SP_EL3 does not exist.

As for the naming of use-el*, would tpidr-el* be acceptable?

[olista01]

LGTM. Do you have commit access? If not, I can commit this for you.

[philip.derrin]

I don't have commit access; please go ahead and commit it.

lib/Target/AArch64/AArch64.td

def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
     "true", "Enable Branch Target Identification" >;
 
 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
     "true", "Enable Random Number generation instructions" >;
 
 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
     "true", "Enable Memory Tagging Extension" >;
 
+foreach i = 1-3 in
+    def FeatureUseEL#i : SubtargetFeature<"use-el"#i, "UseEL"#i, "true",
+                                          "Generate access to EL"#i#" registers">;
+
+def FeatureUseSPForTP : SubtargetFeature<"use-sp-for-tp", "UseSPForTP", "true",
+                                      "Use SP_EL[1|2] instead of TPIDR_EL[1|2] for TLS">;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
 
   case AArch64::MOVbaseTLS: {
     unsigned DstReg = MI.getOperand(0).getReg();
     auto SysReg = AArch64SysReg::TPIDR_EL0;
     MachineFunction *MF = MBB.getParent();
     if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
         MF->getTarget().getCodeModel() == CodeModel::Kernel)
       SysReg = AArch64SysReg::TPIDR_EL1;
+    const auto &ST = MF->getSubtarget<AArch64Subtarget>();
+    if (ST.hasFeature(AArch64::FeatureUseSPForTP)) {
+      if (ST.hasFeature(AArch64::FeatureUseEL2))
+        SysReg = AArch64SysReg::SP_EL2;
+      else if (ST.hasFeature(AArch64::FeatureUseEL1))
+        SysReg = AArch64SysReg::SP_EL1;
+      else
+        report_fatal_error("SP can only be used for TP in EL1 or EL2");
+    } else {
+      if (ST.hasFeature(AArch64::FeatureUseEL3))
+        SysReg = AArch64SysReg::TPIDR_EL3;
+      else if (ST.hasFeature(AArch64::FeatureUseEL2))
+        SysReg = AArch64SysReg::TPIDR_EL2;
+      else if (ST.hasFeature(AArch64::FeatureUseEL1))
+        SysReg = AArch64SysReg::TPIDR_EL1;
+    }
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
         .addImm(SysReg);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::MOVi32imm:
     return expandMOVImm(MBB, MBBI, 32);

lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasFuseAddress = false;
   bool HasFuseAES = false;
   bool HasFuseCryptoEOR = false;
   bool HasFuseCCSelect = false;
   bool HasFuseLiterals = false;
   bool DisableLatencySchedHeuristic = false;
   bool UseRSqrt = false;
   bool Force32BitJumpTables = false;
+  bool UseEL1 = false;
+  bool UseEL2 = false;
+  bool UseEL3 = false;
+  bool UseSPForTP = false;
   uint8_t MaxInterleaveFactor = 2;
   uint8_t VectorInsertExtractBaseCost = 3;
   uint16_t CacheLineSize = 0;
   uint16_t PrefetchDistance = 0;
   uint16_t MinPrefetchStride = 1;
   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
   unsigned PrefFunctionAlignment = 0;
   unsigned PrefLoopAlignment = 0;
public:
   bool hasFuseLiterals() const { return HasFuseLiterals; }
 
   /// Return true if the CPU supports any kind of instruction fusion.
   bool hasFusion() const {
     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
            hasFuseAES() || hasFuseCCSelect() || hasFuseLiterals();
   }
 
+  bool useEL1() const { return UseEL1; }
+  bool useEL2() const { return UseEL2; }
+  bool useEL3() const { return UseEL3; }
+  bool useSPForTP() const { return UseSPForTP; }
+
   bool useRSqrt() const { return UseRSqrt; }
   bool force32BitJumpTables() const { return Force32BitJumpTables; }
   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
   unsigned getVectorInsertExtractBaseCost() const {
     return VectorInsertExtractBaseCost;
   }
   unsigned getCacheLineSize() const { return CacheLineSize; }
   unsigned getPrefetchDistance() const { return PrefetchDistance; }

test/CodeGen/AArch64/arm64-builtins-linux.ll

 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+use-el1 | FileCheck --check-prefix=USEEL1 %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+use-el2 | FileCheck --check-prefix=USEEL2 %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+use-el3 | FileCheck --check-prefix=USEEL3 %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+use-el1,+use-sp-for-tp | FileCheck --check-prefix=USEEL1-USESPFORTP %s
+; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+use-el2,+use-sp-for-tp | FileCheck --check-prefix=USEEL2-USESPFORTP %s
 
 ; Function Attrs: nounwind readnone
 declare i8* @llvm.thread.pointer() #1
 
 define i8* @thread_pointer() {
 ; CHECK: thread_pointer:
 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
 ; FUCHSIA-KERNEL: thread_pointer:
 ; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
+; USEEL1: thread_pointer:
+; USEEL1: mrs {{x[0-9]+}}, TPIDR_EL1
+; USEEL2: thread_pointer:
+; USEEL2: mrs {{x[0-9]+}}, TPIDR_EL2
+; USEEL3: thread_pointer:
+; USEEL3: mrs {{x[0-9]+}}, TPIDR_EL3
+; USEEL1-USESPFORTP: thread_pointer:
+; USEEL1-USESPFORTP: mrs {{x[0-9]+}}, SP_EL1
+; USEEL2-USESPFORTP: thread_pointer:
+; USEEL2-USESPFORTP: mrs {{x[0-9]+}}, SP_EL2
   %1 = tail call i8* @llvm.thread.pointer()
   ret i8* %1
 }