Fix MachineInstr::findRegisterUseOperandIdx subreg checks

[rampitec]

Summary

The function only checks that instruction reads a super-register
containing requested physical register. In case if a sub-register
if being read that is also a use of a super-reg, so added the check.
In particular MI->readsRegister() is broken because of the missing
check. The resulting check is essentially regsOverlap().

[rampitec]

I have realized the old check was also needed, an instruction reads a register in both cases: if the operand is a subreg of a requested register or if it is a superreg.

With the new patch previous changes to other targets are gone. Therefor gone the ask to review their test changes.

[rampitec]

The effective check is just regsOverlap().

[arsenm]

lib/CodeGen/MachineInstr.cpp

936

Why is TRI optional here? I would expect it to be mandatory if there is a physical register and assert

[rampitec]

lib/CodeGen/MachineInstr.cpp

936

That's a good question why, but it is optional.
I have tried to use just TRI->regsOverlap() instead of the whole condition, and then run into crashes due to TRI being nullptr.

[rampitec]

lib/CodeGen/MachineInstr.cpp

936

Here are just some examples of places where the function is called without optional TRI operand and with a physreg:

lib/Target/AArch64/AArch64InstrInfo.cpp:

1515│ case AArch64::FCSELDrrr: {
1516├> int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);

lib/Target/AMDGPU/SIInstrInfo.cpp:

4769├> if (MI.findRegisterUseOperandIdx(AMDGPU::SCC) != -1)
4770│ Worklist.insert(&MI);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp:

891├> bool BaseKill = LatestMI->killsRegister(Base);

and then:

include/llvm/CodeGen/MachineInstr.h:

1134│ bool killsRegister(unsigned Reg,
1135│ const TargetRegisterInfo *TRI = nullptr) const {
1136├> return findRegisterUseOperandIdx(Reg, true, TRI) != -1;

There is huge number of places across all targets.

[rampitec]

lib/CodeGen/MachineInstr.cpp

936

Altogether 2539 tests fail across all targets if TRI check is removed, even if physreg check is in place.

[arsenm]

lib/CodeGen/MachineInstr.cpp

936

Is there any real reason not to pass it in though? I would think it shouldn't be hard to make it mandatory, other than the manual work

[rampitec]

lib/CodeGen/MachineInstr.cpp

936

I do not think there is such a reason. That is just a lot of places across all backends.
Anyway, this is really orthogonal to this patch.

[nhaehnle]

The code change looks fine to me, but it should be possible to cleanup the test case a bit.

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

135–151

It should be possible to remove most of the IR here.

760–781

It should be possible to remove most of this boilerplate.

[rampitec]

Test cleanup.

[arsenm]

LGTM

lib/CodeGen/MachineInstr.cpp

int MachineInstr::findRegisterUseOperandIdx(
     unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = getOperand(i);
     if (!MO.isReg() || !MO.isUse())
       continue;
     unsigned MOReg = MO.getReg();
     if (!MOReg)
       continue;
-    if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
-                         TargetRegisterInfo::isPhysicalRegister(Reg) &&
-                         TRI->isSubRegister(MOReg, Reg)))
+    if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
       if (!isKill || MO.isKill())
         return i;
   }
   return -1;
 }
 
 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
 /// indicating if this instruction reads or writes Reg. This also considers

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

--- |
 
   if:
     br label %end
 
   end:
     ret void
   }
 
+  define amdgpu_kernel void @if_and_xor_read_exec_copy_subreg(i32 %z, i32 %v) #0 {
+  main_body:
+    %id = call i32 @llvm.amdgcn.workitem.id.x()
+    %cc = icmp eq i32 %id, 0
+    %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %cc)
+    %1 = extractvalue { i1, i64 } %0, 0
+    %2 = extractvalue { i1, i64 } %0, 1
+    br i1 %1, label %if, label %end
+
+  if:                                               ; preds = %main_body
+    %v.if = load volatile i32, i32 addrspace(1)* undef
+    br label %end
+
+  end:                                              ; preds = %if, %main_body
+    %r = phi i32 [ 4, %main_body ], [ %v.if, %if ]
+    call void @llvm.amdgcn.end.cf(i64 %2)
+    store i32 %r, i32 addrspace(1)* undef
+    ret void
+  }
+
   ; Function Attrs: nounwind readnone
   declare i32 @llvm.amdgcn.workitem.id.x() #1
 
   declare { i1, i64 } @llvm.amdgcn.if(i1)
 
   declare void @llvm.amdgcn.end.cf(i64)
 
 
bb.2.end:
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(1)* undef`)
     S_ENDPGM
 
 ...
+---
+# A read from exec copy subreg prevents optimization
+# CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}}
+# CHECK: $sgpr0_sgpr1 = COPY $exec
+# CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1
+name:            if_and_xor_read_exec_copy_subreg
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$vgpr0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.main_body:
+    liveins: $vgpr0
+
+    $sgpr0_sgpr1 = COPY $exec
+    $sgpr4 = S_MOV_B32 $sgpr1
+    $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
+    $vgpr0 = V_MOV_B32_e32 4, implicit $exec
+    $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
+    $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
+    $exec = S_MOV_B64_term killed $sgpr2_sgpr3
+    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1.if:
+    liveins: $sgpr0_sgpr1
+
+    $sgpr7 = S_MOV_B32 61440
+    $sgpr6 = S_MOV_B32 -1
+    $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
+
+  bb.2.end:
+    liveins: $vgpr0, $sgpr0_sgpr1
+
+    $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
+    $sgpr3 = S_MOV_B32 61440
+    $sgpr2 = S_MOV_B32 -1
+    BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(1)* undef`)
+    S_ENDPGM
+...