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sbaranga (silviu.baranga@arm.com)
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May 21 2015, 2:19 AM (225 w, 6 d)

Recent Activity

May 31 2019

sbaranga accepted D62734: [AArch64] Check for simple type in FPToUInt.

Seems reasonable to me. LGTM

May 31 2019, 8:19 AM · Restricted Project

May 30 2019

sbaranga accepted D62624: [InstCombine] Avoid use after free in DenseMap, when built with GCC.

Thanks, LGTM!

May 30 2019, 4:09 AM · Restricted Project

Jan 6 2019

sbaranga accepted D56098: [ARM] Teach ComputeKnownBitsTarget to handle extract vectors.

LGTM! (with one nit)

Jan 6 2019, 3:39 PM

Dec 28 2018

sbaranga added inline comments to D56098: [ARM] Teach ComputeKnownBitsTarget to handle extract vectors.
Dec 28 2018, 8:42 AM
sbaranga added inline comments to D56098: [ARM] Teach ComputeKnownBitsTarget to handle extract vectors.
Dec 28 2018, 2:12 AM

Oct 26 2018

sbaranga accepted D53748: [ARM] Fix test inlineasm-X-allocation.ll.

Thanks, LGTM!

Oct 26 2018, 7:54 AM
sbaranga added a comment to D53748: [ARM] Fix test inlineasm-X-allocation.ll.

The initial intent was to make sure that we are forcing the operands to not be VFP registers, so I would have expected to get a vadd.f32 r0, r0, r0. However, since the instruction is invalid it doesn't make a good test (as you observed).

Oct 26 2018, 4:51 AM
sbaranga added a comment to D53748: [ARM] Fix test inlineasm-X-allocation.ll.

IIRC the contents of the asm string shouldn't matter here, and we would expect to get an error in the assembler instead when trying to assemble the output (which is fine, since this is a misuse of the X constraint).

Oct 26 2018, 4:03 AM

Aug 24 2018

sbaranga added a comment to D50644: [WIP] [LAA] Allow runtime checks when strides different but address space does not wrap around.

For pointer-with-unknown-bounds.ll, I think the point was just checking that we don't vectorize in the case where the SCEV expressions for the pointers are not affine.

Aug 24 2018, 12:39 AM

Aug 17 2018

sbaranga added a comment to D50644: [WIP] [LAA] Allow runtime checks when strides different but address space does not wrap around.

Hi Anna,

Aug 17 2018, 8:13 AM

Jul 19 2018

sbaranga accepted D49463: [ARM] Add new feature to enable optimizing the VFP registers.

LGTM

Jul 19 2018, 11:58 PM

Jul 18 2018

sbaranga added a comment to D49461: [LV] Fix for PR38110, LV encountered llvm_unreachable() .

Seems reasonable to me.

Ideally we should be handling the phi node case (which is why the unreachable was there), but crashing doesn't seem like the right thing to do.

Personally, I see a value in differentiating explicitly known handling versus just being conservative ----- but I don't mind converting that into a comment instead if that's preferred.

Jul 18 2018, 11:04 PM
sbaranga added inline comments to D49463: [ARM] Add new feature to enable optimizing the VFP registers.
Jul 18 2018, 10:59 PM
sbaranga added inline comments to D49463: [ARM] Add new feature to enable optimizing the VFP registers.
Jul 18 2018, 8:43 AM
sbaranga added a comment to D49461: [LV] Fix for PR38110, LV encountered llvm_unreachable() .

Seems reasonable to me.

Jul 18 2018, 2:02 AM
sbaranga added a comment to D49463: [ARM] Add new feature to enable optimizing the VFP registers.

If this is no longer only used by Cortex-A15, I think the regression tests need to be updated to use the new feature instead of the passing the cpu.

Jul 18 2018, 1:05 AM

Mar 22 2018

sbaranga accepted D44768: revert 325687.

LGTM, thanks!

Mar 22 2018, 12:14 AM

Feb 21 2018

sbaranga committed rL325687: [SCEV] Temporarily disable loop versioning for the purpose.
[SCEV] Temporarily disable loop versioning for the purpose
Feb 21 2018, 7:24 AM

Feb 19 2018

sbaranga accepted D42604: PR36032 fix assert cause by not computed SCEV PredicatedBackEdgeCount.
Feb 19 2018, 8:10 AM

Feb 12 2018

sbaranga added a comment to D42604: PR36032 fix assert cause by not computed SCEV PredicatedBackEdgeCount.

LGTM with one minor nit.

Feb 12 2018, 1:05 AM

Jan 29 2018

sbaranga added a comment to D42604: PR36032 fix assert cause by not computed SCEV PredicatedBackEdgeCount.

Thanks for submitting the fix! Please see the inline comments.

Jan 29 2018, 1:12 AM

Dec 13 2017

sbaranga added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

LGTM!

Dec 13 2017, 2:44 AM

Dec 10 2017

sbaranga added inline comments to D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Dec 10 2017, 11:03 AM

Dec 5 2017

sbaranga added inline comments to D40625: Harmonizing attribute GNU/C++ spellings.
Dec 5 2017, 2:07 AM

Nov 28 2017

sbaranga added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Dorit,

Nov 28 2017, 12:50 PM

Nov 20 2017

sbaranga added inline comments to D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Nov 20 2017, 1:15 PM

Nov 19 2017

sbaranga added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

IIUC, what IndVarSimply does is call the rewriter and then fix the users of the induction; This is similar in effect to what we do: We don't need to call the PSCEV rewriter again, we already have the nice AddRec for the induction phi (isInductionPhi() had already obtained it); The vectorization of the induction phi proceeds unchanged; The only thing we are adding is the def-use wiring so that in the vectorized loop, any users of the cast instructions will be users of the vectorized phi. We never vectorize the casts, and we never actively remove them -- they will end up dead code in the vectorized loop because they will not be used.

Nov 19 2017, 10:55 AM

Nov 18 2017

sbaranga added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Sorry for not having a look earlier.

Nov 18 2017, 7:13 AM

Sep 13 2017

sbaranga added a comment to D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

Hi Anna,

Sep 13 2017, 7:20 AM

Sep 12 2017

sbaranga added a comment to D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

Thanks! Committed in r313012.

Sep 12 2017, 12:52 AM
sbaranga committed rL313012: [LAA] Allow more run-time alias checks by coercing pointer expressions to….
[LAA] Allow more run-time alias checks by coercing pointer expressions to…
Sep 12 2017, 12:49 AM
sbaranga closed D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.
Sep 12 2017, 12:49 AM

Aug 23 2017

sbaranga updated the diff for D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

Address comments received so far.

Aug 23 2017, 8:57 AM

Aug 21 2017

sbaranga added a comment to D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

Sorry for not replying earlier. It looks like there are only minor changes left? I plan to push an update after this gets unblocked.

Aug 21 2017, 2:46 AM

Jul 3 2017

sbaranga added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

It looks ok to me, thanks!

Jul 3 2017, 8:35 AM

Jun 14 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Jun 14 2017, 9:03 AM

Jun 13 2017

sbaranga added a comment to D33836: [AArch64] Enable FeatureFuseAES for the generic processor model..

This generally makes sense to me!

Jun 13 2017, 7:55 AM

Jun 12 2017

sbaranga added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Sorry for the delay, I missed the last update. I have a few minor suggestions, but otherwise I think it generally looks good.
I think Sanjoy still needs to approve this before it can go in.

Jun 12 2017, 9:56 AM

Jun 6 2017

sbaranga added a comment to D33836: [AArch64] Enable FeatureFuseAES for the generic processor model..

We already have the IR in misched-fusion-aes.ll that can be used for microbenchmarks (just call the functions in a loop)? I think that should be theoretically enough for an evaluation.

Jun 6 2017, 8:56 AM

May 22 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
May 22 2017, 3:20 PM

May 15 2017

sbaranga added a comment to D33196: [AArch64] Explicitly enable FeatureFuseLiterals on Cortex-A72 (NFC)..

Hi Florian,

May 15 2017, 8:11 AM

Apr 26 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Apr 26 2017, 9:10 AM

Apr 25 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Apr 25 2017, 10:40 AM

Apr 23 2017

sbaranga added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

nitpick: you should run a spell checker over the patch.

Apr 23 2017, 2:52 PM

Apr 12 2017

sbaranga added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Hi Dorit,

Apr 12 2017, 4:53 AM

Apr 4 2017

sbaranga accepted D31655: [LAA] Correctly return a half-open range in expandBounds.
Apr 4 2017, 4:46 AM
sbaranga added a comment to D31655: [LAA] Correctly return a half-open range in expandBounds.

LGTM

Apr 4 2017, 4:46 AM
sbaranga added inline comments to D31655: [LAA] Correctly return a half-open range in expandBounds.
Apr 4 2017, 3:52 AM

Mar 21 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Mar 21 2017, 7:20 AM

Mar 16 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Mar 16 2017, 10:29 AM

Mar 9 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Mar 9 2017, 2:35 AM

Mar 8 2017

sbaranga updated the diff for D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

Renaming Force to Assume.

Mar 8 2017, 9:16 AM

Mar 7 2017

sbaranga added inline comments to D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.
Mar 7 2017, 3:05 AM

Feb 28 2017

sbaranga added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Hi Dorit,

Feb 28 2017, 5:56 AM

Feb 20 2017

sbaranga added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
Feb 20 2017, 10:35 AM

Jan 31 2017

sbaranga committed rL293629: [InstCombine] Make sure that LHS and RHS have the same type in.
[InstCombine] Make sure that LHS and RHS have the same type in
Jan 31 2017, 6:15 AM

Jan 10 2017

sbaranga accepted D28400: [AArch64] Use generic bitreverse intrinsic, rather than AArch64 specific..

This looks straight-forward to me. LGTM.

Jan 10 2017, 8:52 AM
sbaranga accepted D28379: [AArch64] Add support for lowering the bitreverse intrinsic to the rbit instruction..

LGTM!

Jan 10 2017, 8:35 AM
sbaranga added inline comments to D28393: [SCEV] Make howFarToZero produce a smaller max backedge-taken count.
Jan 10 2017, 6:59 AM

Nov 30 2016

sbaranga added a comment to D27130: [AArch64] Fix useful bits detection for BFM instructions.

Thanks, both! r288253

Nov 30 2016, 9:15 AM
sbaranga committed rL288253: [AArch64] Fix useful bits detection for BFM instructions.
[AArch64] Fix useful bits detection for BFM instructions
Nov 30 2016, 9:14 AM
sbaranga closed D27130: [AArch64] Fix useful bits detection for BFM instructions.
Nov 30 2016, 9:14 AM

Nov 29 2016

sbaranga updated the diff for D27130: [AArch64] Fix useful bits detection for BFM instructions.

Update variable names names in the test and make it more readable overall.

Nov 29 2016, 7:20 AM

Nov 25 2016

sbaranga added a comment to D26856: [AArch64] Introduce features that will allow only assembler support for neon, crypto, fp-armv8 and fullfp16..

It looks like gcc should have been emitting an error here instead of the "sorry, not implemented".

Nov 25 2016, 8:48 AM
sbaranga retitled D27130: [AArch64] Fix useful bits detection for BFM instructions from to [AArch64] Fix useful bits detection for BFM instructions.
Nov 25 2016, 6:52 AM

Nov 23 2016

sbaranga added a comment to D26856: [AArch64] Introduce features that will allow only assembler support for neon, crypto, fp-armv8 and fullfp16..

Thanks, that makes sense. I also wasn't aware of no-implicit-float.

Nov 23 2016, 7:35 AM

Nov 18 2016

sbaranga updated the diff for D26858: [AArch64] Don't constrain the assembler when using -mgeneral-regs-only.

Update regression tests.

Nov 18 2016, 9:13 AM
sbaranga retitled D26858: [AArch64] Don't constrain the assembler when using -mgeneral-regs-only from to [AArch64] Don't constrain the assembler when using -mgeneral-regs-only.
Nov 18 2016, 8:04 AM
sbaranga retitled D26856: [AArch64] Introduce features that will allow only assembler support for neon, crypto, fp-armv8 and fullfp16. from to [AArch64] Introduce features that will allow only assembler support for neon, crypto, fp-armv8 and fullfp16..
Nov 18 2016, 7:58 AM

Oct 26 2016

sbaranga accepted D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

Thanks for making the changes! LGTM

Oct 26 2016, 5:29 AM
sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

Yes, now that I think about it skipping case c) makes sense.

Oct 26 2016, 3:03 AM

Oct 24 2016

sbaranga added inline comments to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .
Oct 24 2016, 2:45 AM

Oct 21 2016

sbaranga added inline comments to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .
Oct 21 2016, 4:05 AM
sbaranga added a comment to D25682: [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops.

LGTM for the SCEV part.

Oct 21 2016, 1:55 AM

Oct 20 2016

sbaranga added inline comments to D25682: [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops.
Oct 20 2016, 6:50 AM
sbaranga added inline comments to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .
Oct 20 2016, 6:42 AM

Oct 19 2016

sbaranga added inline comments to D25682: [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops.
Oct 19 2016, 11:35 AM
sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

Intuitively it seems like we would want to use getPtrStride in the interleaved access analysis the same way we do in isConsecutivePtr. Is the issue here that we might add additional run-time checks that we aren't currently? We already call isConsecutivePtr for the pointer operand of every load/store in the loop. Would the additional checks then be duplicates?

Oct 19 2016, 8:19 AM

Oct 18 2016

sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

I see. Thanks.

So in this case, don't we have a problem of potentially adding runtime SCEV assumptions without ever checking if we exceed the threshold? getPtrStride is called with Assume=true several times from the cost-model stage and from the actual vectorization transformation stage, via the call to isConsecutivePtr. Looks like these call sites are past the point when we check whether we exceeded the threshold for runtime SCEV assumptions...?

Oct 18 2016, 10:50 AM

Oct 14 2016

sbaranga accepted D25464: [NFC] Loop Versioning for LICM code clean up.

LGTM

Oct 14 2016, 2:37 AM
sbaranga added inline comments to D25464: [NFC] Loop Versioning for LICM code clean up.
Oct 14 2016, 2:25 AM

Oct 12 2016

sbaranga added inline comments to D25464: [NFC] Loop Versioning for LICM code clean up.
Oct 12 2016, 11:03 AM

Oct 11 2016

sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

Agreed?

Oct 11 2016, 9:08 AM
sbaranga added inline comments to D24934: [LICM] Add support of a new optimization case to Loop Versioning for LICM + code clean up.
Oct 11 2016, 2:21 AM

Oct 10 2016

sbaranga added a comment to D24934: [LICM] Add support of a new optimization case to Loop Versioning for LICM + code clean up.

I just had a brief look through this, but I don't think LAA changes are correct (see the inline comment).
Also if there are non-functional changes here, could you split them into another review (this would make things easier to understand)?

Oct 10 2016, 9:44 AM
sbaranga updated subscribers of D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .
Oct 10 2016, 8:10 AM
sbaranga added reviewers for D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride : anemet, mssimpso.
Oct 10 2016, 6:37 AM
sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

Thanks Silviu for the detailed explanation.

ShouldCheckWrap indicates if we need to check if the pointer is wrapping in order to identify this as a strided pointer. This is mainly needed for dependence analysis.

So I take it we are fine with ShouldCheckWrap=false here (being past the dependence testing stage).

Oct 10 2016, 6:36 AM

Oct 8 2016

sbaranga added a comment to D25276: [LoopVectorizer] Interleaved-mem-accesses analysis and getPtrStride .

ShouldCheckWrap indicates if we need to check if the pointer is wrapping in order to identify this as a strided pointer. This is mainly needed for dependence analysis.

Oct 8 2016, 6:20 AM

Sep 28 2016

sbaranga accepted D25000: [SCEV] Use a SmallPtrSet as a temporary union predicate; NFC.
Sep 28 2016, 2:49 AM
sbaranga added a comment to D25000: [SCEV] Use a SmallPtrSet as a temporary union predicate; NFC.

Very nice! LGTM

Sep 28 2016, 2:48 AM

Sep 14 2016

sbaranga committed rL281474: [StackProtector] Use INITIALIZE_TM_PASS instead of INITIALIZE_PASS.
[StackProtector] Use INITIALIZE_TM_PASS instead of INITIALIZE_PASS
Sep 14 2016, 7:18 AM

Sep 7 2016

sbaranga added a comment to D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set.

I've investigated using MIR for getting a test case. The problem that I currently have with this is that I'm unable to run the PEI pass (where the problem is happening). If I try to do this I get a segfault in the stack protector pass. The problem seems to be that the TargetMachine is null. I'm not sure if this is something specific to PEI - but there doesn't seem to be any other regression tests that tries to run just this pass.

Sep 7 2016, 9:00 AM
sbaranga added a comment to D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set.

Have you investigate using the mir representation to produce a test case?

Sep 7 2016, 3:49 AM

Sep 6 2016

sbaranga added a comment to D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set.

Thanks, Hal! r280698

Sep 6 2016, 3:19 AM
sbaranga committed rL280698: [RegisterScavenger] Remove aliasing registers of operands from the candidate set.
[RegisterScavenger] Remove aliasing registers of operands from the candidate set
Sep 6 2016, 3:18 AM
sbaranga closed D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set.
Sep 6 2016, 3:18 AM

Sep 1 2016

sbaranga retitled D24130: [RegisterScavenger] Remove aliasing registers of operands from the candidate set from to [RegisterScavenger] Remove aliasing registers of operands from the candidate set.
Sep 1 2016, 6:57 AM

Aug 8 2016

sbaranga added a comment to D23261: [AArch64] PR28877: Don't assume we're running after legalization when creating vcvtfp2fxs.

Thanks, James! Committed in r278002.

Aug 8 2016, 6:22 AM
sbaranga committed rL278002: [AArch64] PR28877: Don't assume we're running after legalization when….
[AArch64] PR28877: Don't assume we're running after legalization when…
Aug 8 2016, 6:22 AM