Fix MachineInstr::findRegisterUseOperandIdx subreg checks

[rampitec]

Summary

The function only checks that instruction reads a super-register
containing requested physical register. In case if a sub-register
if being read that is also a use of a super-reg, so added the check.
In particular MI->readsRegister() is broken because of the missing
check. The resulting check is essentially regsOverlap().

[rampitec]

I have realized the old check was also needed, an instruction reads a register in both cases: if the operand is a subreg of a requested register or if it is a superreg.

With the new patch previous changes to other targets are gone. Therefor gone the ask to review their test changes.

[rampitec]

The effective check is just regsOverlap().

[arsenm]

lib/CodeGen/MachineInstr.cpp

938

Why is TRI optional here? I would expect it to be mandatory if there is a physical register and assert

[rampitec]

lib/CodeGen/MachineInstr.cpp

938

That's a good question why, but it is optional.
I have tried to use just TRI->regsOverlap() instead of the whole condition, and then run into crashes due to TRI being nullptr.

[rampitec]

lib/CodeGen/MachineInstr.cpp

938

Here are just some examples of places where the function is called without optional TRI operand and with a physreg:

lib/Target/AArch64/AArch64InstrInfo.cpp:

1515│ case AArch64::FCSELDrrr: {
1516├> int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);

lib/Target/AMDGPU/SIInstrInfo.cpp:

4769├> if (MI.findRegisterUseOperandIdx(AMDGPU::SCC) != -1)
4770│ Worklist.insert(&MI);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp:

891├> bool BaseKill = LatestMI->killsRegister(Base);

and then:

include/llvm/CodeGen/MachineInstr.h:

1134│ bool killsRegister(unsigned Reg,
1135│ const TargetRegisterInfo *TRI = nullptr) const {
1136├> return findRegisterUseOperandIdx(Reg, true, TRI) != -1;

There is huge number of places across all targets.

[rampitec]

lib/CodeGen/MachineInstr.cpp

938

Altogether 2539 tests fail across all targets if TRI check is removed, even if physreg check is in place.

[arsenm]

lib/CodeGen/MachineInstr.cpp

938

Is there any real reason not to pass it in though? I would think it shouldn't be hard to make it mandatory, other than the manual work

[rampitec]

lib/CodeGen/MachineInstr.cpp

938

I do not think there is such a reason. That is just a lot of places across all backends.
Anyway, this is really orthogonal to this patch.

[nhaehnle]

The code change looks fine to me, but it should be possible to cleanup the test case a bit.

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

135–151

It should be possible to remove most of the IR here.

760–781

It should be possible to remove most of this boilerplate.

[rampitec]

Test cleanup.

[arsenm]

LGTM

lib/CodeGen/MachineInstr.cpp

for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = getOperand(i);
     if (!MO.isReg() || !MO.isUse())
       continue;
     unsigned MOReg = MO.getReg();
     if (!MOReg)
       continue;
     if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
                          TargetRegisterInfo::isPhysicalRegister(Reg) &&
-                         TRI->isSubRegister(MOReg, Reg)))
+                         TRI->isSubRegister(Reg, MOReg)))
       if (!isKill || MO.isKill())
         return i;
   }
   return -1;
 }
 
 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
 /// indicating if this instruction reads or writes Reg. This also considers

test/CodeGen/AArch64/post-ra-machine-sink.mir

 ...
 
 ---
 # Sink w19 to %bb.3 through %bb.2.
 # CHECK-LABEL: name: sinkcopy8
 # CHECK-LABEL: bb.0:
 # CHECK-NOT: renamable $w19 = COPY $w0, implicit-def $x19
 # CHECK-LABEL: bb.2:
-# CHECK: $w1 = ADDWrr $w1, $w0, implicit $x0
+# CHECK: $w1 = ADDWrr $w1, $w0, implicit killed $x0
 # CHECK-LABEL: bb.3:
 # CHECK: liveins: $x1, $w0
-# CHECK: renamable $w19 = COPY killed $w0, implicit-def $x19
+# CHECK: renamable $w19 = COPY $w0, implicit-def $x19
 name: sinkcopy8
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $w0, $x1
     $w1 = SUBSWri $w1, 1, 0, implicit-def $nzcv
     renamable $w19 = COPY $w0, implicit-def $x19
     Bcc 11, %bb.2, implicit $nzcv

test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

--- |
 
   if:
     br label %end
 
   end:
     ret void
   }
 
+  define amdgpu_kernel void @if_and_xor_read_exec_copy_subreg(i32 %z, i32 %v) #0 {
+  main_body:
+    %id = call i32 @llvm.amdgcn.workitem.id.x()
+    %cc = icmp eq i32 %id, 0
+    %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %cc)
+    %1 = extractvalue { i1, i64 } %0, 0
+    %2 = extractvalue { i1, i64 } %0, 1
+    br i1 %1, label %if, label %end
+
+  if:                                               ; preds = %main_body
+    %v.if = load volatile i32, i32 addrspace(1)* undef
+    br label %end
+
+  end:                                              ; preds = %if, %main_body
+    %r = phi i32 [ 4, %main_body ], [ %v.if, %if ]
+    call void @llvm.amdgcn.end.cf(i64 %2)
+    store i32 %r, i32 addrspace(1)* undef
+    ret void
+  }
+
   ; Function Attrs: nounwind readnone
   declare i32 @llvm.amdgcn.workitem.id.x() #1
 
   declare { i1, i64 } @llvm.amdgcn.if(i1)
 
   declare void @llvm.amdgcn.end.cf(i64)
 
 
bb.2.end:
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(1)* undef`)
     S_ENDPGM
 
 ...
+---
+# A read from exec copy subreg prevents optimization
+# CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}}
+# CHECK: $sgpr0_sgpr1 = COPY $exec
+# CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1
+name:            if_and_xor_read_exec_copy_subreg
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$vgpr0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.main_body:
+    liveins: $vgpr0
+
+    $sgpr0_sgpr1 = COPY $exec
+    $sgpr4 = S_MOV_B32 $sgpr1
+    $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
+    $vgpr0 = V_MOV_B32_e32 4, implicit $exec
+    $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
+    $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
+    $exec = S_MOV_B64_term killed $sgpr2_sgpr3
+    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1.if:
+    liveins: $sgpr0_sgpr1
+
+    $sgpr7 = S_MOV_B32 61440
+    $sgpr6 = S_MOV_B32 -1
+    $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
+
+  bb.2.end:
+    liveins: $vgpr0, $sgpr0_sgpr1
+
+    $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
+    $sgpr3 = S_MOV_B32 61440
+    $sgpr2 = S_MOV_B32 -1
+    BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(1)* undef`)
+    S_ENDPGM
+...

test/CodeGen/ARM/deps-fix.ll

 ; RUN: llc < %s -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard -mtriple armv7-linux-gnueabi | FileCheck %s
 
 ;; This test checks that the ExecutionDomainFix pass performs the domain changes
 ;; even when some dependencies are propagated through implicit definitions.
 
 ; CHECK: fun_a
 define <4 x float> @fun_a(<4 x float> %in, <4 x float> %x, float %y) nounwind {
-; CHECK: vext
-; CHECK: vext
+; CHECK: vorr
 ; CHECK: vadd.f32
   %1 = insertelement <4 x float> %in, float %y, i32 0
   %2 = fadd <4 x float> %1, %x  
   ret <4 x float> %2
 }
 ; CHECK: fun_b
 define <4 x i32> @fun_b(<4 x i32> %in, <4 x i32> %x, i32 %y) nounwind {
 ; CHECK: vmov.32
 ; CHECK: vadd.i32
   %1 = insertelement <4 x i32> %in, i32 %y, i32 0
   %2 = add <4 x i32> %1, %x  
   ret <4 x i32> %2
 }

test/CodeGen/Mips/atomic64.ll

 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB0_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    daddu $3, $2, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB0_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB0_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadAdd:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB0_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    daddu $3, $2, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB0_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB0_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadAdd:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))

 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB1_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    dsubu $3, $2, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB1_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB1_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadSub:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB1_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    dsubu $3, $2, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB1_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB1_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadSub:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))

 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAnd)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB2_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    and $3, $2, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB2_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB2_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadAnd:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAnd)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB2_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    and $3, $2, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB2_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB2_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadAnd:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd)))

 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadOr)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB3_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    or $3, $2, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB3_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB3_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadOr:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadOr)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB3_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    or $3, $2, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB3_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB3_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadOr:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))

 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadXor)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB4_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    xor $3, $2, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB4_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB4_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadXor:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadXor)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadXor)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB4_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    xor $3, $2, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB4_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB4_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadXor:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadXor)))

 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB5_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    and $3, $2, $4
 ; MIPS64R6-NEXT:    nor $3, $zero, $3
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB5_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB5_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadNand:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB5_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    and $3, $2, $4
 ; MIPS64R6O0-NEXT:    nor $3, $zero, $3
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB5_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB5_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadNand:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand)))

 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap64)))
 ; MIPS64R6-NEXT:    sd $4, 8($sp)
 ; MIPS64R6-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6-NEXT:  .LBB6_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    move $3, $4
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB6_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB6_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    daddiu $sp, $sp, 16
 ;
 ; MIPS64R6O0-LABEL: AtomicSwap64:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap64)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap64)))
 ; MIPS64R6O0-NEXT:    move $25, $4
 ; MIPS64R6O0-NEXT:    sd $4, 8($sp)
 ; MIPS64R6O0-NEXT:    ld $4, 8($sp)
 ; MIPS64R6O0-NEXT:    ld $1, %got_disp(x)($1)
 ; MIPS64R6O0-NEXT:  .LBB6_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $2, 0($1)
 ; MIPS64R6O0-NEXT:    move $3, $4
 ; MIPS64R6O0-NEXT:    scd $3, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $3, .LBB6_1
+; MIPS64R6O0-NEXT:    beqc $3, $zero, .LBB6_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    sd $25, 0($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicSwap64:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    daddiu $sp, $sp, -16

 ; MIPS64R6-NEXT:  .LBB7_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6-NEXT:    lld $2, 0($1)
 ; MIPS64R6-NEXT:    bnec $2, $4, .LBB7_3
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
 ; MIPS64R6-NEXT:    # in Loop: Header=BB7_1 Depth=1
 ; MIPS64R6-NEXT:    move $3, $5
 ; MIPS64R6-NEXT:    scd $3, 0($1)
-; MIPS64R6-NEXT:    beqzc $3, .LBB7_1
+; MIPS64R6-NEXT:    beqc $3, $zero, .LBB7_1
 ; MIPS64R6-NEXT:    nop
 ; MIPS64R6-NEXT:  .LBB7_3: # %entry
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    daddiu $sp, $sp, 16
 ;
 ; MIPS64R6O0-LABEL: AtomicCmpSwap64:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -48

 ; MIPS64R6O0-NEXT:  .LBB7_1: # %entry
 ; MIPS64R6O0-NEXT:    # =>This Inner Loop Header: Depth=1
 ; MIPS64R6O0-NEXT:    lld $6, 0($1)
 ; MIPS64R6O0-NEXT:    bnec $6, $4, .LBB7_3
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    # in Loop: Header=BB7_1 Depth=1
 ; MIPS64R6O0-NEXT:    move $7, $5
 ; MIPS64R6O0-NEXT:    scd $7, 0($1)
-; MIPS64R6O0-NEXT:    beqzc $7, .LBB7_1
+; MIPS64R6O0-NEXT:    beqc $7, $zero, .LBB7_1
 ; MIPS64R6O0-NEXT:  .LBB7_3: # %entry
 ; MIPS64R6O0-NEXT:    sd $2, 24($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    move $2, $6
 ; MIPS64R6O0-NEXT:    sd $6, 32($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    sd $25, 16($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    sd $3, 8($sp) # 8-byte Folded Spill
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 48
 ; MIPS64R6O0-NEXT:    jrc $ra

test/CodeGen/Mips/compactbranches/compact-branches-64.ll

 
 ; Function Attrs: nounwind
 define void @l7() {
 entry:
 ; CHECK-LABEL: l7:
 ; CHECK: jalrc $25
   %call = tail call i64 @k()
   %cmp = icmp eq i64 %call, 0
-; CHECK: bnezc
+; CHECK: bnec
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; CHECK: jalrc $25
   tail call void @f(i64 signext 4)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
 ; CHECK: jrc  $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l8() {
 entry:
 ; CHECK-LABEL: l8:
 ; CHECK: jalrc $25
   %call = tail call i64 @k()
   %cmp = icmp eq i64 %call, 0
-; CHECK: beqzc
+; CHECK: beqc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
 ; CHECK: jalrc $25
   tail call void @f(i64 signext 5)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
 ; CHECK: jrc  $ra
   ret void
 }
 
 define i64 @l9(i8* ()* %i) {
 entry:
 ; CHECK-LABEL: l9:
   %i.addr = alloca i8* ()*, align 4
   store i8* ()* %i, i8* ()** %i.addr, align 4
 ; CHECK: jalrc $25
   %call = call i64 @k()
   %cmp = icmp ne i64 %call, 0
-; CHECK: beqzc
+; CHECK: beqc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %0 = load i8* ()*, i8* ()** %i.addr, align 4
 ; CHECK: jalrc $25
   %call1 = call i8* %0()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
 ; CHECK: jrc $ra
   ret i64 -1
 }