[PowerPC] Turn on CR-Logical reducer pass

[nemanjai]

Summary

Quite a while ago, we implemented a pass that will reduce the number of CR-logical operations we emit. It does so by converting a CR-logical operation into a branch. We have kept this off by default because it seemed to cause a significant regression with one benchmark.
However, that regression turned out to be due to a completely unrelated reason - AADB introducing a self-copy that is a priority-setting nop and it was just exacerbated by this pass.

Now that we understand the reason for the only degradation, we can turn this pass on by default. A subsequent patch will detect and remove self-copies in the pre-emit peephole.

[hfinkel]

Now that we understand the reason for the only degradation, we can turn this pass on by default. A subsequent patch will detect and remove self-copies in the pre-emit peephole.

SGTM.

[RKSimon]

@nemanjai This is breaking on EXPENSIVE_CHECKS buildbots - please can you take a look? http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20263/steps/test-check-all/logs/stdio

[nemanjai]

In D52431#1714255, @RKSimon wrote:

@nemanjai This is breaking on EXPENSIVE_CHECKS buildbots - please can you take a look? http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20263/steps/test-check-all/logs/stdio

Sorry about that. I'll have a look. I don't think it is the cause of the AMDGPU failures though.

[nemanjai]

In D52431#1714330, @nemanjai wrote:

In D52431#1714255, @RKSimon wrote:

@nemanjai This is breaking on EXPENSIVE_CHECKS buildbots - please can you take a look? http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20263/steps/test-check-all/logs/stdio

Sorry about that. I'll have a look. I don't think it is the cause of the AMDGPU failures though.

Turns out I cannot build with EXPENSIVE_CHECKS turned on with my setup on PPC Linux. I'll revert the change until I can get this sorted out.

[RKSimon]

In D52431#1714330, @nemanjai wrote:

In D52431#1714255, @RKSimon wrote:

@nemanjai This is breaking on EXPENSIVE_CHECKS buildbots - please can you take a look? http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20263/steps/test-check-all/logs/stdio

Sorry about that. I'll have a look. I don't think it is the cause of the AMDGPU failures though.

No, they were already a known problem: https://bugs.llvm.org/show_bug.cgi?id=43699

[nemanjai]

@RKSimon What are the chances I could get access to a machine where these issues can be reproduced? I have tried building with EXPENSIVE_CHECKS on PPC Linux, but that fails and I tried it on my MacBook but I am not seeing these failures with the patch applied.

OTOH, I see that on that bot, you build a debug build. I wonder if this failure only happens on debug builds with EXPENSIVE_CHECKS... I'll try that on my machine now.

[RKSimon]

@nemanjai Any luck on this? It seems to be something to do with PPCReduceCRLogicals::splitBlockOnBinaryCROp AllCRLogicalOps.push_back() calls, resulting in a reallocation and the original CRLogicalOpInfo &CRI reference being lost. Should/can the CRLogicalOpInfo& be passed by value instead?

[RKSimon]

This was reverted in rL375233

[nemanjai]

In D52431#1715629, @RKSimon wrote:

@nemanjai Any luck on this? It seems to be something to do with PPCReduceCRLogicals::splitBlockOnBinaryCROp AllCRLogicalOps.push_back() calls, resulting in a reallocation and the original CRLogicalOpInfo &CRI reference being lost. Should/can the CRLogicalOpInfo& be passed by value instead?

Ah, this makes perfect sense. Thanks Simon. I'll try to put together a reproducer and a fix.

[nemanjai]

A few updates to the CR Logical Reducer in addition to the pulled patch that turns it on:

• Do not use std::vector as there is no real reason for it
• Do not take references into a growable data structure :(

@RKSimon Simon, could you do me a big favour and try this out on the machine on which you saw the failures. I am not sure if this is the (only) issue but references into a growable data structure certainly should be removed. Thanks for spotting this issue - I don't know what I was thinking when I originally wrote this a long time ago.

[RKSimon]

In D52431#1715683, @nemanjai wrote:

A few updates to the CR Logical Reducer in addition to the pulled patch that turns it on:

• Do not use std::vector as there is no real reason for it
• Do not take references into a growable data structure :(

@RKSimon Simon, could you do me a big favour and try this out on the machine on which you saw the failures. I am not sure if this is the (only) issue but references into a growable data structure certainly should be removed. Thanks for spotting this issue - I don't know what I was thinking when I originally wrote this a long time ago.

I'll test it out but I'll be travelling to the devmtg so its not going to be until Monday at the earliest.

[RKSimon]

Thanks @nemanjai this no longer asserts/crashes on my windows build

[nemanjai]

In D52431#1716969, @RKSimon wrote:

Thanks @nemanjai this no longer asserts/crashes on my windows build

Thank you so much for all your help sorting this out Simon.

lib/Target/PowerPC/PPCReduceCRLogicals.cpp

 
 private:
   const PPCInstrInfo *TII;
   MachineFunction *MF;
   MachineRegisterInfo *MRI;
   const MachineBranchProbabilityInfo *MBPI;
 
   // A vector to contain all the CR logical operations
-  std::vector<CRLogicalOpInfo> AllCRLogicalOps;
+  SmallVector<CRLogicalOpInfo, 16> AllCRLogicalOps;
   void initialize(MachineFunction &MFParm);
   void collectCRLogicals();
-  bool handleCROp(CRLogicalOpInfo &CRI);
+  bool handleCROp(unsigned Idx);
   bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
   static bool isCRLogical(MachineInstr &MI) {
     unsigned Opc = MI.getOpcode();
     return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||
       Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV ||
       Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET ||
       Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET;
   }
   bool simplifyCode() {
     bool Changed = false;
     // Not using a range-based for loop here as the vector may grow while being
     // operated on.
     for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
-      Changed |= handleCROp(AllCRLogicalOps[i]);
+      Changed |= handleCROp(i);
     return Changed;
   }
 
 public:
   PPCReduceCRLogicals() : MachineFunctionPass(ID) {
     initializePPCReduceCRLogicalsPass(*PassRegistry::getPassRegistry());
   }
 
void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {
   AllCRLogicalOps.clear();
 }
 
 /// Contains all the implemented transformations on CR logical operations.
 /// For example, a binary CR logical can be used to split a block on its inputs,
 /// a unary CR logical might be used to change the condition code on a
 /// comparison feeding it. A nullary CR logical might simply be removable
 /// if the user of the bit it [un]sets can be transformed.
-bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) {
+bool PPCReduceCRLogicals::handleCROp(unsigned Idx) {
   // We can definitely split a block on the inputs to a binary CR operation
   // whose defs and (single) use are within the same block.
   bool Changed = false;
+  CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];
   if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&
       CRI.DefsSingleUse) {
     Changed = splitBlockOnBinaryCROp(CRI);
     if (Changed)
       NumBlocksSplitOnBinaryCROp++;
   }
   return Changed;
 }

lib/Target/PowerPC/PPCTargetMachine.cpp

 static cl::opt<bool>
 EnableMachineCombinerPass("ppc-machine-combiner",
                           cl::desc("Enable the machine combiner pass"),
                           cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
   ReduceCRLogical("ppc-reduce-cr-logicals",
                   cl::desc("Expand eligible cr-logical binary ops to branches"),
-                  cl::init(false), cl::Hidden);
+                  cl::init(true), cl::Hidden);
 extern "C" void LLVMInitializePowerPCTarget() {
   // Register the targets
   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
 #ifndef NDEBUG

test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

 ; CHECK-NEXT:    stw 4, 392(1)
 ; CHECK-NEXT:    stw 3, 400(1)
 ; CHECK-NEXT:    lwz 4, 388(1)
 ; CHECK-NEXT:    stw 4, 404(1)
 ; CHECK-NEXT:    bc 4, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb5
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 0
-; CHECK-NEXT:    b .LBB0_16
+; CHECK-NEXT:    b .LBB0_17
 ; CHECK-NEXT:  .LBB0_2: # %bb1
 ; CHECK-NEXT:    lfd 0, 400(1)
 ; CHECK-NEXT:    lis 3, 15856
 ; CHECK-NEXT:    stw 3, 336(1)
 ; CHECK-NEXT:    lfd 1, 392(1)
 ; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    stfd 0, 304(1)
 ; CHECK-NEXT:    stw 29, 340(1)

 ; CHECK-NEXT:    lfd 3, 256(1)
 ; CHECK-NEXT:    stw 3, 252(1)
 ; CHECK-NEXT:    lwz 3, 192(1)
 ; CHECK-NEXT:    stw 3, 248(1)
 ; CHECK-NEXT:    lfd 4, 248(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    stfd 2, 176(1)
 ; CHECK-NEXT:    stfd 1, 168(1)
-; CHECK-NEXT:    fcmpu 0, 2, 27
+; CHECK-NEXT:    fcmpu 1, 2, 27
 ; CHECK-NEXT:    lwz 3, 180(1)
-; CHECK-NEXT:    fcmpu 1, 1, 27
-; CHECK-NEXT:    crandc 20, 6, 0
-; CHECK-NEXT:    cror 21, 5, 7
+; CHECK-NEXT:    fcmpu 0, 1, 27
+; CHECK-NEXT:    crandc 20, 2, 4
 ; CHECK-NEXT:    stw 3, 268(1)
-; CHECK-NEXT:    cror 20, 21, 20
 ; CHECK-NEXT:    lwz 3, 176(1)
 ; CHECK-NEXT:    stw 3, 264(1)
 ; CHECK-NEXT:    lwz 3, 172(1)
 ; CHECK-NEXT:    lfd 30, 264(1)
 ; CHECK-NEXT:    stw 3, 276(1)
 ; CHECK-NEXT:    lwz 3, 168(1)
 ; CHECK-NEXT:    stw 3, 272(1)
 ; CHECK-NEXT:    lfd 31, 272(1)
-; CHECK-NEXT:    bc 12, 20, .LBB0_13
-; CHECK-NEXT:  # %bb.10: # %bb2
+; CHECK-NEXT:    bc 12, 20, .LBB0_14
+; CHECK-NEXT:  # %bb.10: # %bb1
+; CHECK-NEXT:    cror 20, 1, 3
+; CHECK-NEXT:    bc 12, 20, .LBB0_14
+; CHECK-NEXT:  # %bb.11: # %bb2
 ; CHECK-NEXT:    fneg 28, 31
 ; CHECK-NEXT:    stfd 28, 48(1)
 ; CHECK-NEXT:    lis 3, 16864
 ; CHECK-NEXT:    stw 3, 80(1)
 ; CHECK-NEXT:    fneg 29, 30
 ; CHECK-NEXT:    lwz 3, 52(1)
 ; CHECK-NEXT:    stfd 29, 40(1)
 ; CHECK-NEXT:    li 29, 0

 ; CHECK-NEXT:    fctiwz 2, 2
 ; CHECK-NEXT:    stfd 2, 24(1)
 ; CHECK-NEXT:    lwz 3, 36(1)
 ; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 4, 28(1)
 ; CHECK-NEXT:    crandc 20, 6, 1
 ; CHECK-NEXT:    cror 20, 4, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
-; CHECK-NEXT:    bc 12, 20, .LBB0_12
-; CHECK-NEXT:  # %bb.11: # %bb2
+; CHECK-NEXT:    bc 12, 20, .LBB0_13
+; CHECK-NEXT:  # %bb.12: # %bb2
 ; CHECK-NEXT:    ori 3, 4, 0
-; CHECK-NEXT:    b .LBB0_12
-; CHECK-NEXT:  .LBB0_12: # %bb2
+; CHECK-NEXT:    b .LBB0_13
+; CHECK-NEXT:  .LBB0_13: # %bb2
 ; CHECK-NEXT:    subfic 4, 3, 0
 ; CHECK-NEXT:    subfe 3, 29, 30
-; CHECK-NEXT:    b .LBB0_16
-; CHECK-NEXT:  .LBB0_13: # %bb3
+; CHECK-NEXT:    b .LBB0_17
+; CHECK-NEXT:  .LBB0_14: # %bb3
 ; CHECK-NEXT:    stfd 31, 112(1)
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    stw 3, 148(1)
 ; CHECK-NEXT:    stw 3, 140(1)
 ; CHECK-NEXT:    stw 3, 136(1)
 ; CHECK-NEXT:    stfd 30, 104(1)
 ; CHECK-NEXT:    lis 4, 16864
 ; CHECK-NEXT:    lwz 3, 116(1)

 ; CHECK-NEXT:    fctiwz 2, 2
 ; CHECK-NEXT:    stfd 2, 88(1)
 ; CHECK-NEXT:    lwz 3, 100(1)
 ; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 4, 92(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
-; CHECK-NEXT:    bc 12, 20, .LBB0_14
-; CHECK-NEXT:    b .LBB0_15
-; CHECK-NEXT:  .LBB0_14: # %bb3
-; CHECK-NEXT:    addi 4, 3, 0
+; CHECK-NEXT:    bc 12, 20, .LBB0_15
+; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_15: # %bb3
+; CHECK-NEXT:    addi 4, 3, 0
+; CHECK-NEXT:  .LBB0_16: # %bb3
 ; CHECK-NEXT:    mr 3, 30
-; CHECK-NEXT:  .LBB0_16: # %bb5
+; CHECK-NEXT:  .LBB0_17: # %bb5
 ; CHECK-NEXT:    lfd 31, 456(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    lfd 30, 448(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    lfd 29, 440(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    lfd 28, 432(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    lwz 12, 408(1)
 ; CHECK-NEXT:    lfd 27, 424(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    lwz 30, 416(1) # 4-byte Folded Reload
 ; CHECK-NEXT:    mtcrf 32, 12 # cr2

test/CodeGen/PowerPC/brcond.ll

-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -ppc-reduce-cr-logicals=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-reduce-cr-logicals=false < %s | FileCheck %s
 
 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
 ; CHECK-LABEL: testi32slt
 ; CHECK: crorc [[REG:[0-9]+]], 2, 6
 ; CHECK: bc 12, [[REG]], {{\.[a-zA-Z0-9_]+}}
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
   %cmp3tmp = icmp eq i32 %c1, %c2

test/CodeGen/PowerPC/pr42492.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
 
 define void @f(i8*, i8*, i64*) {
 ; Check we don't assert and this is not a Hardware Loop
 ; CHECK-LABEL: f:
-; CHECK:  .LBB0_2: #
-; CHECK-NEXT:    cmplwi
-; CHECK-NEXT:    cmpd
-; CHECK-NEXT:    sldi
-; CHECK-NEXT:    cror
-; CHECK-NEXT:    addi
-; CHECK-NEXT:    bc
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpld 3, 4
+; CHECK-NEXT:    beqlr 0
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    ld 6, 8(5)
+; CHECK-NEXT:    not 3, 3
+; CHECK-NEXT:    add 3, 3, 4
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_2: #
+; CHECK-NEXT:    sldi 6, 6, 4
+; CHECK-NEXT:    cmplwi 4, 14
+; CHECK-NEXT:    addi 7, 4, 1
+; CHECK-NEXT:    bc 12, 1, .LBB0_4
+; CHECK-NEXT:  # %bb.3: #
+; CHECK-NEXT:    cmpd 3, 4
+; CHECK-NEXT:    mr 4, 7
+; CHECK-NEXT:    bc 4, 2, .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    std 6, 8(5)
+; CHECK-NEXT:    blr
 
   %4 = icmp eq i8* %0, %1
   br i1 %4, label %9, label %5
 
 5:                                                ; preds = %3
   %6 = getelementptr inbounds i64, i64* %2, i64 1
   %7 = load i64, i64* %6, align 8
   br label %10

test/CodeGen/PowerPC/tocSaveInPrologue.ll

 ; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -64(r1)
 ; CHECK-NEXT:    mr r29, r5
-; CHECK-NEXT:    cmpwi cr1, r4, 11
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    extsw r28, r4
 ; CHECK-NEXT:    std r2, 24(r1)
 ; CHECK-NEXT:    cmpwi r29, 1
-; CHECK-NEXT:    cror 4*cr5+lt, lt, 4*cr1+lt
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
+; CHECK-NEXT:    bc 12, lt, .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    cmpwi cr0, r4, 11
+; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:    .p2align 5
-; CHECK-NEXT:  .LBB0_1: # %for.body.us
-; CHECK-NEXT:  # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:  .LBB0_2: # %for.body.us
+; CHECK-NEXT:    #
 ; CHECK-NEXT:    mtctr r30
 ; CHECK-NEXT:    mr r3, r28
 ; CHECK-NEXT:    mr r12, r30
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r29, r29, -1
 ; CHECK-NEXT:    cmplwi r29, 0
-; CHECK-NEXT:    bne cr0, .LBB0_1
-; CHECK-NEXT:  .LBB0_2: # %for.cond.cleanup
+; CHECK-NEXT:    bne cr0, .LBB0_2
+; CHECK-NEXT:  .LBB0_3: # %for.cond.cleanup
 ; CHECK-NEXT:    mtctr r30
 ; CHECK-NEXT:    mr r3, r28
 ; CHECK-NEXT:    mr r12, r30
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r1, r1, 64
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0

test/CodeGen/PowerPC/vec-min-max.ll

entry:
   %0 = fcmp fast ole <2 x double> %a, %b
   %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
   ret <2 x double> %1
 }
 
 define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
 ; CHECK-LABEL: invalidv1i128:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    mfvsrd 3, 36
 ; CHECK-NEXT:    xxswapd 0, 36
-; CHECK-NEXT:    mfvsrd 4, 36
-; CHECK-NEXT:    mfvsrd 5, 34
+; CHECK-NEXT:    mfvsrd 4, 34
+; CHECK-NEXT:    xxswapd 1, 34
+; CHECK-NEXT:    cmpld 4, 3
+; CHECK-NEXT:    cmpd 1, 4, 3
 ; CHECK-NEXT:    mfvsrd 3, 0
-; CHECK-NEXT:    xxswapd 0, 34
-; CHECK-NEXT:    cmpld 5, 4
-; CHECK-NEXT:    cmpd 1, 5, 4
 ; CHECK-NEXT:    crandc 20, 4, 2
-; CHECK-NEXT:    mfvsrd 6, 0
-; CHECK-NEXT:    cmpld 1, 6, 3
-; CHECK-NEXT:    crand 21, 2, 4
-; CHECK-NEXT:    cror 20, 21, 20
-; CHECK-NEXT:    bc 12, 20, .LBB12_2
+; CHECK-NEXT:    mfvsrd 4, 1
+; CHECK-NEXT:    cmpld 1, 4, 3
+; CHECK-NEXT:    bc 12, 20, .LBB12_3
 ; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    crand 20, 2, 4
+; CHECK-NEXT:    bc 12, 20, .LBB12_3
+; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    vmr 2, 4
-; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:  .LBB12_3:
 ; CHECK-NEXT:    xxswapd 0, 34
 ; CHECK-NEXT:    mfvsrd 4, 34
 ; CHECK-NEXT:    mfvsrd 3, 0
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: invalidv1i128:
 ; NOP8VEC:       # %bb.0:
 ; NOP8VEC-NEXT:    cmpld 4, 8