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nemanjainemanjai
committedOct 22, 2019
[PowerPC] Turn on CR-Logical reducer pass
This re-commits r375152 which was pulled in r375233 because it broke the EXPENSIVE_CHECKS bot on Windows. The reason for the failure was a bug in the pass that the commit turned on by default. This patch fixes that bug and turns the pass back on. This patch has been verified on the buildbot that originally failed thanks to Simon Pilgrim. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375497
·
llvmorg-21-initllvmorg-10.0.0-rc1
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-50
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‎llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

+5-4
Original file line numberDiff line numberDiff line change
@@ -381,10 +381,10 @@ class PPCReduceCRLogicals : public MachineFunctionPass {
381381
const MachineBranchProbabilityInfo *MBPI;
382382

383383
// A vector to contain all the CR logical operations
384-
std::vector<CRLogicalOpInfo> AllCRLogicalOps;
384+
SmallVector<CRLogicalOpInfo, 16> AllCRLogicalOps;
385385
void initialize(MachineFunction &MFParm);
386386
void collectCRLogicals();
387-
bool handleCROp(CRLogicalOpInfo &CRI);
387+
bool handleCROp(unsigned Idx);
388388
bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
389389
static bool isCRLogical(MachineInstr &MI) {
390390
unsigned Opc = MI.getOpcode();
@@ -398,7 +398,7 @@ class PPCReduceCRLogicals : public MachineFunctionPass {
398398
// Not using a range-based for loop here as the vector may grow while being
399399
// operated on.
400400
for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
401-
Changed |= handleCROp(AllCRLogicalOps[i]);
401+
Changed |= handleCROp(i);
402402
return Changed;
403403
}
404404

@@ -578,10 +578,11 @@ void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {
578578
/// a unary CR logical might be used to change the condition code on a
579579
/// comparison feeding it. A nullary CR logical might simply be removable
580580
/// if the user of the bit it [un]sets can be transformed.
581-
bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) {
581+
bool PPCReduceCRLogicals::handleCROp(unsigned Idx) {
582582
// We can definitely split a block on the inputs to a binary CR operation
583583
// whose defs and (single) use are within the same block.
584584
bool Changed = false;
585+
CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];
585586
if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&
586587
CRI.DefsSingleUse) {
587588
Changed = splitBlockOnBinaryCROp(CRI);

‎llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ EnableMachineCombinerPass("ppc-machine-combiner",
9393
static cl::opt<bool>
9494
ReduceCRLogical("ppc-reduce-cr-logicals",
9595
cl::desc("Expand eligible cr-logical binary ops to branches"),
96-
cl::init(false), cl::Hidden);
96+
cl::init(true), cl::Hidden);
9797
extern "C" void LLVMInitializePowerPCTarget() {
9898
// Register the targets
9999
RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());

‎llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

+20-19
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
3636
; CHECK-NEXT: # %bb.1: # %bb5
3737
; CHECK-NEXT: li 3, 0
3838
; CHECK-NEXT: li 4, 0
39-
; CHECK-NEXT: b .LBB0_16
39+
; CHECK-NEXT: b .LBB0_17
4040
; CHECK-NEXT: .LBB0_2: # %bb1
4141
; CHECK-NEXT: lfd 0, 400(1)
4242
; CHECK-NEXT: lis 3, 15856
@@ -166,13 +166,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
166166
; CHECK-NEXT: bl __gcc_qsub@PLT
167167
; CHECK-NEXT: stfd 2, 176(1)
168168
; CHECK-NEXT: stfd 1, 168(1)
169-
; CHECK-NEXT: fcmpu 0, 2, 27
169+
; CHECK-NEXT: fcmpu 1, 2, 27
170170
; CHECK-NEXT: lwz 3, 180(1)
171-
; CHECK-NEXT: fcmpu 1, 1, 27
172-
; CHECK-NEXT: crandc 20, 6, 0
173-
; CHECK-NEXT: cror 21, 5, 7
171+
; CHECK-NEXT: fcmpu 0, 1, 27
172+
; CHECK-NEXT: crandc 20, 2, 4
174173
; CHECK-NEXT: stw 3, 268(1)
175-
; CHECK-NEXT: cror 20, 21, 20
176174
; CHECK-NEXT: lwz 3, 176(1)
177175
; CHECK-NEXT: stw 3, 264(1)
178176
; CHECK-NEXT: lwz 3, 172(1)
@@ -181,8 +179,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
181179
; CHECK-NEXT: lwz 3, 168(1)
182180
; CHECK-NEXT: stw 3, 272(1)
183181
; CHECK-NEXT: lfd 31, 272(1)
184-
; CHECK-NEXT: bc 12, 20, .LBB0_13
185-
; CHECK-NEXT: # %bb.10: # %bb2
182+
; CHECK-NEXT: bc 12, 20, .LBB0_14
183+
; CHECK-NEXT: # %bb.10: # %bb1
184+
; CHECK-NEXT: cror 20, 1, 3
185+
; CHECK-NEXT: bc 12, 20, .LBB0_14
186+
; CHECK-NEXT: # %bb.11: # %bb2
186187
; CHECK-NEXT: fneg 28, 31
187188
; CHECK-NEXT: stfd 28, 48(1)
188189
; CHECK-NEXT: lis 3, 16864
@@ -231,15 +232,15 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
231232
; CHECK-NEXT: crandc 20, 6, 1
232233
; CHECK-NEXT: cror 20, 4, 20
233234
; CHECK-NEXT: addis 3, 3, -32768
234-
; CHECK-NEXT: bc 12, 20, .LBB0_12
235-
; CHECK-NEXT: # %bb.11: # %bb2
235+
; CHECK-NEXT: bc 12, 20, .LBB0_13
236+
; CHECK-NEXT: # %bb.12: # %bb2
236237
; CHECK-NEXT: ori 3, 4, 0
237-
; CHECK-NEXT: b .LBB0_12
238-
; CHECK-NEXT: .LBB0_12: # %bb2
238+
; CHECK-NEXT: b .LBB0_13
239+
; CHECK-NEXT: .LBB0_13: # %bb2
239240
; CHECK-NEXT: subfic 4, 3, 0
240241
; CHECK-NEXT: subfe 3, 29, 30
241-
; CHECK-NEXT: b .LBB0_16
242-
; CHECK-NEXT: .LBB0_13: # %bb3
242+
; CHECK-NEXT: b .LBB0_17
243+
; CHECK-NEXT: .LBB0_14: # %bb3
243244
; CHECK-NEXT: stfd 31, 112(1)
244245
; CHECK-NEXT: li 3, 0
245246
; CHECK-NEXT: stw 3, 148(1)
@@ -286,13 +287,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
286287
; CHECK-NEXT: crandc 20, 6, 0
287288
; CHECK-NEXT: cror 20, 5, 20
288289
; CHECK-NEXT: addis 3, 3, -32768
289-
; CHECK-NEXT: bc 12, 20, .LBB0_14
290-
; CHECK-NEXT: b .LBB0_15
291-
; CHECK-NEXT: .LBB0_14: # %bb3
292-
; CHECK-NEXT: addi 4, 3, 0
290+
; CHECK-NEXT: bc 12, 20, .LBB0_15
291+
; CHECK-NEXT: b .LBB0_16
293292
; CHECK-NEXT: .LBB0_15: # %bb3
293+
; CHECK-NEXT: addi 4, 3, 0
294+
; CHECK-NEXT: .LBB0_16: # %bb3
294295
; CHECK-NEXT: mr 3, 30
295-
; CHECK-NEXT: .LBB0_16: # %bb5
296+
; CHECK-NEXT: .LBB0_17: # %bb5
296297
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
297298
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
298299
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload

‎llvm/test/CodeGen/PowerPC/brcond.ll

+4-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
1-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
2-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
1+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
2+
; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
3+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
4+
; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s
35

46
define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
57
; CHECK-LABEL: testi32slt

‎llvm/test/CodeGen/PowerPC/pr42492.ll

+8-6
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,15 @@ define void @f(i8*, i8*, i64*) {
1414
; CHECK-NEXT: li 4, 0
1515
; CHECK-NEXT: .p2align 5
1616
; CHECK-NEXT: .LBB0_2: #
17-
; CHECK-NEXT: cmplwi 4, 14
18-
; CHECK-NEXT: cmpd 1, 3, 4
1917
; CHECK-NEXT: sldi 6, 6, 4
20-
; CHECK-NEXT: cror 20, 6, 1
21-
; CHECK-NEXT: addi 4, 4, 1
22-
; CHECK-NEXT: bc 4, 20, .LBB0_2
23-
; CHECK-NEXT: # %bb.3:
18+
; CHECK-NEXT: cmplwi 4, 14
19+
; CHECK-NEXT: addi 7, 4, 1
20+
; CHECK-NEXT: bc 12, 1, .LBB0_4
21+
; CHECK-NEXT: # %bb.3: #
22+
; CHECK-NEXT: cmpd 3, 4
23+
; CHECK-NEXT: mr 4, 7
24+
; CHECK-NEXT: bc 4, 2, .LBB0_2
25+
; CHECK-NEXT: .LBB0_4:
2426
; CHECK-NEXT: std 6, 8(5)
2527
; CHECK-NEXT: blr
2628

‎llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll

+8-7
Original file line numberDiff line numberDiff line change
@@ -16,25 +16,26 @@ define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 sig
1616
; CHECK-NEXT: std r0, 16(r1)
1717
; CHECK-NEXT: stdu r1, -64(r1)
1818
; CHECK-NEXT: mr r29, r5
19-
; CHECK-NEXT: cmpwi cr1, r4, 11
2019
; CHECK-NEXT: mr r30, r3
2120
; CHECK-NEXT: extsw r28, r4
2221
; CHECK-NEXT: std r2, 24(r1)
2322
; CHECK-NEXT: cmpwi r29, 1
24-
; CHECK-NEXT: cror 4*cr5+lt, lt, 4*cr1+lt
25-
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2
23+
; CHECK-NEXT: bc 12, lt, .LBB0_3
24+
; CHECK-NEXT: # %bb.1: # %entry
25+
; CHECK-NEXT: cmpwi cr0, r4, 11
26+
; CHECK-NEXT: bc 12, lt, .LBB0_3
2627
; CHECK-NEXT: .p2align 5
27-
; CHECK-NEXT: .LBB0_1: # %for.body.us
28-
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
28+
; CHECK-NEXT: .LBB0_2: # %for.body.us
29+
; CHECK-NEXT: #
2930
; CHECK-NEXT: mtctr r30
3031
; CHECK-NEXT: mr r3, r28
3132
; CHECK-NEXT: mr r12, r30
3233
; CHECK-NEXT: bctrl
3334
; CHECK-NEXT: ld 2, 24(r1)
3435
; CHECK-NEXT: addi r29, r29, -1
3536
; CHECK-NEXT: cmplwi r29, 0
36-
; CHECK-NEXT: bne cr0, .LBB0_1
37-
; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup
37+
; CHECK-NEXT: bne cr0, .LBB0_2
38+
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
3839
; CHECK-NEXT: mtctr r30
3940
; CHECK-NEXT: mr r3, r28
4041
; CHECK-NEXT: mr r12, r30

‎llvm/test/CodeGen/PowerPC/vec-min-max.ll

+12-11
Original file line numberDiff line numberDiff line change
@@ -240,22 +240,23 @@ entry:
240240
define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
241241
; CHECK-LABEL: invalidv1i128:
242242
; CHECK: # %bb.0:
243+
; CHECK-NEXT: mfvsrd 3, 36
243244
; CHECK-NEXT: xxswapd 0, 36
244-
; CHECK-NEXT: mfvsrd 4, 36
245-
; CHECK-NEXT: mfvsrd 5, 34
245+
; CHECK-NEXT: mfvsrd 4, 34
246+
; CHECK-NEXT: xxswapd 1, 34
247+
; CHECK-NEXT: cmpld 4, 3
248+
; CHECK-NEXT: cmpd 1, 4, 3
246249
; CHECK-NEXT: mfvsrd 3, 0
247-
; CHECK-NEXT: xxswapd 0, 34
248-
; CHECK-NEXT: cmpld 5, 4
249-
; CHECK-NEXT: cmpd 1, 5, 4
250250
; CHECK-NEXT: crandc 20, 4, 2
251-
; CHECK-NEXT: mfvsrd 6, 0
252-
; CHECK-NEXT: cmpld 1, 6, 3
253-
; CHECK-NEXT: crand 21, 2, 4
254-
; CHECK-NEXT: cror 20, 21, 20
255-
; CHECK-NEXT: bc 12, 20, .LBB12_2
251+
; CHECK-NEXT: mfvsrd 4, 1
252+
; CHECK-NEXT: cmpld 1, 4, 3
253+
; CHECK-NEXT: bc 12, 20, .LBB12_3
256254
; CHECK-NEXT: # %bb.1:
255+
; CHECK-NEXT: crand 20, 2, 4
256+
; CHECK-NEXT: bc 12, 20, .LBB12_3
257+
; CHECK-NEXT: # %bb.2:
257258
; CHECK-NEXT: vmr 2, 4
258-
; CHECK-NEXT: .LBB12_2:
259+
; CHECK-NEXT: .LBB12_3:
259260
; CHECK-NEXT: xxswapd 0, 34
260261
; CHECK-NEXT: mfvsrd 4, 34
261262
; CHECK-NEXT: mfvsrd 3, 0

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