[GISel][NFC]: Make MachineIRBuilder fully stateless

[aditya_nandakumar]

Summary

Completely separate out MachineIRBuilderState from MachineIRBuilder as it makes it possible to use different kinds of builders (ConstantFolding/CSEing) by just passing the State.
This makes it inconvenient by 1 extra line to define a builder - for eg

MachineIRBuilderState State;
MachineIRBuilder B(State);
AnyOtherBuilder AOB(State);

Also instead of passing in MachineIRBuilder everywhere - pass in the state - this allows for the target/hook to be explicit about what they expect the builder to do.

[qcolombet]

Hi Aditya,

this allows for the target/hook to be explicit about what they expect the builder to do.

What do you mean by that?

Put differently, is there any example of that in that patch?

Cheers,
-Quentin

[aemerson]

Looks ok, if a bit cumbersome with the additional state (do we need to hold references to it?). I'd like to see how this state is used with the CSE builder first though.

[aditya_nandakumar]

In D52131#1236994, @qcolombet wrote:

Hi Aditya,

this allows for the target/hook to be explicit about what they expect the builder to do.

What do you mean by that?

When there are many kinds of MachineIRBuilders the question always comes out to what the default should be. Instead of picking a default (which most of the time targets won't change) - now various hooks/customlegalization methods will need to decide what kind of builder they need (Say CSE vs ConstantFolding vs Basic). With this, we only pass in the State, and the method/function will explicitly pick a builder.
Additionally I ran into a bug for the following code sequence.

bool legalizeCustom(MachineIRBuilder &B) {
  ConstantFoldingBuilder CB(B.getState());
  CB.setInsertionPoint(SomeMI); // Sets the insertion point only for the CB's copy of the State/insertion point.
  if (someCondition)
     return someLegalizerHelper(B); // Pass B to a helper - but B's copy of the state has still no MBB/Insertion point set - only CB's copy was updated.
  else
     // Build using CB.
}

In the above code someLegalizerHelper had assumed that the insertion point will always be set before it was called - but in this case it was not.
Instead the following code sequence would not have the above bug.

bool legalizeCustom(MachineIRBuilderState &State) {
  ConstantFoldingBuilder CB(State);
  CB.setInsertionPoint(SomeMI);  // Changing the state that was passed in.
  if (someCondition)
    return someLegalizerHelper(State); // Insertion point is still reflected in State.
  // Build with CB.
}

Put differently, is there any example of that in that patch?

Cheers,
-Quentin

[aditya_nandakumar]

In D52131#1236995, @aemerson wrote:

Looks ok, if a bit cumbersome with the additional state (do we need to hold references to it?). I'd like to see how this state is used with the CSE builder first though.

I'm in the process of reworking parts of the CSEBuilder - I'll try to have a patch in a few days. It would look something like this unit test

void someFoo(MachineIRBuilderState &State) {
  CSEMIRBuilder CSEB(State);
  CSEB.setInsertionPoint(SomeMI);
  auto A = CSEB.buildConstant(s32, 42);
  auto B = CSEB.buildConstant(s32, 42);
  assert(A == B);
  MachineIRBuilder B(State);
  auto C = B.buildConstant(s32, 42);
  assert(C != A);
  unsigned NewReg = MRI.createGenericVReg(s32);
  auto Copy = CSEB.buildConstant(NewReg, 42);
  assert(Copy->getOpcode() == COPY);
  assert (Source of Copy == A);
}

As of now the State has a CSEInfo object which has info about what instructions are available in the CSEMap and will use them if available instead of creating a new vreg + new inst or materialize a copy if a specific destreg is passed in.

[aemerson]

Abandon?

include/llvm/CodeGen/GlobalISel/Combiner.h

public:
 
   bool combineMachineInstrs(MachineFunction &MF);
 
 protected:
   CombinerInfo &CInfo;
 
   MachineRegisterInfo *MRI = nullptr;
   const TargetPassConfig *TPC;
-  MachineIRBuilder Builder;
+  MachineIRBuilderState BuilderState;
 };
 
 } // End namespace llvm.
 
 #endif // LLVM_CODEGEN_GLOBALISEL_GICOMBINER_H

include/llvm/CodeGen/GlobalISel/IRTranslator.h

private:
   }
 
   /// @}
 
   // Builder for machine instruction a la IRBuilder.
   // I.e., compared to regular MIBuilder, this one also inserts the instruction
   // in the current block, it can creates block, etc., basically a kind of
   // IRBuilder, but for Machine IR.
+  MachineIRBuilderState CurBuilderState;
   MachineIRBuilder CurBuilder;
 
   // Builder set to the entry block (just after ABI lowering instructions). Used
   // as a convenient location for Constants.
+  MachineIRBuilderState EntryBuilderState;
   MachineIRBuilder EntryBuilder;
 
   // The MachineFunction currently being translated.
   MachineFunction *MF;
 
   /// MachineRegisterInfo used to create virtual registers.
   MachineRegisterInfo *MRI = nullptr;
 

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "legalizer"
 
 namespace llvm {
 class LegalizationArtifactCombiner {
-  MachineIRBuilder &Builder;
+  MachineIRBuilder Builder;
   MachineRegisterInfo &MRI;
   const LegalizerInfo &LI;
 
 public:
-  LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+  LegalizationArtifactCombiner(MachineIRBuilderState &State,
+                               MachineRegisterInfo &MRI,
                                const LegalizerInfo &LI)
-      : Builder(B), MRI(MRI), LI(LI) {}
+      : Builder(State), MRI(MRI), LI(LI) {}
 
   bool tryCombineAnyExt(MachineInstr &MI,
                         SmallVectorImpl<MachineInstr *> &DeadInsts) {
     if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
       return false;
     if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
                                            MI.getOperand(1).getReg(), MRI)) {
       LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

public:
 
   /// Legalize a vector instruction by increasing the number of vector elements
   /// involved and ignoring the added elements later.
   LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
                                     LLT WideTy);
 
   /// Expose MIRBuilder so clients can set their own RecordInsertInstruction
   /// functions
+  MachineIRBuilderState MIRBuilderState;
   MachineIRBuilder MIRBuilder;
 
   /// Expose LegalizerInfo so the clients can re-use.
   const LegalizerInfo &getLegalizerInfo() const { return LI; }
 
 private:
   /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
   /// Use by extending the operand's type to \p WideTy using the specified \p

include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

 #include <unordered_map>
 #include <utility>
 
 namespace llvm {
 
 extern cl::opt<bool> DisableGISelLegalityCheck;
 
 class MachineInstr;
-class MachineIRBuilder;
+struct MachineIRBuilderState;
 class MachineRegisterInfo;
 class MCInstrInfo;
 
 namespace LegalizeActions {
 enum LegalizeAction : std::uint8_t {
   /// The operation is expected to be selectable directly by the target, and
   /// no transformation is necessary.
   Legal,
public:
   /// instruction.
   ///
   /// \returns a description of the next legalization step to perform.
   LegalizeActionStep getAction(const MachineInstr &MI,
                                const MachineRegisterInfo &MRI) const;
 
   bool isLegal(const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 
-  virtual bool legalizeCustom(MachineInstr &MI,
-                              MachineRegisterInfo &MRI,
-                              MachineIRBuilder &MIRBuilder) const;
+  virtual bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
+                              MachineIRBuilderState &MIRBuilderState) const;
 
 private:
   /// Determine what action should be taken to legalize the given generic
   /// instruction opcode, type-index and type. Requires computeTables to have
   /// been called.
   ///
   /// \returns a pair consisting of the kind of legalization that should be
   /// performed and the destination type.

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

struct MachineIRBuilderState {
 
   /// \name Fields describing the insertion point.
   /// @{
   MachineBasicBlock *MBB;
   MachineBasicBlock::iterator II;
   /// @}
 
   std::function<void(MachineInstr *)> InsertedInstr;
+
+  void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
+  void stopRecordingInsertions();
+
+  void setMF(MachineFunction &MF);
+  void setMBB(MachineBasicBlock &MBB);
+  void setInstr(MachineInstr &MI);
 };
 
 /// Helper class to build MachineInstr.
 /// It keeps internally the insertion point and debug location for all
 /// the new instructions we want to create.
 /// This information can be modify via the related setters.
 class MachineIRBuilderBase {
 
-  MachineIRBuilderState State;
+  MachineIRBuilderState &State;
   const TargetInstrInfo &getTII() {
     assert(State.TII && "TargetInstrInfo is not set");
     return *State.TII;
   }
 
   void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
 
 protected:
protected:
   unsigned getRegFromArg(const MachineInstrBuilder &MIB) {
     return MIB->getOperand(0).getReg();
   }
 
   void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
 
 public:
   /// Some constructors for easy use.
-  MachineIRBuilderBase() = default;
-  MachineIRBuilderBase(MachineFunction &MF) { setMF(MF); }
-  MachineIRBuilderBase(MachineInstr &MI) : MachineIRBuilderBase(*MI.getMF()) {
+  MachineIRBuilderBase() = delete;
+  MachineIRBuilderBase(MachineFunction &MF, MachineIRBuilderState &State)
+      : State(State) {
+    setMF(MF);
+  }
+  MachineIRBuilderBase(MachineInstr &MI, MachineIRBuilderState &State)
+      : MachineIRBuilderBase(*MI.getMF(), State) {
     setInstr(MI);
   }
 
-  MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
+  MachineIRBuilderBase(MachineIRBuilderState &BState) : State(BState) {}
 
   /// Getter for the function we currently build.
   MachineFunction &getMF() {
     assert(State.MF && "MachineFunction is not set");
     return *State.MF;
   }
 
   /// Getter for DebugLoc
public:
   /// \pre MBB must be in getMF().
   /// \pre II must be a valid iterator in MBB.
   void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
   /// @}
 
   /// \name Setters for the insertion point.
   /// @{
   /// Set the MachineFunction where to build instructions.
-  void setMF(MachineFunction &);
+  void setMF(MachineFunction &MF) { State.setMF(MF); }
 
   /// Set the insertion point to the  end of \p MBB.
   /// \pre \p MBB must be contained by getMF().
-  void setMBB(MachineBasicBlock &MBB);
+  void setMBB(MachineBasicBlock &MBB) { State.setMBB(MBB); };
 
   /// Set the insertion point to before MI.
   /// \pre MI must be in getMF().
-  void setInstr(MachineInstr &MI);
+  void setInstr(MachineInstr &MI) { State.setInstr(MI); }
   /// @}
 
   /// \name Control where instructions we create are recorded (typically for
   /// visiting again later during legalization).
   /// @{
   void recordInsertion(MachineInstr *InsertedInstr) const;
   void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
   void stopRecordingInsertions();

include/llvm/CodeGen/GlobalISel/RegBankSelect.h

private:
   /// Get the frequency of the edges.
   /// This is required for non-fast mode.
   MachineBranchProbabilityInfo *MBPI = nullptr;
 
   /// Current optimization remark emitter. Used to report failures.
   std::unique_ptr<MachineOptimizationRemarkEmitter> MORE;
 
   /// Helper class used for every code morphing.
+  MachineIRBuilderState MIRBuilderState;
   MachineIRBuilder MIRBuilder;
 
   /// Optimization mode of the pass.
   Mode OptMode;
 
   /// Current target configuration. Controls how the pass handles errors.
   const TargetPassConfig *TPC;
 

lib/CodeGen/GlobalISel/Combiner.cpp

 bool Combiner::combineMachineInstrs(MachineFunction &MF) {
   // If the ISel pipeline failed, do not bother running this pass.
   // FIXME: Should this be here or in individual combiner passes.
   if (MF.getProperties().hasProperty(
           MachineFunctionProperties::Property::FailedISel))
     return false;
 
   MRI = &MF.getRegInfo();
+  MachineIRBuilder Builder(BuilderState);
   Builder.setMF(MF);
 
   LLVM_DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n');
 
   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
 
   bool MFChanged = false;
   bool Changed;

lib/CodeGen/GlobalISel/IRTranslator.cpp

if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
     R << (" (in function: " + MF.getName() + ")").str();
 
   if (TPC.isGlobalISelAbortEnabled())
     report_fatal_error(R.getMsg());
   else
     ORE.emit(R);
 }
 
-IRTranslator::IRTranslator() : MachineFunctionPass(ID) {
+IRTranslator::IRTranslator()
+    : MachineFunctionPass(ID), CurBuilder(CurBuilderState),
+      EntryBuilder(EntryBuilderState) {
   initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
 }
 
 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<StackProtector>();
   AU.addRequired<TargetPassConfig>();
   getSelectionDAGFallbackAnalysisUsage(AU);
   MachineFunctionPass::getAnalysisUsage(AU);
void IRTranslator::finalizeFunction() {
   // needed during the translation.
   PendingPHIs.clear();
   VMap.reset();
   FrameIndices.clear();
   MachinePreds.clear();
   // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
   // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
   // destroying it twice (in ~IRTranslator() and ~LLVMContext())
-  EntryBuilder = MachineIRBuilder();
-  CurBuilder = MachineIRBuilder();
+  EntryBuilderState = MachineIRBuilderState();
+  CurBuilderState = MachineIRBuilderState();
 }
 
 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
   MF = &CurMF;
   const Function &F = MF->getFunction();
   if (F.empty())
     return false;
   CLI = MF->getSubtarget().getCallLowering();

lib/CodeGen/GlobalISel/Legalizer.cpp

for (MachineInstr &MI : *MBB) {
       if (!isPreISelGenericOpcode(MI.getOpcode()))
         continue;
       if (isArtifact(MI))
         ArtifactList.insert(&MI);
       else
         InstList.insert(&MI);
     }
   }
-  Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
+  Helper.MIRBuilderState.recordInsertions([&](MachineInstr *MI) {
     // Only legalize pre-isel generic instructions.
     // Legalization process could generate Target specific pseudo
     // instructions with generic types. Don't record them
     if (isPreISelGenericOpcode(MI->getOpcode())) {
       if (isArtifact(*MI))
         ArtifactList.insert(MI);
       else
         InstList.insert(MI);
     }
     LLVM_DEBUG(dbgs() << ".. .. New MI: " << *MI;);
   });
   const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
-  LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo);
+  LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilderState,
+                                           MF.getRegInfo(), LInfo);
   auto RemoveDeadInstFromLists = [&InstList,
                                   &ArtifactList](MachineInstr *DeadMI) {
     InstList.remove(DeadMI);
     ArtifactList.remove(DeadMI);
   };
   bool Changed = false;
   do {
     while (!InstList.empty()) {
       MachineInstr &MI = *InstList.pop_back_val();
       assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
       if (isTriviallyDead(MI, MRI)) {
         LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
         MI.eraseFromParentAndMarkDBGValuesForRemoval();
         continue;
       }
 
       // Do the legalization for this instruction.
       auto Res = Helper.legalizeInstrStep(MI);
       // Error out if we couldn't legalize this instruction. We may want to
       // fall back to DAG ISel instead in the future.
       if (Res == LegalizerHelper::UnableToLegalize) {
-        Helper.MIRBuilder.stopRecordingInsertions();
+        Helper.MIRBuilderState.stopRecordingInsertions();
         reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
                            "unable to legalize instruction", MI);
         return false;
       }
       Changed |= Res == LegalizerHelper::Legalized;
     }
     while (!ArtifactList.empty()) {
       MachineInstr &MI = *ArtifactList.pop_back_val();

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "legalizer"
 
 using namespace llvm;
 using namespace LegalizeActions;
 
 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
-    : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
-  MIRBuilder.setMF(MF);
+    : MIRBuilder(MIRBuilderState), MRI(MF.getRegInfo()),
+      LI(*MF.getSubtarget().getLegalizerInfo()) {
+  MIRBuilderState.setMF(MF);
 }
 
 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI)
-    : MRI(MF.getRegInfo()), LI(LI) {
-  MIRBuilder.setMF(MF);
+    : MIRBuilder(MIRBuilderState), MRI(MF.getRegInfo()), LI(LI) {
+  MIRBuilderState.setMF(MF);
 }
 LegalizerHelper::LegalizeResult
 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
 
   auto Step = LI.getAction(MI, MRI);
   switch (Step.Action) {
   case Legal:
LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
   case Lower:
     LLVM_DEBUG(dbgs() << ".. Lower\n");
     return lower(MI, Step.TypeIdx, Step.NewType);
   case FewerElements:
     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
   case Custom:
     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
-    return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
+    return LI.legalizeCustom(MI, MRI, MIRBuilderState) ? Legalized
                                                        : UnableToLegalize;
   default:
     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
     return UnableToLegalize;
   }
 }
 
 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
                                    SmallVectorImpl<unsigned> &VRegs) {

lib/CodeGen/GlobalISel/LegalizerInfo.cpp

LegalizerInfo::getAction(const MachineInstr &MI,
   return getAction({MI.getOpcode(), Types, MemDescrs});
 }
 
 bool LegalizerInfo::isLegal(const MachineInstr &MI,
                             const MachineRegisterInfo &MRI) const {
   return getAction(MI, MRI).Action == Legal;
 }
 
-bool LegalizerInfo::legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
-                                   MachineIRBuilder &MIRBuilder) const {
+bool LegalizerInfo::legalizeCustom(
+    MachineInstr &MI, MachineRegisterInfo &MRI,
+    MachineIRBuilderState &MIRBuilderState) const {
   return false;
 }
 
 LegalizerInfo::SizeAndActionsVec
 LegalizerInfo::increaseToLargerTypesAndDecreaseToLargest(
     const SizeAndActionsVec &v, LegalizeAction IncreaseAction,
     LegalizeAction DecreaseAction) {
   SizeAndActionsVec result;

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugInfo.h"
 
 using namespace llvm;
 
-void MachineIRBuilderBase::setMF(MachineFunction &MF) {
-  State.MF = &MF;
-  State.MBB = nullptr;
-  State.MRI = &MF.getRegInfo();
-  State.TII = MF.getSubtarget().getInstrInfo();
-  State.DL = DebugLoc();
-  State.II = MachineBasicBlock::iterator();
-  State.InsertedInstr = nullptr;
-}
-
-void MachineIRBuilderBase::setMBB(MachineBasicBlock &MBB) {
-  State.MBB = &MBB;
-  State.II = MBB.end();
-  assert(&getMF() == MBB.getParent() &&
-         "Basic block is in a different function");
+void MachineIRBuilderState::setMF(MachineFunction &MF) {
+  this->MF = &MF;
+  MBB = nullptr;
+  MRI = &MF.getRegInfo();
+  TII = MF.getSubtarget().getInstrInfo();
+  DL = DebugLoc();
+  II = MachineBasicBlock::iterator();
+  InsertedInstr = nullptr;
+}
+
+void MachineIRBuilderState::setMBB(MachineBasicBlock &MBB) {
+  this->MBB = &MBB;
+  II = MBB.end();
+  assert(MF == MBB.getParent() && "Basic block is in a different function");
 }
 
-void MachineIRBuilderBase::setInstr(MachineInstr &MI) {
+void MachineIRBuilderState::setInstr(MachineInstr &MI) {
   assert(MI.getParent() && "Instruction is not part of a basic block");
   setMBB(*MI.getParent());
-  State.II = MI.getIterator();
+  II = MI.getIterator();
 }
 
 void MachineIRBuilderBase::setInsertPt(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator II) {
   assert(MBB.getParent() == &getMF() &&
          "Basic block is in a different function");
   State.MBB = &MBB;
   State.II = II;
 }
 
 void MachineIRBuilderBase::recordInsertion(MachineInstr *InsertedInstr) const {
   if (State.InsertedInstr)
     State.InsertedInstr(InsertedInstr);
 }
 
+void MachineIRBuilderState::recordInsertions(
+    std::function<void(MachineInstr *)> Inserted) {
+  InsertedInstr = std::move(Inserted);
+}
+
+void MachineIRBuilderState::stopRecordingInsertions() {
+  InsertedInstr = nullptr;
+}
+
 void MachineIRBuilderBase::recordInsertions(
     std::function<void(MachineInstr *)> Inserted) {
   State.InsertedInstr = std::move(Inserted);
 }
 
 void MachineIRBuilderBase::stopRecordingInsertions() {
   State.InsertedInstr = nullptr;
 }

lib/CodeGen/GlobalISel/RegBankSelect.cpp

 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,
                     "Assign register bank of generic virtual registers", false,
                     false)
 
 RegBankSelect::RegBankSelect(Mode RunningMode)
-    : MachineFunctionPass(ID), OptMode(RunningMode) {
+    : MachineFunctionPass(ID), MIRBuilder(MIRBuilderState),
+      OptMode(RunningMode) {
   initializeRegBankSelectPass(*PassRegistry::getPassRegistry());
   if (RegBankSelectMode.getNumOccurrences() != 0) {
     OptMode = RegBankSelectMode;
     if (RegBankSelectMode != RunningMode)
       LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
   }
 }
 

lib/Target/AArch64/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::selectVaStartDarwin(
   return true;
 }
 
 void AArch64InstructionSelector::materializeLargeCMVal(
     MachineInstr &I, const Value *V, unsigned char OpFlags) const {
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
-  MachineIRBuilder MIB(I);
+  MachineIRBuilderState State;
+  MachineIRBuilder MIB(I, State);
 
   auto MovZ = MIB.buildInstr(AArch64::MOVZXi, &AArch64::GPR64RegClass);
   MovZ->addOperand(MF, I.getOperand(1));
   MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
                                      AArch64II::MO_NC);
   MovZ->addOperand(MF, MachineOperand::CreateImm(0));
   constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);
 

lib/Target/AArch64/AArch64LegalizerInfo.h

 class AArch64Subtarget;
 
 /// This class provides the information for the target register banks.
 class AArch64LegalizerInfo : public LegalizerInfo {
 public:
   AArch64LegalizerInfo(const AArch64Subtarget &ST);
 
   bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
-                      MachineIRBuilder &MIRBuilder) const override;
+                      MachineIRBuilderState &) const override;
 
 private:
   bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     MachineIRBuilder &MIRBuilder) const;
+                     MachineIRBuilderState &State) const;
 };
 } // End llvm namespace.
 #endif

lib/Target/AArch64/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   }
 
   computeTables();
   verify(*ST.getInstrInfo());
 }
 
 bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI,
                                           MachineRegisterInfo &MRI,
-                                          MachineIRBuilder &MIRBuilder) const {
+                                          MachineIRBuilderState &State) const {
   switch (MI.getOpcode()) {
   default:
     // No idea what to do.
     return false;
   case TargetOpcode::G_VAARG:
-    return legalizeVaArg(MI, MRI, MIRBuilder);
+    return legalizeVaArg(MI, MRI, State);
   }
 
   llvm_unreachable("expected switch to return");
 }
 
 bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
                                          MachineRegisterInfo &MRI,
-                                         MachineIRBuilder &MIRBuilder) const {
+                                         MachineIRBuilderState &State) const {
+  MachineIRBuilder MIRBuilder(State);
   MIRBuilder.setInstr(MI);
   MachineFunction &MF = MIRBuilder.getMF();
   unsigned Align = MI.getOperand(2).getImm();
   unsigned Dst = MI.getOperand(0).getReg();
   unsigned ListPtr = MI.getOperand(1).getReg();
 
   LLT PtrTy = MRI.getType(ListPtr);
   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());

lib/Target/ARM/ARMLegalizerInfo.h

 class ARMSubtarget;
 
 /// This class provides the information for the target register banks.
 class ARMLegalizerInfo : public LegalizerInfo {
 public:
   ARMLegalizerInfo(const ARMSubtarget &ST);
 
   bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
-                      MachineIRBuilder &MIRBuilder) const override;
+                      MachineIRBuilderState &MIRBuilderState) const override;
 
 private:
   void setFCmpLibcallsGNU();
   void setFCmpLibcallsAEABI();
 
   struct FCmpLibcallInfo {
     // Which libcall this is.
     RTLIB::Libcall LibcallID;

lib/Target/ARM/ARMLegalizerInfo.cpp

ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
   assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
   if (Size == 32)
     return FCmp32Libcalls[Predicate];
   if (Size == 64)
     return FCmp64Libcalls[Predicate];
   llvm_unreachable("Unsupported size for FCmp predicate");
 }
 
-bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
-                                      MachineRegisterInfo &MRI,
-                                      MachineIRBuilder &MIRBuilder) const {
+bool ARMLegalizerInfo::legalizeCustom(
+    MachineInstr &MI, MachineRegisterInfo &MRI,
+    MachineIRBuilderState &MIRBuilderState) const {
   using namespace TargetOpcode;
 
+  MachineIRBuilder MIRBuilder(MIRBuilderState);
   MIRBuilder.setInstr(MI);
   LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
 
   switch (MI.getOpcode()) {
   default:
     return false;
   case G_SREM:
   case G_UREM: {

tools/llvm-exegesis/lib/Assembler.cpp

for (unsigned OpIndex = 0, E = Inst.getNumOperands(); OpIndex < E;
       }
     }
   }
   // Insert the return code.
   const llvm::TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   if (TII->getReturnOpcode() < TII->getNumOpcodes()) {
     llvm::BuildMI(MBB, DL, TII->get(TII->getReturnOpcode()));
   } else {
-    llvm::MachineIRBuilder MIB(MF);
+    llvm::MachineIRBuilderState State;
+    llvm::MachineIRBuilder MIB(MF, State);
     MIB.setMBB(*MBB);
     MF.getSubtarget().getCallLowering()->lowerReturn(MIB, nullptr, 0);
   }
 }
 
 static std::unique_ptr<llvm::Module>
 createModule(const std::unique_ptr<llvm::LLVMContext> &Context,
              const llvm::DataLayout DL) {

unittests/CodeGen/GlobalISel/LegalizerHelperTest.h

for (auto &MBB : *MF)
     for (MachineInstr &MI : MBB) {
       if (MI.getOpcode() == TargetOpcode::COPY)
         Copies.push_back(MI.getOperand(0).getReg());
     }
 }
 
 class LegalizerHelperTest : public ::testing::Test {
 protected:
-  LegalizerHelperTest() : ::testing::Test() {
+  LegalizerHelperTest() : ::testing::Test(), B(State) {
     TM = createTargetMachine();
     if (!TM)
       return;
     ModuleMMIPair = createDummyModule(Context, *TM, "");
     MF = getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
     collectCopies(Copies, MF);
     EntryMBB = &*MF->begin();
     B.setMF(*MF);
     MRI = &MF->getRegInfo();
     B.setInsertPt(*EntryMBB, EntryMBB->end());
   }
   LLVMContext Context;
   std::unique_ptr<TargetMachine> TM;
   MachineFunction *MF;
   std::pair<std::unique_ptr<Module>, std::unique_ptr<MachineModuleInfo>>
       ModuleMMIPair;
   SmallVector<unsigned, 4> Copies;
   MachineBasicBlock *EntryMBB;
   MachineIRBuilder B;
+  MachineIRBuilderState State;
   MachineRegisterInfo *MRI;
 };
 
 #define DefineLegalizerInfo(Name, SettingUpActionsBlock)                       \
   class Name##Info : public LegalizerInfo {                                    \
   public:                                                                      \
     Name##Info(const TargetSubtargetInfo &ST) {                                \
       using namespace TargetOpcode;                                            \

unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

TEST(PatternMatchInstr, MatchIntConstant) {
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
   auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
   int64_t Cst;
   bool match = mi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst));
   ASSERT_TRUE(match);
   ASSERT_EQ(Cst, 42);
 }
 
 TEST(PatternMatchInstr, MatchBinaryOp) {
   LLVMContext Context;
   std::unique_ptr<TargetMachine> TM = createTargetMachine();
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
   LLT s64 = LLT::scalar(64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   // Test case for no bind.
   bool match =
       mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg()));
   ASSERT_TRUE(match);
auto MIBCAdd1 =
                      CFB.buildConstant(s32, 1));
   // This should be a constant now.
   match = mi_match(MIBCAdd1->getOperand(0).getReg(), MRI, m_ICst(Cst));
   ASSERT_TRUE(match);
   ASSERT_EQ(Cst, 1);
 
   // Try one of the other constructors of MachineIRBuilder to make sure it's
   // compatible.
-  ConstantFoldingMIRBuilder CFB1(*MF);
+  ConstantFoldingMIRBuilder CFB1(*MF, State);
   CFB1.setInsertPt(*EntryMBB, EntryMBB->end());
   auto MIBCSub =
       CFB1.buildInstr(TargetOpcode::G_SUB, s32, CFB1.buildConstant(s32, 1),
                       CFB1.buildConstant(s32, 1));
   // This should be a constant now.
   match = mi_match(MIBCSub->getOperand(0).getReg(), MRI, m_ICst(Cst));
   ASSERT_TRUE(match);
   ASSERT_EQ(Cst, 0);
 }
 
 TEST(PatternMatchInstr, MatchFPUnaryOp) {
   LLVMContext Context;
   std::unique_ptr<TargetMachine> TM = createTargetMachine();
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
 
   // Truncate s64 to s32.
   LLT s32 = LLT::scalar(32);
   auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]);
 
   // Match G_FABS.
TEST(PatternMatchInstr, MatchExtendsTrunc) {
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
 
   auto MIBTrunc = B.buildTrunc(s32, Copies[0]);
   auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
   auto MIBZExt = B.buildZExt(s64, MIBTrunc);
TEST(PatternMatchInstr, MatchSpecificType) {
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
 
   // Try to match a 64bit add.
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   ASSERT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), MRI,
TEST(PatternMatchInstr, MatchCombinators) {
   if (!TM)
     return;
   auto ModuleMMIPair = createDummyModule(Context, *TM, "");
   MachineFunction *MF =
       getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get());
   SmallVector<unsigned, 4> Copies;
   collectCopies(Copies, MF);
   MachineBasicBlock *EntryMBB = &*MF->begin();
-  MachineIRBuilder B(*MF);
+  MachineIRBuilderState State;
+  MachineIRBuilder B(*MF, State);
   MachineRegisterInfo &MRI = MF->getRegInfo();
   B.setInsertPt(*EntryMBB, EntryMBB->end());
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   unsigned Src0, Src1;
   bool match =
       mi_match(MIBAdd->getOperand(0).getReg(), MRI,