[AArch64] Attempt to parse expressions as adr/adrp operands

[dmgreen]

Summary

This tries to make use of evaluateAsRelocatable in AArch64AsmParser::classifySymbolRef to
parse more complex expressions as relocatable operands to ADR/ADRP's. It is hopefully
better than the existing code which only handles Symbol +- Constant.

Fixes PR38831

[efriedma]

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

5289 ↗

(On Diff #164431)

classifySymbolRef is used for other instructions, including movw/movk, add/sub, and ldr. Please make sure we have appropriate test coverage.

It looks like a lot of instructions try to do some sort of fallback if classifySymbolRef fails. I'm not sure that actually make sense, but please make sure we have test coverage, at least.

5313 ↗

(On Diff #164431)

It looks like there isn't any test coverage for the !Res.getSymA() || Res.getSymB() part? In particular, I'm not sure why you'd want to reject an absolute value, in general.

There should probably also be test coverage that someone doesn't write something silly like adr x0, :lo12:f.

test/MC/AArch64/adr-badsyms.s

36 ↗

(On Diff #164431)

Newline?

[jakehehrlich]

cc @mcgrathr @phosek

Awesome! I'm looking at this now.

[peter.smith]

I don't have much to add over Eli's existing comments. I think the general form of (symA - symB) + constant may not be handled well for all instructions though.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

5313 ↗

(On Diff #164431)

In principle I agree that something like

 .text
lab1: nop
lab2: nop
 adr x0, lab2 - lab1 + 0x1000

which would be rejected by the code above, but is equivalent to adr x0, 0x1004 which is.

From a brief experiment I don't think that the backend can handle expressions like that for all relocations though. I ended up with a RELA relocation with addend 0x1004 to an undefined symbol, which unsurprisingly didn't get past the linker, we'd need an absolute symbol with value 0. May be if the backend were fixed first we could let that one through.

[dmgreen]

I seem to have stepped into a bit of a rabbit hole here.. and a lot of things seem to be a bit broken.

As far as I understand, something like (lab2-lab1)*2 + Sym should be accepted (if the difference between lab2 and lab1 is know, Sym can be relocated against). This is handled by gcc, but I don't see how it would be easily handled by clang atm. We are trying to classify these operands quite early.

I haven't managed to fix that here, but have added a number of tests around the place for things I couldn't see otherwise tested. Let me know if I should add any more.

I've also made mov's only accept 0 addends and ld/st accept addends > 0 and not mod scale. I think this is OK (it seems to be what gcc does, you don't know the alignment of Sym afterall), but I'm not sure if it needs to work that way for darwin.

[efriedma]

LGTM, but please give Peter a couple days to see if he has any additional comments.

[peter.smith]

Yes I'm happy with this too.

[phosek]

I tested this change with Fuchsia and it's working for us. Thank you for looking into this! I'd like to see this landed as soon as possible as it unblocks the toolchain roll for us.

[dmgreen]

OK. Thanks guys.

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SMLoc.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
DiagnosticPredicate isSVEPattern() const {
     if (!MCE)
       return DiagnosticPredicateTy::NoMatch;
     int64_t Val = MCE->getValue();
     if (Val >= 0 && Val < 32)
       return DiagnosticPredicateTy::Match;
     return DiagnosticPredicateTy::NearMatch;
   }
 
-  bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const {
+  bool isSymbolicUImm12Offset(const MCExpr *Expr) const {
     AArch64MCExpr::VariantKind ELFRefKind;
     MCSymbolRefExpr::VariantKind DarwinRefKind;
     int64_t Addend;
     if (!AArch64AsmParser::classifySymbolRef(Expr, ELFRefKind, DarwinRefKind,
                                            Addend)) {
       // If we don't understand the expression, assume the best and
       // let the fixup and relocation code deal with it.
       return true;
     }
 
     if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
         ELFRefKind == AArch64MCExpr::VK_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_GOT_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC ||
         ELFRefKind == AArch64MCExpr::VK_TPREL_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
         ELFRefKind == AArch64MCExpr::VK_GOTTPREL_LO12_NC ||
         ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_SECREL_LO12 ||
         ELFRefKind == AArch64MCExpr::VK_SECREL_HI12) {
       // Note that we don't range-check the addend. It's adjusted modulo page
       // size when converted, so there is no "out of range" condition when using
       // @pageoff.
-      return Addend >= 0 && (Addend % Scale) == 0;
+      return true;
     } else if (DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF ||
                DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF) {
       // @gotpageoff/@tlvppageoff can only be used directly, not with an addend.
       return Addend == 0;
     }
 
     return false;
   }
 
   template <int Scale> bool isUImm12Offset() const {
     if (!isImm())
       return false;
 
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
-      return isSymbolicUImm12Offset(getImm(), Scale);
+      return isSymbolicUImm12Offset(getImm());
 
     int64_t Val = MCE->getValue();
     return (Val % Scale) == 0 && Val >= 0 && (Val / Scale) < 0x1000;
   }
 
   template <int N, int M>
   bool isImmInRange() const {
     if (!isImm())
if (!AArch64AsmParser::classifySymbolRef(getImm(), ELFRefKind,
                                              DarwinRefKind, Addend)) {
       return false;
     }
     if (DarwinRefKind != MCSymbolRefExpr::VK_None)
       return false;
 
     for (unsigned i = 0; i != AllowedModifiers.size(); ++i) {
       if (ELFRefKind == AllowedModifiers[i])
-        return Addend == 0;
+        return true;
     }
 
     return false;
   }
 
   bool isMovZSymbolG3() const {
     return isMovWSymbol(AArch64MCExpr::VK_ABS_G3);
   }
AArch64AsmParser::classifySymbolRef(const MCExpr *Expr,
 
   const MCSymbolRefExpr *SE = dyn_cast<MCSymbolRefExpr>(Expr);
   if (SE) {
     // It's a simple symbol reference with no addend.
     DarwinRefKind = SE->getKind();
     return true;
   }
 
-  const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr);
-  if (!BE)
-    return false;
-
-  SE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
-  if (!SE)
-    return false;
-  DarwinRefKind = SE->getKind();
-
-  if (BE->getOpcode() != MCBinaryExpr::Add &&
-      BE->getOpcode() != MCBinaryExpr::Sub)
-    return false;
-
-  // See if the addend is a constant, otherwise there's more going
-  // on here than we can deal with.
-  auto AddendExpr = dyn_cast<MCConstantExpr>(BE->getRHS());
-  if (!AddendExpr)
+  // Check that it looks like a symbol + an addend
+  MCValue Res;
+  bool Relocatable = Expr->evaluateAsRelocatable(Res, nullptr, nullptr);
+  if (!Relocatable || !Res.getSymA() || Res.getSymB())
     return false;
 
-  Addend = AddendExpr->getValue();
-  if (BE->getOpcode() == MCBinaryExpr::Sub)
-    Addend = -Addend;
+  DarwinRefKind = Res.getSymA()->getKind();
+  Addend = Res.getConstant();
 
   // It's some symbol reference + a constant addend, but really
   // shouldn't use both Darwin and ELF syntax.
   return ELFRefKind == AArch64MCExpr::VK_INVALID ||
          DarwinRefKind == MCSymbolRefExpr::VK_None;
 }
 
 /// Force static initialization.

llvm/trunk/test/MC/AArch64/adr-diagnostics.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu %s -filetype=obj -o /dev/null 2>&1 | FileCheck %s
+
+  adr x0, -start
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adr x0, -start
+// CHECK-NEXT:   ^
+  adr x1, start * 10
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adr x1, start * 10
+// CHECK-NEXT:   ^
+  adr x2, 2 * (start + 987136)
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adr x2, 2 * (start + 987136)
+// CHECK-NEXT:   ^
+  adr x3, (end + start)
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adr x3, (end + start)
+// CHECK-NEXT:   ^
+  adr x4, #(end - start)
+// CHECK: error: No relocation available to represent this relative expression
+// CHECK-NEXT:   adr x4, #(end - start)
+// CHECK-NEXT:   ^
+
+  adrp x0, -start
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adrp x0, -start
+// CHECK-NEXT:   ^
+  adrp x1, start * 10
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adrp x1, start * 10
+// CHECK-NEXT:   ^
+  adrp x2, 2 * (start + 987136)
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adrp x2, 2 * (start + 987136)
+// CHECK-NEXT:   ^
+  adrp x3, (end + start)
+// CHECK: error: expected relocatable expression
+// CHECK-NEXT:   adrp x3, (end + start)
+// CHECK-NEXT:   ^
+  adrp x4, #(end - start)
+// CHECK: error: No relocation available to represent this relative expression
+// CHECK-NEXT:   adrp x4, #(end - start)
+// CHECK-NEXT:   ^

llvm/trunk/test/MC/AArch64/adr.s

+// RUN: llvm-mc -triple aarch64-elf -filetype=obj %s -o - | llvm-objdump -d -r - | FileCheck %s
+
+// CHECK: adr x0, #100
+// CHECK-NEXT: adr x2, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_LO21  Symbol
+// CHECK-NEXT: adr x3, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_LO21  Symbol
+// CHECK-NEXT: adr x4, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_LO21  Symbol+987136
+// CHECK-NEXT: adr x5, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_LO21  Symbol+987136
+// CHECK-NEXT: adr x6, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_LO21  Symbol+987136
+
+  adr x0, 100
+  adr x2, Symbol
+  adr x3, Symbol + 0
+  adr x4, Symbol + 987136
+  adr x5, (0xffffffff000f1000 - 0xffffffff00000000 + Symbol)
+  adr x6, Symbol + (0xffffffff000f1000 - 0xffffffff00000000)
+
+// CHECK-NEXT: adrp x0, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_PG_HI21 Symbol
+// CHECK-NEXT: adrp x2, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_PG_HI21 Symbol
+// CHECK-NEXT: adrp x3, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_PG_HI21 Symbol+987136
+// CHECK-NEXT: adrp x4, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_PG_HI21 Symbol+987136
+// CHECK-NEXT: adrp x5, #0
+// CHECK-NEXT: R_AARCH64_ADR_PREL_PG_HI21 Symbol+987136
+
+  adrp x0, Symbol
+  adrp x2, Symbol + 0
+  adrp x3, Symbol + 987136
+  adrp x4, (0xffffffff000f1000 - 0xffffffff00000000 + Symbol)
+  adrp x5, Symbol + (0xffffffff000f1000 - 0xffffffff00000000)

llvm/trunk/test/MC/AArch64/arm64-elf-relocs.s

 // RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
 // RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - < %s | \
 // RUN:   FileCheck --check-prefix=CHECK-ENCODING %s
 // RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \
 // RUN:   llvm-objdump -triple=arm64-linux-gnu - -r | \
 // RUN:   FileCheck %s --check-prefix=CHECK-OBJ-LP64
 
    add x0, x2, #:lo12:sym
+   add x0, x2, #:lo12:sym+12
+   add x0, x2, #:lo12:sym-3
 // CHECK: add x0, x2, :lo12:sym
+// CHECK: add x0, x2, :lo12:sym+12
+// CHECK: add x0, x2, :lo12:sym-3
 // CHECK-OBJ-LP64:  0 R_AARCH64_ADD_ABS_LO12_NC sym
+// CHECK-OBJ-LP64:  4 R_AARCH64_ADD_ABS_LO12_NC sym+12
+// CHECK-OBJ-LP64:  8 R_AARCH64_ADD_ABS_LO12_NC sym-3
 
    add x5, x7, #:dtprel_lo12:sym
 // CHECK: add x5, x7, :dtprel_lo12:sym
-// CHECK-OBJ-LP64: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
+// CHECK-OBJ-LP64: c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
 
    add x9, x12, #:dtprel_lo12_nc:sym
 // CHECK: add x9, x12, :dtprel_lo12_nc:sym
-// CHECK-OBJ-LP64: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64: 10 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
 
    add x20, x30, #:tprel_lo12:sym
 // CHECK: add x20, x30, :tprel_lo12:sym
-// CHECK-OBJ-LP64: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
+// CHECK-OBJ-LP64: 14 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
 
    add x9, x12, #:tprel_lo12_nc:sym
 // CHECK: add x9, x12, :tprel_lo12_nc:sym
-// CHECK-OBJ-LP64: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64: 18 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
 
    add x5, x0, #:tlsdesc_lo12:sym
 // CHECK: add x5, x0, :tlsdesc_lo12:sym
-// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12 sym
+// CHECK-OBJ-LP64: 1c R_AARCH64_TLSDESC_ADD_LO12 sym
 
         add x0, x2, #:lo12:sym+8
 // CHECK: add x0, x2, :lo12:sym
-// CHECK-OBJ-LP64: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
+// CHECK-OBJ-LP64: 20 R_AARCH64_ADD_ABS_LO12_NC sym+8
 
    add x5, x7, #:dtprel_lo12:sym+1
 // CHECK: add x5, x7, :dtprel_lo12:sym+1
-// CHECK-OBJ-LP64: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
+// CHECK-OBJ-LP64: 24 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
 
    add x9, x12, #:dtprel_lo12_nc:sym+2
 // CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
-// CHECK-OBJ-LP64:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
+// CHECK-OBJ-LP64: 28 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
 
    add x20, x30, #:tprel_lo12:sym+12
 // CHECK: add x20, x30, :tprel_lo12:sym+12
-// CHECK-OBJ-LP64: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
+// CHECK-OBJ-LP64: 2c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
 
    add x9, x12, #:tprel_lo12_nc:sym+54
 // CHECK: add x9, x12, :tprel_lo12_nc:sym+54
-// CHECK-OBJ-LP64: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
+// CHECK-OBJ-LP64: 30 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
 
    add x5, x0, #:tlsdesc_lo12:sym+70
 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
-// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12 sym+70
+// CHECK-OBJ-LP64: 34 R_AARCH64_TLSDESC_ADD_LO12 sym+70
 
         .hword sym + 4 - .
-// CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4
+// CHECK-OBJ-LP64: 38 R_AARCH64_PREL16 sym+4
         .word sym - . + 8
-// CHECK-OBJ-LP64: 32 R_AARCH64_PREL32 sym+8
+// CHECK-OBJ-LP64: 3a R_AARCH64_PREL32 sym+8
         .xword sym-.
-// CHECK-OBJ-LP64: 36 R_AARCH64_PREL64 sym{{$}}
+// CHECK-OBJ-LP64: 3e R_AARCH64_PREL64 sym{{$}}
 
         .hword sym
-// CHECK-OBJ-LP64: 3e R_AARCH64_ABS16 sym
+// CHECK-OBJ-LP64: 46 R_AARCH64_ABS16 sym
         .word sym+1
-// CHECK-OBJ-LP64: 40 R_AARCH64_ABS32 sym+1
+// CHECK-OBJ-LP64: 48 R_AARCH64_ABS32 sym+1
         .xword sym+16
-// CHECK-OBJ-LP64: 44 R_AARCH64_ABS64 sym+16
+// CHECK-OBJ-LP64: 4c R_AARCH64_ABS64 sym+16
 
    adrp x0, sym
 // CHECK: adrp x0, sym
-// CHECK-OBJ-LP64: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
+// CHECK-OBJ-LP64: 54 R_AARCH64_ADR_PREL_PG_HI21 sym
 
    adrp x15, :got:sym
 // CHECK: adrp x15, :got:sym
-// CHECK-OBJ-LP64: 50 R_AARCH64_ADR_GOT_PAGE sym
+// CHECK-OBJ-LP64: 58 R_AARCH64_ADR_GOT_PAGE sym
 
    adrp x29, :gottprel:sym
 // CHECK: adrp x29, :gottprel:sym
-// CHECK-OBJ-LP64: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
+// CHECK-OBJ-LP64: 5c R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
 
    adrp x2, :tlsdesc:sym
 // CHECK: adrp x2, :tlsdesc:sym
-// CHECK-OBJ-LP64: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
+// CHECK-OBJ-LP64: 60 R_AARCH64_TLSDESC_ADR_PAGE21 sym
 
    // LLVM is not competent enough to do this relocation because the
    // page boundary could occur anywhere after linking. A relocation
    // is needed.
    adrp x3, trickQuestion
    .global trickQuestion
 trickQuestion:
 // CHECK: adrp x3, trickQuestion
-// CHECK-OBJ-LP64: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
+// CHECK-OBJ-LP64: 64 R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
 
    ldrb w2, [x3, :lo12:sym]
    ldrsb w5, [x7, #:lo12:sym]
    ldrsb x11, [x13, :lo12:sym]
    ldr b17, [x19, #:lo12:sym]
+   ldrb w2, [x3, :lo12:sym+15]
+   ldrsb w5, [x7, #:lo12:sym-2]
+   ldr b17, [x19, #:lo12:sym+4]
 // CHECK: ldrb w2, [x3, :lo12:sym]
 // CHECK: ldrsb w5, [x7, :lo12:sym]
 // CHECK: ldrsb x11, [x13, :lo12:sym]
 // CHECK: ldr b17, [x19, :lo12:sym]
+// CHECK: ldrb w2, [x3, :lo12:sym+15]
+// CHECK: ldrsb w5, [x7, :lo12:sym-2]
+// CHECK: ldr b17, [x19, :lo12:sym+4]
 // CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym+15
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym-2
+// CHECK-OBJ-LP64: R_AARCH64_LDST8_ABS_LO12_NC sym+4
 
    ldrb w23, [x29, #:dtprel_lo12_nc:sym]
    ldrsb w23, [x19, #:dtprel_lo12:sym]
    ldrsb x17, [x13, :dtprel_lo12_nc:sym]
    ldr b11, [x7, #:dtprel_lo12:sym]
+   ldrb w23, [x29, #:dtprel_lo12_nc:sym+2]
 // CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
 // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
 // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
 // CHECK: ldr b11, [x7, :dtprel_lo12:sym]
+// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym+2]
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+// CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym+2
 
    ldrb w1, [x2, :tprel_lo12:sym]
    ldrsb w3, [x4, #:tprel_lo12_nc:sym]
    ldrsb x5, [x6, :tprel_lo12:sym]
    ldr b7, [x8, #:tprel_lo12_nc:sym]
 // CHECK: ldrb w1, [x2, :tprel_lo12:sym]
 // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
 // CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
 // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
 
    ldrh w2, [x3, #:lo12:sym]
    ldrsh w5, [x7, :lo12:sym]
    ldrsh x11, [x13, #:lo12:sym]
    ldr h17, [x19, :lo12:sym]
+   ldrh w2, [x3, #:lo12:sym+4]
 // CHECK: ldrh w2, [x3, :lo12:sym]
 // CHECK: ldrsh w5, [x7, :lo12:sym]
 // CHECK: ldrsh x11, [x13, :lo12:sym]
 // CHECK: ldr h17, [x19, :lo12:sym]
+// CHECK: ldrh w2, [x3, :lo12:sym+4]
 // CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-LP64: R_AARCH64_LDST16_ABS_LO12_NC sym+4
 
    ldrh w23, [x29, #:dtprel_lo12_nc:sym]
    ldrsh w23, [x19, :dtprel_lo12:sym]
    ldrsh x17, [x13, :dtprel_lo12_nc:sym]
    ldr h11, [x7, #:dtprel_lo12:sym]
 // CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
 // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
 // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]

 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
 // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
 
    ldr x28, [x27, :lo12:sym]
    ldr d26, [x25, #:lo12:sym]
+   ldr x28, [x27, :lo12:sym+10]
+   ldr x28, [x27, :lo12:sym-15]
 // CHECK: ldr x28, [x27, :lo12:sym]
 // CHECK: ldr d26, [x25, :lo12:sym]
+// CHECK: ldr x28, [x27, :lo12:sym+10]
+// CHECK: ldr x28, [x27, :lo12:sym-15]
 // CHECK-OBJ-LP64: R_AARCH64_LDST64_ABS_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LDST64_ABS_LO12_NC sym
+// CHECK-OBJ-LP64: R_AARCH64_LDST64_ABS_LO12_NC sym+10
+// CHECK-OBJ-LP64: R_AARCH64_LDST64_ABS_LO12_NC sym-15
 
    ldr x24, [x23, #:got_lo12:sym]
    ldr d22, [x21, :got_lo12:sym]
+   ldr x24, [x23, :got_lo12:sym+7]
 // CHECK: ldr x24, [x23, :got_lo12:sym]
 // CHECK: ldr d22, [x21, :got_lo12:sym]
+// CHECK: ldr x24, [x23, :got_lo12:sym+7]
 // CHECK-OBJ-LP64: R_AARCH64_LD64_GOT_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_LD64_GOT_LO12_NC sym
+// CHECK-OBJ-LP64: R_AARCH64_LD64_GOT_LO12_NC sym+7
 
    ldr x24, [x23, :dtprel_lo12_nc:sym]
    ldr d22, [x21, #:dtprel_lo12:sym]
 // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
 // CHECK: ldr d22, [x21, :dtprel_lo12:sym]
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
 // CHECK-OBJ-LP64: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
 

 // CHECK: add x3, x5, :lo12:imm
 
    ldr x24, #:got:sym
    ldr d22, :got:sym
 // CHECK: ldr x24, :got:sym
 // CHECK: ldr d22, :got:sym
 // CHECK-OBJ-LP64: R_AARCH64_GOT_LD_PREL19 sym
 // CHECK-OBJ-LP64: R_AARCH64_GOT_LD_PREL19 sym
 No newline at end of file

llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s

// CHECK-ERROR-NEXT:                       ^
         add x3, x9, #variable-16
 // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095]
 // CHECK-ERROR-NEXT:         add x3, x9, #variable
 // CHECK-ERROR-NEXT:                      ^
 // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095]
 // CHECK-ERROR-NEXT:         add x3, x9, #variable-16
 // CHECK-ERROR-NEXT:                 ^
 
+        // Relocation on a sub
+        sub x1, x0, :lo12:loc
+// CHECK-ERROR: error: invalid immediate expression
+// CHECK-ERROR:         sub x1, x0, :lo12:loc
+// CHECK-ERROR:                     ^
 
 
 //------------------------------------------------------------------------------
 // Add-subtract (shifted register)
 //------------------------------------------------------------------------------
 
         add wsp, w1, w2, lsr #3
         add x4, sp, x9, asr #5

 // CHECK-ERROR-NEXT:                   ^
 
 //------------------------------------------------------------------------------
 // PC-relative addressing
 //------------------------------------------------------------------------------
 
         adr sp, loc             // expects xzr
         adr x0, :got:loc        // bad relocation type
+        adr x1, :lo12:loc
         adrp x3, #20            // Immediate unaligned
         adrp w2, loc            // 64-bit register needed
         adrp x5, :got_lo12:loc  // bad relocation type
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         adr sp, loc
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: unexpected adr label
 // CHECK-ERROR-NEXT:         adr x0, :got:loc
 // CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: unexpected adr label
+// CHECK-ERROR-NEXT:         adr x1, :lo12:loc
+// CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected label or encodable integer pc offset
 // CHECK-ERROR-NEXT:         adrp x3, #20
 // CHECK-ERROR-NEXT:                  ^
 // CHECK-ERROR-NEXT: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         adrp w2, loc
 // CHECK-ERROR-NEXT:              ^
 // CHECK-ERROR-NEXT: error: page or gotpage label reference expected
 // CHECK-ERROR-NEXT:         adrp x5, :got_lo12:loc

llvm/trunk/test/MC/AArch64/elf-reloc-movw.s

// RUN:   llvm-readobj -r | FileCheck -check-prefix=OBJ %s
         movn x17, #:abs_g0_s:some_label
 
         movz x19, #:abs_g1_s:some_label
         movn x19, #:abs_g1_s:some_label
 
         movz x19, #:abs_g2_s:some_label
         movn x19, #:abs_g2_s:some_label
 
+        movz x19, #:abs_g1:some_label + 20 - 10
+        movn x19, #:abs_g2_s:some_label - 20 + 10
+        movk x11, #:abs_g3:some_label + 2 * 10
+
 // OBJ:      Relocations [
 // OBJ-NEXT:   Section {{.*}} .rela.text {
 // OBJ-NEXT:     0x0  R_AARCH64_MOVW_UABS_G0    some_label 0x0
 // OBJ-NEXT:     0x4  R_AARCH64_MOVW_UABS_G0_NC some_label 0x0
 // OBJ-NEXT:     0x8  R_AARCH64_MOVW_UABS_G1    some_label 0x0
 // OBJ-NEXT:     0xC  R_AARCH64_MOVW_UABS_G1_NC some_label 0x0
 // OBJ-NEXT:     0x10 R_AARCH64_MOVW_UABS_G2    some_label 0x0
 // OBJ-NEXT:     0x14 R_AARCH64_MOVW_UABS_G2_NC some_label 0x0
 // OBJ-NEXT:     0x18 R_AARCH64_MOVW_UABS_G3    some_label 0x0
 // OBJ-NEXT:     0x1C R_AARCH64_MOVW_UABS_G3    some_label 0x0
 // OBJ-NEXT:     0x20 R_AARCH64_MOVW_SABS_G0    some_label 0x0
 // OBJ-NEXT:     0x24 R_AARCH64_MOVW_SABS_G0    some_label 0x0
 // OBJ-NEXT:     0x28 R_AARCH64_MOVW_SABS_G1    some_label 0x0
 // OBJ-NEXT:     0x2C R_AARCH64_MOVW_SABS_G1    some_label 0x0
 // OBJ-NEXT:     0x30 R_AARCH64_MOVW_SABS_G2    some_label 0x0
 // OBJ-NEXT:     0x34 R_AARCH64_MOVW_SABS_G2    some_label 0x0
+// OBJ-NEXT:     0x38 R_AARCH64_MOVW_UABS_G1    some_label 0xA
+// OBJ-NEXT:     0x3C R_AARCH64_MOVW_SABS_G2    some_label 0xFFFFFFFFFFFFFFF6
+// OBJ-NEXT:     0x40 R_AARCH64_MOVW_UABS_G3    some_label 0x14
 // OBJ-NEXT:   }
 // OBJ-NEXT: ]

llvm/trunk/test/MC/AArch64/label-arithmetic-elf.s

 // RUN: llvm-mc -triple aarch64-elf -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
 
 start:
   .space 8
 end:
   // CHECK-LABEL: end:
 
   adds w0, w1, #(end - start)
   adds x0, x1, #(end - start)
   add w0, w1, #(end - start)
   add x0, x1, #(end - start)
   cmp w0, #(end - start)
   cmp x0, #(end - start)
   sub w0, w1, #(end - start)
   sub x0, x1, #(end - start)
+  // FIXME: adr x1, #(end - start) // This could be supported, but currently doesn't work
   // CHECK: adds w0, w1, #8
   // CHECK: adds x0, x1, #8
   // CHECK: add w0, w1, #8
   // CHECK: add x0, x1, #8
   // CHECK: cmp w0, #8
   // CHECK: cmp x0, #8
   // CHECK: sub w0, w1, #8
   // CHECK: sub x0, x1, #8
+  // FIXME: adr x1, #8
 
   add w0, w1, #(end - start), lsl #12
   cmp w0, #(end - start), lsl #12
   // CHECK: add w0, w1, #8, lsl #12
   // CHECK: cmp w0, #8, lsl #12
 
   add w0, w1, #((end - start) >> 2)
   cmp w0, #((end - start) >> 2)