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Differential D51213

[MIPS GlobalISel] Legalize i8 and i16 add
ClosedPublic

Authored by Petar.Avramovic on Aug 24 2018, 6:18 AM.

Details

Reviewers
atanasyan
petarj
dsanders
Commits
rG1fa5051bad75: [MIPS GlobalISel] Legalize i8 and i16 add
rL340697: [MIPS GlobalISel] Legalize i8 and i16 add
Summary

Legalize G_ADD for types smaller then i32.
LegalizationArtifactCombiner replaces extend instructions with appropriate bitwise instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Aug 24 2018, 6:18 AM
Herald added subscribers: arichardson, kristof.beyls, rovka, sdardis. · View Herald TranscriptAug 24 2018, 6:18 AM
atanasyan accepted this revision.Aug 26 2018, 12:04 AM

LGTM

This revision is now accepted and ready to land.Aug 26 2018, 12:04 AM
Closed by commit rL340697: [MIPS GlobalISel] Legalize i8 and i16 add (authored by petarj). · Explain WhyAug 26 2018, 12:26 AM
This revision was automatically updated to reflect the committed changes.
Herald added subscribers: llvm-commits, jrtc27. · View Herald TranscriptAug 26 2018, 12:26 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
4 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
188 lines
llvm-ir/
76 lines

Diff 162580

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 16 Lines
using namespace llvm; using namespace llvm;
MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
using namespace TargetOpcode; using namespace TargetOpcode;
const LLT s32 = LLT::scalar(32); const LLT s32 = LLT::scalar(32);
const LLT p0 = LLT::pointer(0, 32); const LLT p0 = LLT::pointer(0, 32);
getActionDefinitionsBuilder(G_ADD).legalFor({s32}); getActionDefinitionsBuilder(G_ADD)
.legalFor({s32})
.minScalar(0, s32);
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0}); .legalForCartesianProduct({p0, s32}, {p0});
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR})
.legalFor({s32}); .legalFor({s32});
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
Show All 14 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @add_i32(i32 %x, i32 %y) {entry: ret void} define void @add_i32() {entry: ret void}
define void @add_i8_sext() {entry: ret void}
define void @add_i8_zext() {entry: ret void}
define void @add_i8_aext() {entry: ret void}
define void @add_i16_sext() {entry: ret void}
define void @add_i16_zext() {entry: ret void}
define void @add_i16_aext() {entry: ret void}
... ...
--- ---
name: add_i32 name: add_i32
alignment: 2 alignment: 2
legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: add_i32 ; MIPS32-LABEL: name: add_i32
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32: $v0 = COPY [[ADD]](s32) ; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_ADD %0, %1 %2:_(s32) = G_ADD %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
---
name: add_i8_sext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i8_sext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: add_i8_zext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i8_zext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: add_i8_aext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i8_aext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s8)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: add_i16_sext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i16_sext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_SEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: add_i16_zext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i16_zext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ZEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...
---
name: add_i16_aext
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: add_i16_aext
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: $v0 = COPY [[COPY4]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_ADD %1, %0
%5:_(s32) = G_ANYEXT %4(s16)
$v0 = COPY %5(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @add_i32(i32 %x, i32 %y) { define i32 @add_i32(i32 %x, i32 %y) {
; MIPS32-LABEL: add_i32: ; MIPS32-LABEL: add_i32:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $2, $4, $5 ; MIPS32-NEXT: addu $2, $4, $5
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%z = add i32 %x, %y %z = add i32 %x, %y
ret i32 %z ret i32 %z
} }
define signext i8 @add_i8_sext(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: add_i8_sext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: sll $4, $4, 24
; MIPS32-NEXT: sra $2, $4, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i8 %b, %a
ret i8 %add
}
define zeroext i8 @add_i8_zext(i8 zeroext %a, i8 zeroext %b) {
; MIPS32-LABEL: add_i8_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: lui $5, 0
; MIPS32-NEXT: ori $5, $5, 255
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i8 %b, %a
ret i8 %add
}
define i8 @add_i8_aext(i8 %a, i8 %b) {
; MIPS32-LABEL: add_i8_aext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i8 %b, %a
ret i8 %add
}
define signext i16 @add_i16_sext(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: add_i16_sext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: sll $4, $4, 16
; MIPS32-NEXT: sra $2, $4, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i16 %b, %a
ret i16 %add
}
define zeroext i16 @add_i16_zext(i16 zeroext %a, i16 zeroext %b) {
; MIPS32-LABEL: add_i16_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: lui $5, 0
; MIPS32-NEXT: ori $5, $5, 65535
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i16 %b, %a
ret i16 %add
}
define i16 @add_i16_aext(i16 %a, i16 %b) {
; MIPS32-LABEL: add_i16_aext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $2, $5, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%add = add i16 %b, %a
ret i16 %add
}