[Sparc] Add tail call support

[dcederman]

Summary

This patch adds tail call support to the 32-bit Sparc backend.

Two new instructions are defined, TAIL_CALL and TAIL_CALLri. They are encoded the same as CALL and BINDri, but are marked with isReturn so that the epilogue gets emitted. In contrast to CALL, TAIL_CALL is not marked with isCall. This makes it possible to use the leaf function optimization when the only call a function makes is a tail call.

TAIL_CALL modifies the return address in %o7, so for leaf functions the value in %o7 needs to be restored after the call. For normal functions which uses the restore instruction this is not necessary.

[dcederman]

Do not tail call opt if either the callee or caller returns a struct and the other does not.

[jrtc27]

lib/Target/Sparc/SparcISelLowering.cpp

733 ↗

(On Diff #180646)

Whilst correct for now given the 64-bit lowering does not support tail calls, this condition only applies to the 32-bit SPARC ABI, as the 64-bit ABI does not have the extra unimp after the delay slot for struct-returning functions. Perhaps worth adding a comment here so this doesn't get forgotten?

[dcederman]

lib/Target/Sparc/SparcISelLowering.cpp

733 ↗

(On Diff #180646)

Ok, I'll add a condition to only disallow this on 32-bit SPARC.

[dcederman]

On 64-bit Sparc we can allow tail call optimizations on functions that returns a struct even though the caller does not (and vice versa).

[dcederman]

Rebased on master. Changed unsigned into Register in a couple of places and changed "no-frame-pointer-elim" to "frame-pointer" in test.

[jrtc27]

llvm/test/CodeGen/SPARC/tailcall.ll

2

Perhaps worth using update_llc_test_checks.py, or at least adding some CHECK-NEXTs as the delay slot being filled (rather than something else being silently emitted in between) is pretty important.

[dcederman]

Autogenerated assertions with update_llc_test_checks.py.

[brad]

ping.

[koakuma]

Looks good to me, also all testcases are passing here:

-- Testing: 93 tests, 48 workers --
PASS: LLVM :: CodeGen/SPARC/2007-05-09-JumpTables.ll (1 of 93)
PASS: LLVM :: CodeGen/SPARC/2012-05-01-LowerArguments.ll (2 of 93)
PASS: LLVM :: CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll (3 of 93)
PASS: LLVM :: CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll (4 of 93)
PASS: LLVM :: CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll (5 of 93)
PASS: LLVM :: CodeGen/SPARC/2009-08-28-WeakLinkage.ll (6 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-22-SRet.ll (7 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-21-ByValArgs.ll (8 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonDetectRoundChangePassUT.ll (9 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-12-03-TailDuplication.ll (10 of 93)
PASS: LLVM :: CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll (11 of 93)
PASS: LLVM :: CodeGen/SPARC/cast-sret-func.ll (12 of 93)
PASS: LLVM :: CodeGen/SPARC/DbgValueOtherTargets.test (13 of 93)
PASS: LLVM :: CodeGen/SPARC/64cond.ll (14 of 93)
PASS: LLVM :: CodeGen/SPARC/analyze-branch.ll (15 of 93)
PASS: LLVM :: CodeGen/SPARC/64atomics.ll (16 of 93)
PASS: LLVM :: CodeGen/SPARC/fp128-split.ll (17 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll (18 of 93)
PASS: LLVM :: CodeGen/SPARC/empty-functions.ll (19 of 93)
PASS: LLVM :: CodeGen/SPARC/64spill.ll (20 of 93)
PASS: LLVM :: CodeGen/SPARC/basictest.ll (21 of 93)
PASS: LLVM :: CodeGen/SPARC/float-constants.ll (22 of 93)
PASS: LLVM :: CodeGen/SPARC/codemodel.ll (23 of 93)
PASS: LLVM :: CodeGen/SPARC/constructor.ll (24 of 93)
PASS: LLVM :: CodeGen/SPARC/inline-asm-i-constraint-i1.ll (25 of 93)
PASS: LLVM :: CodeGen/SPARC/inlineasm-output-template.ll (26 of 93)
PASS: LLVM :: CodeGen/SPARC/imm.ll (27 of 93)
PASS: LLVM :: CodeGen/SPARC/missinglabel.ll (28 of 93)
PASS: LLVM :: CodeGen/SPARC/fshl.ll (29 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll (30 of 93)
PASS: LLVM :: CodeGen/SPARC/inlineasm-v9.ll (31 of 93)
PASS: LLVM :: CodeGen/SPARC/fail-alloca-align.ll (32 of 93)
PASS: LLVM :: CodeGen/SPARC/leafproc.ll (33 of 93)
PASS: LLVM :: CodeGen/SPARC/pic.ll (34 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-11-Call.ll (35 of 93)
PASS: LLVM :: CodeGen/SPARC/parts.ll (36 of 93)
PASS: LLVM :: CodeGen/SPARC/missing-sret.ll (37 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonSMACUMACInstructionUT.ll (38 of 93)
PASS: LLVM :: CodeGen/SPARC/2013-05-17-CallFrame.ll (39 of 93)
PASS: LLVM :: CodeGen/SPARC/inlineasm.ll (40 of 93)
PASS: LLVM :: CodeGen/SPARC/private.ll (41 of 93)
PASS: LLVM :: CodeGen/SPARC/rem.ll (42 of 93)
PASS: LLVM :: CodeGen/SPARC/multiple-div.ll (43 of 93)
PASS: LLVM :: CodeGen/SPARC/readcycle.ll (44 of 93)
PASS: LLVM :: CodeGen/SPARC/register-clobber.ll (45 of 93)
PASS: LLVM :: CodeGen/SPARC/reg64.ll (46 of 93)
PASS: LLVM :: CodeGen/SPARC/inlineasm-bad.ll (47 of 93)
PASS: LLVM :: CodeGen/SPARC/mature-mc-support.ll (48 of 93)
PASS: LLVM :: CodeGen/SPARC/sethiandn.ll (49 of 93)
PASS: LLVM :: CodeGen/SPARC/mult-alt-generic-sparc.ll (50 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-19-DelaySlot.ll (51 of 93)
PASS: LLVM :: CodeGen/SPARC/select-mask.ll (52 of 93)
PASS: LLVM :: CodeGen/SPARC/sret-secondary.ll (53 of 93)
PASS: LLVM :: CodeGen/SPARC/spillsize.ll (54 of 93)
PASS: LLVM :: CodeGen/SPARC/obj-relocs.ll (55 of 93)
PASS: LLVM :: CodeGen/SPARC/32abi.ll (56 of 93)
PASS: LLVM :: CodeGen/SPARC/spill.ll (57 of 93)
PASS: LLVM :: CodeGen/SPARC/disable-fsmuld-fmuls.ll (58 of 93)
PASS: LLVM :: CodeGen/SPARC/2009-08-28-PIC.ll (59 of 93)
PASS: LLVM :: CodeGen/SPARC/64bit.ll (60 of 93)
PASS: LLVM :: CodeGen/SPARC/soft-mul-div.ll (61 of 93)
PASS: LLVM :: CodeGen/SPARC/trap.ll (62 of 93)
PASS: LLVM :: CodeGen/SPARC/reserved-regs.ll (63 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-11-CC.ll (64 of 93)
PASS: LLVM :: CodeGen/SPARC/varargs-v8.ll (65 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonItinerariesUT.ll (66 of 93)
PASS: LLVM :: CodeGen/SPARC/zerostructcall.ll (67 of 93)
PASS: LLVM :: CodeGen/SPARC/vector-extract-elt.ll (68 of 93)
PASS: LLVM :: CodeGen/SPARC/vector-call.ll (69 of 93)
PASS: LLVM :: CodeGen/SPARC/stack-align.ll (70 of 93)
PASS: LLVM :: CodeGen/SPARC/tailcall.ll (71 of 93)
PASS: LLVM :: CodeGen/SPARC/soft-float.ll (72 of 93)
PASS: LLVM :: CodeGen/SPARC/setjmp.ll (73 of 93)
PASS: LLVM :: CodeGen/SPARC/thread-pointer.ll (74 of 93)
PASS: LLVM :: CodeGen/SPARC/overflow-intrinsic-optimizations.ll (75 of 93)
PASS: LLVM :: CodeGen/SPARC/2011-01-11-FrameAddr.ll (76 of 93)
PASS: LLVM :: CodeGen/SPARC/64abi.ll (77 of 93)
PASS: LLVM :: CodeGen/SPARC/exception.ll (78 of 93)
PASS: LLVM :: CodeGen/SPARC/smulo-128-legalisation-lowering.ll (79 of 93)
PASS: LLVM :: CodeGen/SPARC/varargs.ll (80 of 93)
PASS: LLVM :: CodeGen/SPARC/umulo-128-legalisation-lowering.ll (81 of 93)
PASS: LLVM :: CodeGen/SPARC/blockaddr.ll (82 of 93)
PASS: LLVM :: CodeGen/SPARC/atomics.ll (83 of 93)
PASS: LLVM :: CodeGen/SPARC/constpool.ll (84 of 93)
PASS: LLVM :: CodeGen/SPARC/stack-protector.ll (85 of 93)
PASS: LLVM :: CodeGen/SPARC/globals.ll (86 of 93)
PASS: LLVM :: CodeGen/SPARC/func-addr.ll (87 of 93)
PASS: LLVM :: CodeGen/SPARC/float.ll (88 of 93)
PASS: LLVM :: CodeGen/SPARC/fp16-promote.ll (89 of 93)
PASS: LLVM :: CodeGen/SPARC/ctpop.ll (90 of 93)
PASS: LLVM :: CodeGen/SPARC/tls.ll (91 of 93)
PASS: LLVM :: CodeGen/SPARC/LeonCASAInstructionUT.ll (92 of 93)
PASS: LLVM :: CodeGen/SPARC/fp128.ll (93 of 93)

Testing Time: 52.30s
  Passed: 93

llvm/lib/Target/Sparc/DelaySlotFiller.cpp

Filler::findDelayInstr(MachineBasicBlock &MBB,
   SmallSet<unsigned, 32> RegDefs;
   SmallSet<unsigned, 32> RegUses;
   bool sawLoad = false;
   bool sawStore = false;
 
   if (slot == MBB.begin())
     return MBB.end();
 
-  if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
+  unsigned Opc = slot->getOpcode();
+
+  if (Opc == SP::RET || Opc == SP::TLS_CALL)
     return MBB.end();
 
-  if (slot->getOpcode() == SP::RETL) {
+  if (Opc == SP::RETL || Opc == SP::TAIL_CALL || Opc == SP::TAIL_CALLri) {
     MachineBasicBlock::iterator J = slot;
     --J;
 
     if (J->getOpcode() == SP::RESTORErr
         || J->getOpcode() == SP::RESTOREri) {
       // change retl to ret.
+      if (Opc == SP::RETL)
         slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
       return J;
     }
   }
 
   // Call's delay filler can def some of call's uses.
   if (slot->isCall())
     insertCallDefsUses(slot, RegDefs, RegUses);
   else
bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
 
   unsigned structSizeOpNum = 0;
   switch (I->getOpcode()) {
   default: llvm_unreachable("Unknown call opcode.");
   case SP::CALL: structSizeOpNum = 1; break;
   case SP::CALLrr:
   case SP::CALLri: structSizeOpNum = 2; break;
   case SP::TLS_CALL: return false;
+  case SP::TAIL_CALLri:
+  case SP::TAIL_CALL: return false;
   }
 
   const MachineOperand &MO = I->getOperand(structSizeOpNum);
   if (!MO.isImm())
     return false;
   StructSize = MO.getImm();
   return true;
 }

llvm/lib/Target/Sparc/SparcCallingConv.td

def RetCC_Sparc64 : CallingConv<[
 
   // Otherwise, return values are passed exactly like arguments.
   CCDelegateTo<CC_Sparc64>
 ]>;
 
 // Callee-saved registers are handled by the register window mechanism.
 def CSR : CalleeSavedRegs<(add)> {
   let OtherPreserved = (add (sequence "I%u", 0, 7),
-                            (sequence "L%u", 0, 7));
+                            (sequence "L%u", 0, 7), O6);
 }
 
 // Callee-saved registers for calls with ReturnsTwice attribute.
 def RTCSR : CalleeSavedRegs<(add)> {
   let OtherPreserved = (add I6, I7);
 }

llvm/lib/Target/Sparc/SparcFrameLowering.cpp

 
 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
                                   MachineBasicBlock &MBB) const {
   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
   const SparcInstrInfo &TII =
       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
   DebugLoc dl = MBBI->getDebugLoc();
-  assert(MBBI->getOpcode() == SP::RETL &&
-         "Can only put epilog before 'retl' instruction!");
+  assert((MBBI->getOpcode() == SP::RETL || MBBI->getOpcode() == SP::TAIL_CALL ||
+          MBBI->getOpcode() == SP::TAIL_CALLri) &&
+         "Can only put epilog before 'retl' or 'tail_call' instruction!");
   if (!FuncInfo->isLeafProc()) {
     BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
       .addReg(SP::G0);
     return;
   }
   MachineFrameInfo &MFI = MF.getFrameInfo();
 
   int NumBytes = (int) MFI.getStackSize();
-  if (NumBytes == 0)
-    return;
-
+  if (NumBytes != 0)
     emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
+
+  // Preserve return address in %o7
+  if (MBBI->getOpcode() == SP::TAIL_CALL) {
+    MBB.addLiveIn(SP::O7);
+    BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::G1)
+        .addReg(SP::G0)
+        .addReg(SP::O7);
+    BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::O7)
+        .addReg(SP::G0)
+        .addReg(SP::G1);
+  }
 }
 
 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
   // Reserve call frame if there are no variable sized objects on the stack.
   return !MF.getFrameInfo().hasVarSizedObjects();
 }
 
 // hasFP - Return true if the specified function should have a dedicated frame

llvm/lib/Target/Sparc/SparcISelLowering.h

 
 #include "Sparc.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
   class SparcSubtarget;
 
   namespace SPISD {
     enum NodeType : unsigned {
       FIRST_NUMBER = ISD::BUILTIN_OP_END,
       CMPICC,      // Compare two GPR operands, set icc+xcc.
       CMPFCC,      // Compare two FP operands, set fcc.
       BRICC,       // Branch to dest on icc condition
       BRXCC,       // Branch to dest on xcc condition (64-bit only).
       BRFCC,       // Branch to dest on fcc condition
       SELECT_ICC,  // Select between two values using the current ICC flags.
       SELECT_XCC,  // Select between two values using the current XCC flags.
       SELECT_FCC,  // Select between two values using the current FCC flags.
 
       Hi, Lo,      // Hi/Lo operations, typically on a global address.
 
       FTOI,        // FP to Int within a FP register.
       ITOF,        // Int to FP within a FP register.
       FTOX,        // FP to Int64 within a FP register.
       XTOF,        // Int64 to FP within a FP register.
 
       CALL,        // A call instruction.
       RET_FLAG,    // Return with a flag operand.
       GLOBAL_BASE_REG, // Global base reg for PIC.
       FLUSHW,      // FLUSH register windows to stack.
 
+      TAIL_CALL,   // Tail call
+
       TLS_ADD,     // For Thread Local Storage (TLS).
       TLS_LD,
       TLS_CALL
     };
   }
 
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
public:
 
     SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
     SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
                                    SelectionDAG &DAG) const;
 
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
+    bool IsEligibleForTailCallOptimization(CCState &CCInfo,
+                                           CallLoweringInfo &CLI,
+                                           MachineFunction &MF) const;
+
     bool ShouldShrinkFPConstant(EVT VT) const override {
       // Do not shrink FP constpool if VT == MVT::f128.
       // (ldd, call _Q_fdtoq) is more expensive than two ldds.
       return VT != MVT::f128;
     }
 
     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
       // FIXME: We insert fences for each atomics and generate

llvm/lib/Target/Sparc/SparcISelLowering.cpp

if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
     CalleeFn = M->getFunction(CalleeName);
   }
 
   if (!CalleeFn)
     return false;
   return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
 }
 
+/// IsEligibleForTailCallOptimization - Check whether the call is eligible
+/// for tail call optimization.
+bool SparcTargetLowering::IsEligibleForTailCallOptimization(
+    CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
+
+  auto &Outs = CLI.Outs;
+  auto &Caller = MF.getFunction();
+
+  // Do not tail call opt functions with "disable-tail-calls" attribute.
+  if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
+    return false;
+
+  // Do not tail call opt if the stack is used to pass parameters.
+  if (CCInfo.getNextStackOffset() != 0)
+    return false;
+
+  // Do not tail call opt if either the callee or caller returns
+  // a struct and the other does not.
+  if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
+    return false;
+
+  // Byval parameters hand the function a pointer directly into the stack area
+  // we want to reuse during a tail call.
+  for (auto &Arg : Outs)
+    if (Arg.Flags.isByVal())
+      return false;
+
+  return true;
+}
+
 // Lower a call for the 32-bit ABI.
 SDValue
 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
                                   SmallVectorImpl<SDValue> &InVals) const {
   SelectionDAG &DAG                     = CLI.DAG;
   SDLoc &dl                             = CLI.DL;
   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
   SDValue Chain                         = CLI.Chain;
   SDValue Callee                        = CLI.Callee;
   bool &isTailCall                      = CLI.IsTailCall;
   CallingConv::ID CallConv              = CLI.CallConv;
   bool isVarArg                         = CLI.IsVarArg;
 
-  // Sparc target does not yet support tail call optimization.
-  isTailCall = false;
-
   // Analyze operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
                  *DAG.getContext());
   CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
 
+  isTailCall = isTailCall && IsEligibleForTailCallOptimization(
+                                 CCInfo, CLI, DAG.getMachineFunction());
+
   // Get the size of the outgoing arguments stack space requirement.
   unsigned ArgsSize = CCInfo.getNextStackOffset();
 
   // Keep stack frames 8-byte aligned.
   ArgsSize = (ArgsSize+7) & ~7;
 
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
 
if (Size > 0U) {
       ByValArgs.push_back(FIPtr);
     }
     else {
       SDValue nullVal;
       ByValArgs.push_back(nullVal);
     }
   }
 
+  assert(!isTailCall || ArgsSize == 0);
+
+  if (!isTailCall)
     Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
 
   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
   SmallVector<SDValue, 8> MemOpChains;
 
   const unsigned StackOffset = 92;
   bool hasStructRetAttr = false;
   unsigned SRetArgSize = 0;
   // Walk the register/memloc assignments, inserting copies/loads.
case CCValAssign::AExt:
       break;
     case CCValAssign::BCvt:
       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
       break;
     }
 
     if (Flags.isSRet()) {
       assert(VA.needsCustom());
+
+      if (isTailCall)
+        continue;
+
       // store SRet argument in %sp+64
       SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
       SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
       PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
       MemOpChains.push_back(
           DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
       hasStructRetAttr = true;
       // sret only allowed on first argument
if (!MemOpChains.empty())
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
 
   // Build a sequence of copy-to-reg nodes chained together with token
   // chain and flag operands which copy the outgoing args into registers.
   // The InFlag in necessary since all emitted instructions must be
   // stuck together.
   SDValue InFlag;
   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
-    Register Reg = toCallerWindow(RegsToPass[i].first);
+    Register Reg = RegsToPass[i].first;
+    if (!isTailCall)
+      Reg = toCallerWindow(Reg);
     Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
     InFlag = Chain.getValue(1);
   }
 
   bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
 
   // If the callee is a GlobalAddress node (quite common, every direct call is)
   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
   // Likewise ExternalSymbol -> TargetExternalSymbol.
   unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30
                                         : SparcMCExpr::VK_Sparc_WDISP30;
   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
 
   // Returns a chain & a flag for retval copy to use
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
   if (hasStructRetAttr)
     Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
-  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
-    Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
-                                  RegsToPass[i].second.getValueType()));
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
+    Register Reg = RegsToPass[i].first;
+    if (!isTailCall)
+      Reg = toCallerWindow(Reg);
+    Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
+  }
 
   // Add a register mask operand representing the call-preserved registers.
   const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
   const uint32_t *Mask =
       ((hasReturnsTwice)
            ? TRI->getRTCallPreservedMask(CallConv)
            : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
   assert(Mask && "Missing call preserved mask for calling convention");
   Ops.push_back(DAG.getRegisterMask(Mask));
 
   if (InFlag.getNode())
     Ops.push_back(InFlag);
 
+  if (isTailCall) {
+    DAG.getMachineFunction().getFrameInfo().setHasTailCall();
+    return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
+  }
+
   Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
   InFlag = Chain.getValue(1);
 
   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
                              DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
   InFlag = Chain.getValue(1);
 
   // Assign locations to each value returned by this call.
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::XTOF:            return "SPISD::XTOF";
   case SPISD::CALL:            return "SPISD::CALL";
   case SPISD::RET_FLAG:        return "SPISD::RET_FLAG";
   case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
   case SPISD::FLUSHW:          return "SPISD::FLUSHW";
   case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
   case SPISD::TLS_LD:          return "SPISD::TLS_LD";
   case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
+  case SPISD::TAIL_CALL:       return "SPISD::TAIL_CALL";
   }
   return nullptr;
 }
 
 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())
     return MVT::i32;

llvm/lib/Target/Sparc/SparcInstrInfo.td

 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 def SDT_SPCall    : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
 def call          : SDNode<"SPISD::CALL", SDT_SPCall,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                             SDNPVariadic]>;
 
+def tailcall      : SDNode<"SPISD::TAIL_CALL", SDT_SPCall,
+                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+                            SDNPVariadic]>;
+
 def SDT_SPRet     : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 def retflag       : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
                            [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 
 def flushw        : SDNode<"SPISD::FLUSHW", SDTNone,
                            [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
 
 def tlsadd        : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
def TLS_CALL : InstSP<(outs),
                         IIC_jmp_or_call> {
   bits<30> disp;
   let op = 1;
   let Inst{29-0} = disp;
 }
 }
 
 //===----------------------------------------------------------------------===//
+// Instructions for tail calls.
+//===----------------------------------------------------------------------===//
+let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,
+    isTerminator = 1, isBarrier = 1 in {
+  def TAIL_CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
+                         "call $disp",
+                         [(tailcall tglobaladdr:$disp)]> {
+  bits<30> disp;
+  let op = 1;
+  let Inst{29-0} = disp;
+  }
+}
+
+def : Pat<(tailcall (iPTR texternalsym:$dst)),
+          (TAIL_CALL texternalsym:$dst)>;
+
+let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,  isTerminator = 1,
+    isBarrier = 1, rd = 0 in {
+  def TAIL_CALLri : F3_2<2, 0b111000,
+                         (outs), (ins MEMri:$ptr, variable_ops),
+                         "jmp $ptr",
+                         [(tailcall ADDRri:$ptr)]>;
+}
+
+//===----------------------------------------------------------------------===//
 // V9 Instructions
 //===----------------------------------------------------------------------===//
 
 // V9 Conditional Moves.
 let Predicates = [HasV9], Constraints = "$f = $rd" in {
   // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
   let Uses = [ICC], intcc = 1, cc = 0b00 in {
     def MOVICCrr

llvm/test/CodeGen/SPARC/2011-01-11-Call.ll

 ; V9:       save %sp
 ; V9:       call foo
 ; V9-NEXT:  nop
 ; V9:       call bar
 ; V9-NEXT:  nop
 ; V9:       ret
 ; V9-NEXT:  restore
 
-define void @test() nounwind {
+define void @test() #0 {
 entry:
  %0 = tail call i32 (...) @foo() nounwind
  tail call void (...) @bar() nounwind
  ret void
 }
 
 declare i32 @foo(...)
 
 declare void @bar(...)
 
-
 ; V8-LABEL: test_tail_call_with_return
-; V8:       save %sp
-; V8:       call foo
-; V8-NEXT:  nop
-; V8:       ret
-; V8-NEXT:  restore %g0, %o0, %o0
+; V8:       mov %o7, %g1
+; V8-NEXT:  call foo
+; V8-NEXT:  mov %g1, %o7
 
 ; V9-LABEL: test_tail_call_with_return
 ; V9:       save %sp
 ; V9:       call foo
 ; V9-NEXT:  nop
 ; V9:       ret
 ; V9-NEXT:  restore %g0, %o0, %o0
 
 define i32 @test_tail_call_with_return() nounwind {
 entry:
  %0 = tail call i32 (...) @foo() nounwind
  ret i32 %0
 }
+
+attributes #0 = { nounwind "disable-tail-calls"="true" }

llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll

 ;RUN: llc -march=sparc < %s -verify-machineinstrs | FileCheck %s
 ;RUN: llc -march=sparc -O0 < %s -verify-machineinstrs | FileCheck %s -check-prefix=UNOPT
 
 target triple = "sparc-unknown-linux-gnu"
 
-define i32 @test(i32 %a) nounwind {
+define i32 @test(i32 %a) #0 {
 entry:
 ; CHECK: test
 ; CHECK: call bar
 ; CHECK-NOT: nop
 ; CHECK: ret
 ; CHECK-NEXT: restore
   %0 = tail call i32 @bar(i32 %a) nounwind
   ret i32 %0
 }
 
-define i32 @test_jmpl(i32 (i32, i32)* nocapture %f, i32 %a, i32 %b) nounwind {
+define i32 @test_jmpl(i32 (i32, i32)* nocapture %f, i32 %a, i32 %b) #0 {
 entry:
 ; CHECK:      test_jmpl
 ; CHECK:      call
 ; CHECK-NOT:  nop
 ; CHECK:      ret
 ; CHECK-NEXT: restore
   %0 = tail call i32 %f(i32 %a, i32 %b) nounwind
   ret i32 %0

 
 bb5:                                              ; preds = %bb, %entry
   %a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ]
 ;CHECK:      retl
 ;CHECK-NOT: restore
   ret i32 %a_addr.1.lcssa
 }
 
-define i32 @test_inlineasm(i32 %a) nounwind {
+define i32 @test_inlineasm(i32 %a) #0 {
 entry:
 ;CHECK-LABEL:      test_inlineasm:
 ;CHECK: cmp
 ;CHECK:      sethi
 ;CHECK:      !NO_APP
 ;CHECK-NEXT: ble
 ;CHECK-NEXT: mov
   tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
bb1:                                              ; preds = %entry
   ret i32 %2
 }
 
 declare i32 @foo(...)
 
 declare i32 @bar(i32)
 
 
-define i32 @test_implicit_def() nounwind {
+define i32 @test_implicit_def() #0 {
 entry:
 ;UNOPT-LABEL:       test_implicit_def:
 ;UNOPT:       call func
 ;UNOPT-NEXT:  nop
   %0 = tail call i32 @func(i32* undef) nounwind
   ret i32 0
 }
 
-define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {
+define i32 @prevent_o7_in_call_delay_slot(i32 %i0) #0 {
 entry:
 ;CHECK-LABEL:       prevent_o7_in_call_delay_slot:
 ;CHECK:       add %i0, 2, %o5
 ;CHECK:       add %i0, 3, %o7
 ;CHECK:       add %o5, %o7, %o0
 ;CHECK:       call bar
 ;CHECK-NEXT:  nop
   %0 = add nsw i32 %i0, 2

 ;CHECK-LABEL:  restore_add_imm:
 ;CHECK:  ret
 ;CHECK:  restore %o0, 20, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
   %1 = add nsw i32 %0, 20
   ret i32 %1
 }
 
-define i32 @restore_or(i32 %a) {
+define i32 @restore_or(i32 %a) #0 {
 entry:
 ;CHECK-LABEL:  restore_or:
 ;CHECK:  ret
 ;CHECK:  restore %g0, %o0, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
   ret i32 %0
 }
 

 ;CHECK-NOT: restore %g0, %g0, %g0
 ;CHECK:     restore
   %0 = tail call i32 @bar(i32 %a) nounwind
   %1 = icmp ne i32 %0, 0
   %2 = select i1 %1, i32 4096000, i32 0
   ret i32 %2
 }
 
+attributes #0 = { nounwind "disable-tail-calls"="true" }

llvm/test/CodeGen/SPARC/tailcall.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=sparc -verify-machineinstrs | FileCheck %s
+
+define i32 @simple_leaf(i32 %i) #0 {
+; CHECK-LABEL: simple_leaf:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    mov %o7, %g1
+; CHECK-NEXT:    call foo
+; CHECK-NEXT:    mov %g1, %o7
+entry:
+  %call = tail call i32 @foo(i32 %i)
+  ret i32 %call
+}
+
+define i32 @simple_standard(i32 %i) #1 {
+; CHECK-LABEL: simple_standard:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -96, %sp
+; CHECK-NEXT:    call foo
+; CHECK-NEXT:    restore
+entry:
+  %call = tail call i32 @foo(i32 %i)
+  ret i32 %call
+}
+
+define i32 @extra_arg_leaf(i32 %i) #0 {
+; CHECK-LABEL: extra_arg_leaf:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    mov 12, %o1
+; CHECK-NEXT:    mov %o7, %g1
+; CHECK-NEXT:    call foo2
+; CHECK-NEXT:    mov %g1, %o7
+entry:
+  %call = tail call i32 @foo2(i32 %i, i32 12)
+  ret i32 %call
+}
+
+define i32 @extra_arg_standard(i32 %i) #1 {
+; CHECK-LABEL: extra_arg_standard:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -96, %sp
+; CHECK-NEXT:    call foo2
+; CHECK-NEXT:    restore %g0, 12, %o1
+entry:
+  %call = tail call i32 @foo2(i32 %i, i32 12)
+  ret i32 %call
+}
+
+; Perform tail call optimization for external symbol.
+
+define void @caller_extern(i8* %src) optsize #0 {
+; CHECK-LABEL: caller_extern:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    sethi %hi(dest), %o1
+; CHECK-NEXT:    add %o1, %lo(dest), %o1
+; CHECK-NEXT:    mov 7, %o2
+; CHECK-NEXT:    mov %o0, %o3
+; CHECK-NEXT:    mov %o1, %o0
+; CHECK-NEXT:    mov %o3, %o1
+; CHECK-NEXT:    mov %o7, %g1
+; CHECK-NEXT:    call memcpy
+; CHECK-NEXT:    mov %g1, %o7
+entry:
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(
+    i8* getelementptr inbounds ([2 x i8],
+    [2 x i8]* @dest, i32 0, i32 0),
+    i8* %src, i32 7, i1 false)
+  ret void
+}
+
+; Perform tail call optimization for function pointer.
+
+define i32 @func_ptr_test(i32 ()* nocapture %func_ptr) #0 {
+; CHECK-LABEL: func_ptr_test:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    jmp %o0
+; CHECK-NEXT:    nop
+entry:
+  %call = tail call i32 %func_ptr() #1
+  ret i32 %call
+}
+
+define i32 @func_ptr_test2(i32 (i32, i32, i32)* nocapture %func_ptr,
+; CHECK-LABEL: func_ptr_test2:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -96, %sp
+; CHECK-NEXT:    mov 10, %i3
+; CHECK-NEXT:    mov %i0, %i4
+; CHECK-NEXT:    mov %i1, %i0
+; CHECK-NEXT:    jmp %i4
+; CHECK-NEXT:    restore %g0, %i3, %o1
+                           i32 %r, i32 %q) #1 {
+entry:
+  %call = tail call i32 %func_ptr(i32 %r, i32 10, i32 %q) #1
+  ret i32 %call
+}
+
+
+; Do not tail call optimize if stack is used to pass parameters.
+
+define i32 @caller_args() #0 {
+; CHECK-LABEL: caller_args:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -104, %sp
+; CHECK-NEXT:    mov 6, %i0
+; CHECK-NEXT:    mov %g0, %o0
+; CHECK-NEXT:    mov 1, %o1
+; CHECK-NEXT:    mov 2, %o2
+; CHECK-NEXT:    mov 3, %o3
+; CHECK-NEXT:    mov 4, %o4
+; CHECK-NEXT:    mov 5, %o5
+; CHECK-NEXT:    call foo7
+; CHECK-NEXT:    st %i0, [%sp+92]
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    restore %g0, %o0, %o0
+entry:
+  %r = tail call i32 @foo7(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
+  ret i32 %r
+}
+
+; Byval parameters hand the function a pointer directly into the stack area
+; we want to reuse during a tail call. Do not tail call optimize functions with
+; byval parameters.
+
+define i32 @caller_byval() #0 {
+; CHECK-LABEL: caller_byval:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -104, %sp
+; CHECK-NEXT:    ld [%fp+-4], %i0
+; CHECK-NEXT:    st %i0, [%fp+-8]
+; CHECK-NEXT:    call callee_byval
+; CHECK-NEXT:    add %fp, -8, %o0
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    restore %g0, %o0, %o0
+entry:
+  %a = alloca i32*
+  %r = tail call i32 @callee_byval(i32** byval(i32*) %a)
+  ret i32 %r
+}
+
+; Perform tail call optimization for sret function.
+
+define void @sret_test(%struct.a* noalias sret(%struct.a) %agg.result) #0 {
+; CHECK-LABEL: sret_test:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    mov %o7, %g1
+; CHECK-NEXT:    call sret_func
+; CHECK-NEXT:    mov %g1, %o7
+entry:
+  tail call void bitcast (void (%struct.a*)* @sret_func to
+                          void (%struct.a*)*)(%struct.a* sret(%struct.a) %agg.result)
+  ret void
+}
+
+; Do not tail call if either caller or callee returns
+; a struct and the other does not. Returning a large
+; struct will generate a memcpy as the tail function.
+
+define void @ret_large_struct(%struct.big* noalias sret(%struct.big) %agg.result) #0 {
+; CHECK-LABEL: ret_large_struct:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -96, %sp
+; CHECK-NEXT:    ld [%fp+64], %i0
+; CHECK-NEXT:    sethi %hi(bigstruct), %i1
+; CHECK-NEXT:    add %i1, %lo(bigstruct), %o1
+; CHECK-NEXT:    mov 400, %o2
+; CHECK-NEXT:    call memcpy
+; CHECK-NEXT:    mov %i0, %o0
+; CHECK-NEXT:    jmp %i7+12
+; CHECK-NEXT:    restore
+entry:
+  %0 = bitcast %struct.big* %agg.result to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 bitcast (%struct.big* @bigstruct to i8*), i32 400, i1 false)
+  ret void
+}
+
+; Test register + immediate pattern.
+
+define void @addri_test(i32 %ptr) #0 {
+; CHECK-LABEL: addri_test:
+; CHECK:       ! %bb.0: ! %entry
+; CHECK-NEXT:    jmp %o0+4
+; CHECK-NEXT:    nop
+entry:
+  %add = add nsw i32 %ptr, 4
+  %0 = inttoptr i32 %add to void ()*
+  tail call void %0() #1
+  ret void
+}
+
+%struct.a = type { i32, i32 }
+@dest = global [2 x i8] zeroinitializer
+
+%struct.big = type { [100 x i32] }
+@bigstruct = global %struct.big zeroinitializer
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1)
+declare void @sret_func(%struct.a* sret(%struct.a))
+declare i32 @callee_byval(i32** byval(i32*) %a)
+declare i32 @foo(i32)
+declare i32 @foo2(i32, i32)
+declare i32 @foo7(i32, i32, i32, i32, i32, i32, i32)
+
+attributes #0 = { nounwind "disable-tail-calls"="false"
+                  "frame-pointer"="none" }
+attributes #1 = { nounwind "disable-tail-calls"="false"
+                  "frame-pointer"="all" }