Diff 180816

lib/Target/Sparc/DelaySlotFiller.cpp

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines	Filler::findDelayInstr(MachineBasicBlock &MBB,
SmallSet<unsigned, 32> RegDefs;		SmallSet<unsigned, 32> RegDefs;
SmallSet<unsigned, 32> RegUses;		SmallSet<unsigned, 32> RegUses;
bool sawLoad = false;		bool sawLoad = false;
bool sawStore = false;		bool sawStore = false;

if (slot == MBB.begin())		if (slot == MBB.begin())
return MBB.end();		return MBB.end();

if (slot->getOpcode() == SP::RET \|\| slot->getOpcode() == SP::TLS_CALL)		unsigned Opc = slot->getOpcode();

		if (Opc == SP::RET \|\| Opc == SP::TLS_CALL)
return MBB.end();		return MBB.end();

if (slot->getOpcode() == SP::RETL) {		if (Opc == SP::RETL \|\| Opc == SP::TAIL_CALL \|\| Opc == SP::TAIL_CALLri) {
MachineBasicBlock::iterator J = slot;		MachineBasicBlock::iterator J = slot;
--J;		--J;

if (J->getOpcode() == SP::RESTORErr		if (J->getOpcode() == SP::RESTORErr
\|\| J->getOpcode() == SP::RESTOREri) {		\|\| J->getOpcode() == SP::RESTOREri) {
// change retl to ret.		// change retl to ret.
		if (Opc == SP::RETL)
slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));		slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
return J;		return J;
}		}
}		}

// Call's delay filler can def some of call's uses.		// Call's delay filler can def some of call's uses.
if (slot->isCall())		if (slot->isCall())
insertCallDefsUses(slot, RegDefs, RegUses);		insertCallDefsUses(slot, RegDefs, RegUses);
else		else
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines	bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)

unsigned structSizeOpNum = 0;		unsigned structSizeOpNum = 0;
switch (I->getOpcode()) {		switch (I->getOpcode()) {
default: llvm_unreachable("Unknown call opcode.");		default: llvm_unreachable("Unknown call opcode.");
case SP::CALL: structSizeOpNum = 1; break;		case SP::CALL: structSizeOpNum = 1; break;
case SP::CALLrr:		case SP::CALLrr:
case SP::CALLri: structSizeOpNum = 2; break;		case SP::CALLri: structSizeOpNum = 2; break;
case SP::TLS_CALL: return false;		case SP::TLS_CALL: return false;
		case SP::TAIL_CALLri:
		case SP::TAIL_CALL: return false;
}		}

const MachineOperand &MO = I->getOperand(structSizeOpNum);		const MachineOperand &MO = I->getOperand(structSizeOpNum);
if (!MO.isImm())		if (!MO.isImm())
return false;		return false;
StructSize = MO.getImm();		StructSize = MO.getImm();
return true;		return true;
}		}
▲ Show 20 Lines • Show All 139 Lines • Show Last 20 Lines

lib/Target/Sparc/SparcCallingConv.td

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines	def RetCC_Sparc64 : CallingConv<[

// Otherwise, return values are passed exactly like arguments.		// Otherwise, return values are passed exactly like arguments.
CCDelegateTo<CC_Sparc64>		CCDelegateTo<CC_Sparc64>
]>;		]>;

// Callee-saved registers are handled by the register window mechanism.		// Callee-saved registers are handled by the register window mechanism.
def CSR : CalleeSavedRegs<(add)> {		def CSR : CalleeSavedRegs<(add)> {
let OtherPreserved = (add (sequence "I%u", 0, 7),		let OtherPreserved = (add (sequence "I%u", 0, 7),
(sequence "L%u", 0, 7));		(sequence "L%u", 0, 7), O6);
}		}

// Callee-saved registers for calls with ReturnsTwice attribute.		// Callee-saved registers for calls with ReturnsTwice attribute.
def RTCSR : CalleeSavedRegs<(add)> {		def RTCSR : CalleeSavedRegs<(add)> {
let OtherPreserved = (add I6, I7);		let OtherPreserved = (add I6, I7);
}		}

lib/Target/Sparc/SparcFrameLowering.cpp

	Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines

	void SparcFrameLowering::emitEpilogue(MachineFunction &MF,			void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
	MachineBasicBlock &MBB) const {			MachineBasicBlock &MBB) const {
	SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();			SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
	MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();			MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
	const SparcInstrInfo &TII =			const SparcInstrInfo &TII =
	static_cast<const SparcInstrInfo >(MF.getSubtarget().getInstrInfo());			static_cast<const SparcInstrInfo >(MF.getSubtarget().getInstrInfo());
	DebugLoc dl = MBBI->getDebugLoc();			DebugLoc dl = MBBI->getDebugLoc();
	assert(MBBI->getOpcode() == SP::RETL &&			assert((MBBI->getOpcode() == SP::RETL \|\| MBBI->getOpcode() == SP::TAIL_CALL \|\|
	"Can only put epilog before 'retl' instruction!");			MBBI->getOpcode() == SP::TAIL_CALLri) &&
				"Can only put epilog before 'retl' or 'tail_call' instruction!");
	if (!FuncInfo->isLeafProc()) {			if (!FuncInfo->isLeafProc()) {
	BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)			BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
	.addReg(SP::G0);			.addReg(SP::G0);
	return;			return;
	}			}
	MachineFrameInfo &MFI = MF.getFrameInfo();			MachineFrameInfo &MFI = MF.getFrameInfo();

	int NumBytes = (int) MFI.getStackSize();			int NumBytes = (int) MFI.getStackSize();
	if (NumBytes == 0)			if (NumBytes != 0)
	return;

	emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);			emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);

				// Preserve return address in %o7
				if (MBBI->getOpcode() == SP::TAIL_CALL) {
				MBB.addLiveIn(SP::O7);
				BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::G1)
				.addReg(SP::G0)
				.addReg(SP::O7);
				BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::O7)
				.addReg(SP::G0)
				.addReg(SP::G1);
				}
	}			}

	bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {			bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
	// Reserve call frame if there are no variable sized objects on the stack.			// Reserve call frame if there are no variable sized objects on the stack.
	return !MF.getFrameInfo().hasVarSizedObjects();			return !MF.getFrameInfo().hasVarSizedObjects();
	}			}

	// hasFP - Return true if the specified function should have a dedicated frame			// hasFP - Return true if the specified function should have a dedicated frame
	▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

lib/Target/Sparc/SparcISelLowering.h

Show All 39 Lines	enum NodeType : unsigned {
FTOX, // FP to Int64 within a FP register.		FTOX, // FP to Int64 within a FP register.
XTOF, // Int64 to FP within a FP register.		XTOF, // Int64 to FP within a FP register.

CALL, // A call instruction.		CALL, // A call instruction.
RET_FLAG, // Return with a flag operand.		RET_FLAG, // Return with a flag operand.
GLOBAL_BASE_REG, // Global base reg for PIC.		GLOBAL_BASE_REG, // Global base reg for PIC.
FLUSHW, // FLUSH register windows to stack.		FLUSHW, // FLUSH register windows to stack.

		TAIL_CALL, // Tail call

TLS_ADD, // For Thread Local Storage (TLS).		TLS_ADD, // For Thread Local Storage (TLS).
TLS_LD,		TLS_LD,
TLS_CALL		TLS_CALL
};		};
}		}

class SparcTargetLowering : public TargetLowering {		class SparcTargetLowering : public TargetLowering {
const SparcSubtarget *Subtarget;		const SparcSubtarget *Subtarget;
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines	public:

SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;		SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;

SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,		SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
SelectionDAG &DAG) const;		SelectionDAG &DAG) const;

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;		SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;

		bool IsEligibleForTailCallOptimization(CCState &CCInfo,
		CallLoweringInfo &CLI,
		MachineFunction &MF) const;

bool ShouldShrinkFPConstant(EVT VT) const override {		bool ShouldShrinkFPConstant(EVT VT) const override {
// Do not shrink FP constpool if VT == MVT::f128.		// Do not shrink FP constpool if VT == MVT::f128.
// (ldd, call _Q_fdtoq) is more expensive than two ldds.		// (ldd, call _Q_fdtoq) is more expensive than two ldds.
return VT != MVT::f128;		return VT != MVT::f128;
}		}

bool shouldInsertFencesForAtomic(const Instruction *I) const override {		bool shouldInsertFencesForAtomic(const Instruction *I) const override {
// FIXME: We insert fences for each atomics and generate		// FIXME: We insert fences for each atomics and generate
Show All 17 Lines

lib/Target/Sparc/SparcISelLowering.cpp

Show First 20 Lines • Show All 706 Lines • ▼ Show 20 Lines	if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
CalleeFn = M->getFunction(CalleeName);		CalleeFn = M->getFunction(CalleeName);
}		}

if (!CalleeFn)		if (!CalleeFn)
return false;		return false;
return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);		return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
}		}

		/// IsEligibleForTailCallOptimization - Check whether the call is eligible
		/// for tail call optimization.
		bool SparcTargetLowering::IsEligibleForTailCallOptimization(
		CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {

		auto &Outs = CLI.Outs;
		auto &Caller = MF.getFunction();

		// Do not tail call opt functions with "disable-tail-calls" attribute.
		if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
		return false;

		// Do not tail call opt if the stack is used to pass parameters.
		if (CCInfo.getNextStackOffset() != 0)
		return false;

		// The 32-bit ABI requires an unimp instruction after the delay slot of
		// a call to a function that returns a struct. Do not tail call opt if
		// either the callee or caller returns a struct and the other does not.
		jrtc27Unsubmitted Not Done Reply Inline Actions Whilst correct for now given the 64-bit lowering does not support tail calls, this condition only applies to the 32-bit SPARC ABI, as the 64-bit ABI does not have the extra `unimp` after the delay slot for struct-returning functions. Perhaps worth adding a comment here so this doesn't get forgotten? jrtc27: Whilst correct for now given the 64-bit lowering does not support tail calls, this condition…
		dcedermanAuthorUnsubmitted Done Reply Inline Actions Ok, I'll add a condition to only disallow this on 32-bit SPARC. dcederman: Ok, I'll add a condition to only disallow this on 32-bit SPARC.
		if (!Subtarget->is64Bit() && !Outs.empty() &&
		(Caller.hasStructRetAttr() != Outs[0].Flags.isSRet()))
		return false;

		// Byval parameters hand the function a pointer directly into the stack area
		// we want to reuse during a tail call.
		for (auto &Arg : Outs)
		if (Arg.Flags.isByVal())
		return false;

		return true;
		}

// Lower a call for the 32-bit ABI.		// Lower a call for the 32-bit ABI.
SDValue		SDValue
SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,		SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const {		SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;		SelectionDAG &DAG = CLI.DAG;
SDLoc &dl = CLI.DL;		SDLoc &dl = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;		SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;		SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;		SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;		SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;		SDValue Callee = CLI.Callee;
bool &isTailCall = CLI.IsTailCall;		bool &isTailCall = CLI.IsTailCall;
CallingConv::ID CallConv = CLI.CallConv;		CallingConv::ID CallConv = CLI.CallConv;
bool isVarArg = CLI.IsVarArg;		bool isVarArg = CLI.IsVarArg;

// Sparc target does not yet support tail call optimization.
isTailCall = false;

// Analyze operands of the call, assigning locations to each operand.		// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;		SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,		CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());		*DAG.getContext());
CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);		CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);

		isTailCall = isTailCall && IsEligibleForTailCallOptimization(
		CCInfo, CLI, DAG.getMachineFunction());

// Get the size of the outgoing arguments stack space requirement.		// Get the size of the outgoing arguments stack space requirement.
unsigned ArgsSize = CCInfo.getNextStackOffset();		unsigned ArgsSize = CCInfo.getNextStackOffset();

// Keep stack frames 8-byte aligned.		// Keep stack frames 8-byte aligned.
ArgsSize = (ArgsSize+7) & ~7;		ArgsSize = (ArgsSize+7) & ~7;

MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();		MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();

Show All 21 Lines	if (Size > 0U) {
ByValArgs.push_back(FIPtr);		ByValArgs.push_back(FIPtr);
}		}
else {		else {
SDValue nullVal;		SDValue nullVal;
ByValArgs.push_back(nullVal);		ByValArgs.push_back(nullVal);
}		}
}		}

		assert(!isTailCall \|\| ArgsSize == 0);

		if (!isTailCall)
Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);		Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);

SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;		SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;		SmallVector<SDValue, 8> MemOpChains;

const unsigned StackOffset = 92;		const unsigned StackOffset = 92;
bool hasStructRetAttr = false;		bool hasStructRetAttr = false;
unsigned SRetArgSize = 0;		unsigned SRetArgSize = 0;
// Walk the register/memloc assignments, inserting copies/loads.		// Walk the register/memloc assignments, inserting copies/loads.
Show All 28 Lines	case CCValAssign::AExt:
break;		break;
case CCValAssign::BCvt:		case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);		Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
break;		break;
}		}

if (Flags.isSRet()) {		if (Flags.isSRet()) {
assert(VA.needsCustom());		assert(VA.needsCustom());

		if (isTailCall)
		continue;

// store SRet argument in %sp+64		// store SRet argument in %sp+64
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);		SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getIntPtrConstant(64, dl);		SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);		PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(		MemOpChains.push_back(
DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));		DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
hasStructRetAttr = true;		hasStructRetAttr = true;
// sret only allowed on first argument		// sret only allowed on first argument
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines	if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);		Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);

// Build a sequence of copy-to-reg nodes chained together with token		// Build a sequence of copy-to-reg nodes chained together with token
// chain and flag operands which copy the outgoing args into registers.		// chain and flag operands which copy the outgoing args into registers.
// The InFlag in necessary since all emitted instructions must be		// The InFlag in necessary since all emitted instructions must be
// stuck together.		// stuck together.
SDValue InFlag;		SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {		for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
unsigned Reg = toCallerWindow(RegsToPass[i].first);		unsigned Reg = RegsToPass[i].first;
		if (!isTailCall)
		Reg = toCallerWindow(Reg);
Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);		Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);		InFlag = Chain.getValue(1);
}		}

bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);		bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);

// If the callee is a GlobalAddress node (quite common, every direct call is)		// If the callee is a GlobalAddress node (quite common, every direct call is)
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.		// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.		// Likewise ExternalSymbol -> TargetExternalSymbol.
unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;		unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))		if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);		Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))		else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);		Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);

// Returns a chain & a flag for retval copy to use		// Returns a chain & a flag for retval copy to use
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);		SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SmallVector<SDValue, 8> Ops;		SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);		Ops.push_back(Chain);
Ops.push_back(Callee);		Ops.push_back(Callee);
if (hasStructRetAttr)		if (hasStructRetAttr)
Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));		Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)		for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),		unsigned Reg = RegsToPass[i].first;
RegsToPass[i].second.getValueType()));		if (!isTailCall)
		Reg = toCallerWindow(Reg);
		Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
		}

// Add a register mask operand representing the call-preserved registers.		// Add a register mask operand representing the call-preserved registers.
const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();		const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
const uint32_t *Mask =		const uint32_t *Mask =
((hasReturnsTwice)		((hasReturnsTwice)
? TRI->getRTCallPreservedMask(CallConv)		? TRI->getRTCallPreservedMask(CallConv)
: TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));		: TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
assert(Mask && "Missing call preserved mask for calling convention");		assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask));		Ops.push_back(DAG.getRegisterMask(Mask));

if (InFlag.getNode())		if (InFlag.getNode())
Ops.push_back(InFlag);		Ops.push_back(InFlag);

		if (isTailCall) {
		DAG.getMachineFunction().getFrameInfo().setHasTailCall();
		return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
		}

Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);		Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
InFlag = Chain.getValue(1);		InFlag = Chain.getValue(1);

Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),		Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
DAG.getIntPtrConstant(0, dl, true), InFlag, dl);		DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
InFlag = Chain.getValue(1);		InFlag = Chain.getValue(1);

// Assign locations to each value returned by this call.		// Assign locations to each value returned by this call.
▲ Show 20 Lines • Show All 852 Lines • ▼ Show 20 Lines	const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
case SPISD::XTOF: return "SPISD::XTOF";		case SPISD::XTOF: return "SPISD::XTOF";
case SPISD::CALL: return "SPISD::CALL";		case SPISD::CALL: return "SPISD::CALL";
case SPISD::RET_FLAG: return "SPISD::RET_FLAG";		case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";		case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
case SPISD::FLUSHW: return "SPISD::FLUSHW";		case SPISD::FLUSHW: return "SPISD::FLUSHW";
case SPISD::TLS_ADD: return "SPISD::TLS_ADD";		case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
case SPISD::TLS_LD: return "SPISD::TLS_LD";		case SPISD::TLS_LD: return "SPISD::TLS_LD";
case SPISD::TLS_CALL: return "SPISD::TLS_CALL";		case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
		case SPISD::TAIL_CALL: return "SPISD::TAIL_CALL";
}		}
return nullptr;		return nullptr;
}		}

EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,		EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
EVT VT) const {		EVT VT) const {
if (!VT.isVector())		if (!VT.isVector())
return MVT::i32;		return MVT::i32;
▲ Show 20 Lines • Show All 1,567 Lines • Show Last 20 Lines

lib/Target/Sparc/SparcInstrInfo.td

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,		def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;		[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;

def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;		def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
def call : SDNode<"SPISD::CALL", SDT_SPCall,		def call : SDNode<"SPISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,		[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>;		SDNPVariadic]>;

		def tailcall : SDNode<"SPISD::TAIL_CALL", SDT_SPCall,
		[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
		SDNPVariadic]>;

def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;		def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,		def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;		[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;

def flushw : SDNode<"SPISD::FLUSHW", SDTNone,		def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
[SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;		[SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;

def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;		def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
▲ Show 20 Lines • Show All 1,100 Lines • ▼ Show 20 Lines	def TLS_CALL : InstSP<(outs),
IIC_jmp_or_call> {		IIC_jmp_or_call> {
bits<30> disp;		bits<30> disp;
let op = 1;		let op = 1;
let Inst{29-0} = disp;		let Inst{29-0} = disp;
}		}
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
		// Instructions for tail calls.
		//===----------------------------------------------------------------------===//
		let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1,
		isTerminator = 1, isBarrier = 1 in {
		def TAIL_CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
		"call $disp",
		[(tailcall tglobaladdr:$disp)]> {
		bits<30> disp;
		let op = 1;
		let Inst{29-0} = disp;
		}
		}

		def : Pat<(tailcall (iPTR texternalsym:$dst)),
		(TAIL_CALL texternalsym:$dst)>;

		let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1, isTerminator = 1,
		isBarrier = 1, rd = 0 in {
		def TAIL_CALLri : F3_2<2, 0b111000,
		(outs), (ins MEMri:$ptr, variable_ops),
		"jmp $ptr",
		[(tailcall ADDRri:$ptr)]>;
		}

		//===----------------------------------------------------------------------===//
// V9 Instructions		// V9 Instructions
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

// V9 Conditional Moves.		// V9 Conditional Moves.
let Predicates = [HasV9], Constraints = "$f = $rd" in {		let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.		// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
let Uses = [ICC], intcc = 1, cc = 0b00 in {		let Uses = [ICC], intcc = 1, cc = 0b00 in {
def MOVICCrr		def MOVICCrr
▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines

test/CodeGen/SPARC/2011-01-11-Call.ll

	Show All 14 Lines
	; V9: save %sp			; V9: save %sp
	; V9: call foo			; V9: call foo
	; V9-NEXT: nop			; V9-NEXT: nop
	; V9: call bar			; V9: call bar
	; V9-NEXT: nop			; V9-NEXT: nop
	; V9: ret			; V9: ret
	; V9-NEXT: restore			; V9-NEXT: restore

	define void @test() nounwind {			define void @test() #0 {
	entry:			entry:
	%0 = tail call i32 (...) @foo() nounwind			%0 = tail call i32 (...) @foo() nounwind
	tail call void (...) @bar() nounwind			tail call void (...) @bar() nounwind
	ret void			ret void
	}			}

	declare i32 @foo(...)			declare i32 @foo(...)

	declare void @bar(...)			declare void @bar(...)


	; V8-LABEL: test_tail_call_with_return			; V8-LABEL: test_tail_call_with_return
	; V8: save %sp			; V8: mov %o7, %g1
	; V8: call foo			; V8-NEXT: call foo
	; V8-NEXT: nop			; V8-NEXT: mov %g1, %o7
	; V8: ret
	; V8-NEXT: restore %g0, %o0, %o0

	; V9-LABEL: test_tail_call_with_return			; V9-LABEL: test_tail_call_with_return
	; V9: save %sp			; V9: save %sp
	; V9: call foo			; V9: call foo
	; V9-NEXT: nop			; V9-NEXT: nop
	; V9: ret			; V9: ret
	; V9-NEXT: restore %g0, %o0, %o0			; V9-NEXT: restore %g0, %o0, %o0

	define i32 @test_tail_call_with_return() nounwind {			define i32 @test_tail_call_with_return() nounwind {
	entry:			entry:
	%0 = tail call i32 (...) @foo() nounwind			%0 = tail call i32 (...) @foo() nounwind
	ret i32 %0			ret i32 %0
	}			}

				attributes #0 = { nounwind "disable-tail-calls"="true" }

test/CodeGen/SPARC/2011-01-19-DelaySlot.ll

;RUN: llc -march=sparc < %s -verify-machineinstrs \| FileCheck %s		;RUN: llc -march=sparc < %s -verify-machineinstrs \| FileCheck %s
;RUN: llc -march=sparc -O0 < %s -verify-machineinstrs \| FileCheck %s -check-prefix=UNOPT		;RUN: llc -march=sparc -O0 < %s -verify-machineinstrs \| FileCheck %s -check-prefix=UNOPT

target triple = "sparc-unknown-linux-gnu"		target triple = "sparc-unknown-linux-gnu"

define i32 @test(i32 %a) nounwind {		define i32 @test(i32 %a) #0 {
entry:		entry:
; CHECK: test		; CHECK: test
; CHECK: call bar		; CHECK: call bar
; CHECK-NOT: nop		; CHECK-NOT: nop
; CHECK: ret		; CHECK: ret
; CHECK-NEXT: restore		; CHECK-NEXT: restore
%0 = tail call i32 @bar(i32 %a) nounwind		%0 = tail call i32 @bar(i32 %a) nounwind
ret i32 %0		ret i32 %0
}		}

define i32 @test_jmpl(i32 (i32, i32)* nocapture %f, i32 %a, i32 %b) nounwind {		define i32 @test_jmpl(i32 (i32, i32)* nocapture %f, i32 %a, i32 %b) #0 {
entry:		entry:
; CHECK: test_jmpl		; CHECK: test_jmpl
; CHECK: call		; CHECK: call
; CHECK-NOT: nop		; CHECK-NOT: nop
; CHECK: ret		; CHECK: ret
; CHECK-NEXT: restore		; CHECK-NEXT: restore
%0 = tail call i32 %f(i32 %a, i32 %b) nounwind		%0 = tail call i32 %f(i32 %a, i32 %b) nounwind
ret i32 %0		ret i32 %0
Show All 22 Lines

bb5: ; preds = %bb, %entry		bb5: ; preds = %bb, %entry
%a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ]		%a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ]
;CHECK: retl		;CHECK: retl
;CHECK-NOT: restore		;CHECK-NOT: restore
ret i32 %a_addr.1.lcssa		ret i32 %a_addr.1.lcssa
}		}

define i32 @test_inlineasm(i32 %a) nounwind {		define i32 @test_inlineasm(i32 %a) #0 {
entry:		entry:
;CHECK-LABEL: test_inlineasm:		;CHECK-LABEL: test_inlineasm:
;CHECK: cmp		;CHECK: cmp
;CHECK: sethi		;CHECK: sethi
;CHECK: !NO_APP		;CHECK: !NO_APP
;CHECK-NEXT: ble		;CHECK-NEXT: ble
;CHECK-NEXT: mov		;CHECK-NEXT: mov
tail call void asm sideeffect "sethi 0, %g0", ""() nounwind		tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
Show All 9 Lines	bb1: ; preds = %entry
ret i32 %2		ret i32 %2
}		}

declare i32 @foo(...)		declare i32 @foo(...)

declare i32 @bar(i32)		declare i32 @bar(i32)


define i32 @test_implicit_def() nounwind {		define i32 @test_implicit_def() #0 {
entry:		entry:
;UNOPT-LABEL: test_implicit_def:		;UNOPT-LABEL: test_implicit_def:
;UNOPT: call func		;UNOPT: call func
;UNOPT-NEXT: nop		;UNOPT-NEXT: nop
%0 = tail call i32 @func(i32* undef) nounwind		%0 = tail call i32 @func(i32* undef) nounwind
ret i32 0		ret i32 0
}		}

define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {		define i32 @prevent_o7_in_call_delay_slot(i32 %i0) #0 {
entry:		entry:
;CHECK-LABEL: prevent_o7_in_call_delay_slot:		;CHECK-LABEL: prevent_o7_in_call_delay_slot:
;CHECK: add %i0, 2, %o5		;CHECK: add %i0, 2, %o5
;CHECK: add %i0, 3, %o7		;CHECK: add %i0, 3, %o7
;CHECK: add %o5, %o7, %o0		;CHECK: add %o5, %o7, %o0
;CHECK: call bar		;CHECK: call bar
;CHECK-NEXT: nop		;CHECK-NEXT: nop
%0 = add nsw i32 %i0, 2		%0 = add nsw i32 %i0, 2
Show All 23 Lines
;CHECK-LABEL: restore_add_imm:		;CHECK-LABEL: restore_add_imm:
;CHECK: ret		;CHECK: ret
;CHECK: restore %o0, 20, %o0		;CHECK: restore %o0, 20, %o0
%0 = tail call i32 @bar(i32 %a) nounwind		%0 = tail call i32 @bar(i32 %a) nounwind
%1 = add nsw i32 %0, 20		%1 = add nsw i32 %0, 20
ret i32 %1		ret i32 %1
}		}

define i32 @restore_or(i32 %a) {		define i32 @restore_or(i32 %a) #0 {
entry:		entry:
;CHECK-LABEL: restore_or:		;CHECK-LABEL: restore_or:
;CHECK: ret		;CHECK: ret
;CHECK: restore %g0, %o0, %o0		;CHECK: restore %g0, %o0, %o0
%0 = tail call i32 @bar(i32 %a) nounwind		%0 = tail call i32 @bar(i32 %a) nounwind
ret i32 %0		ret i32 %0
}		}

Show All 39 Lines
;CHECK-NOT: restore %g0, %g0, %g0		;CHECK-NOT: restore %g0, %g0, %g0
;CHECK: restore		;CHECK: restore
%0 = tail call i32 @bar(i32 %a) nounwind		%0 = tail call i32 @bar(i32 %a) nounwind
%1 = icmp ne i32 %0, 0		%1 = icmp ne i32 %0, 0
%2 = select i1 %1, i32 4096000, i32 0		%2 = select i1 %1, i32 4096000, i32 0
ret i32 %2		ret i32 %2
}		}

		attributes #0 = { nounwind "disable-tail-calls"="true" }

test/CodeGen/SPARC/tailcall.ll

This file was added.

				; RUN: llc < %s -mtriple=sparc -verify-machineinstrs \| FileCheck %s

				; CHECK-LABEL: simple_leaf
				; CHECK: mov %o7, %g1
				; CHECK: call foo
				; CHECK: mov %g1, %o7

				define i32 @simple_leaf(i32 %i) #0 {
				entry:
				%call = tail call i32 @foo(i32 %i)
				ret i32 %call
				}

				; CHECK-LABEL: simple_standard
				; CHECK: save %sp, -96, %sp
				; CHECK: call foo
				; CHECK: restore

				define i32 @simple_standard(i32 %i) #1 {
				entry:
				%call = tail call i32 @foo(i32 %i)
				ret i32 %call
				}

				; CHECK-LABEL: extra_arg_leaf
				; CHECK: mov 12, %o1
				; CHECK: mov %o7, %g1
				; CHECK: call foo2
				; CHECK: mov %g1, %o7

				define i32 @extra_arg_leaf(i32 %i) #0 {
				entry:
				%call = tail call i32 @foo2(i32 %i, i32 12)
				ret i32 %call
				}

				; CHECK-LABEL: extra_arg_standard
				; CHECK: save %sp, -96, %sp
				; CHECK: call foo2
				; CHECK: restore %g0, 12, %o1

				define i32 @extra_arg_standard(i32 %i) #1 {
				entry:
				%call = tail call i32 @foo2(i32 %i, i32 12)
				ret i32 %call
				}

				; Perform tail call optimization for external symbol.

				; CHECK-LABEL: caller_extern
				; CHECK: mov %o7, %g1
				; CHECK: call memcpy
				; CHECK: mov %g1, %o7

				define void @caller_extern(i8* %src) optsize #0 {
				entry:
				tail call void @llvm.memcpy.p0i8.p0i8.i32(
				i8* getelementptr inbounds ([2 x i8],
				[2 x i8]* @dest, i32 0, i32 0),
				i8* %src, i32 7, i1 false)
				ret void
				}

				; Perform tail call optimization for function pointer.

				; CHECK-LABEL: func_ptr_test
				; CHECK: jmp %o0
				; CHECK: nop

				define i32 @func_ptr_test(i32 ()* nocapture %func_ptr) #0 {
				entry:
				%call = tail call i32 %func_ptr() #1
				ret i32 %call
				}

				; CHECK-LABEL: func_ptr_test2
				; CHECK: save %sp, -96, %sp
				; CHECK: mov 10, %i3
				; CHECK: mov %i0, %i4
				; CHECK: mov %i1, %i0
				; CHECK: jmp %i4
				; CHECK: restore %g0, %i3, %o1
				define i32 @func_ptr_test2(i32 (i32, i32, i32)* nocapture %func_ptr,
				i32 %r, i32 %q) #1 {
				entry:
				%call = tail call i32 %func_ptr(i32 %r, i32 10, i32 %q) #1
				ret i32 %call
				}


				; Do not tail call optimize if stack is used to pass parameters.

				; CHECK-LABEL: caller_args
				; CHECK: ret

				define i32 @caller_args() #0 {
				entry:
				%r = tail call i32 @foo7(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
				ret i32 %r
				}

				; Byval parameters hand the function a pointer directly into the stack area
				; we want to reuse during a tail call. Do not tail call optimize functions with
				; byval parameters.

				; CHECK-LABEL: caller_byval
				; CHECK: ret

				define i32 @caller_byval() #0 {
				entry:
				%a = alloca i32*
				%r = tail call i32 @callee_byval(i32** byval %a)
				ret i32 %r
				}

				; Perform tail call optimization for sret function.

				; CHECK-LABEL: sret_test
				; CHECK: mov %o7, %g1
				; CHECK: call sret_func
				; CHECK: mov %g1, %o7

				define void @sret_test(%struct.a* noalias sret %agg.result) #0 {
				entry:
				tail call void bitcast (void (%struct.a) @sret_func to
				void (%struct.a))(%struct.a* sret %agg.result)
				ret void
				}

				; Do not tail call if either caller or callee returns
				; a struct and the other does not. Returning a large
				; struct will generate a memcpy as the tail function.

				; CHECK-LABEL: ret_large_struct
				; CHECK: jmp %i7+12

				define void @ret_large_struct(%struct.big* noalias sret %agg.result) #0 {
				entry:
				%0 = bitcast %struct.big* %agg.result to i8*
				tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 bitcast (%struct.big* @bigstruct to i8*), i32 400, i1 false)
				ret void
				}

				; Test register + immediate pattern.

				; CHECK-LABEL: addri_test
				; CHECK: jmp %o0+4

				define void @addri_test(i32 %ptr) #0 {
				entry:
				%add = add nsw i32 %ptr, 4
				%0 = inttoptr i32 %add to void ()*
				tail call void %0() #1
				ret void
				}

				%struct.a = type { i32, i32 }
				@dest = global [2 x i8] zeroinitializer

				%struct.big = type { [100 x i32] }
				@bigstruct = global %struct.big zeroinitializer

				declare void @llvm.memcpy.p0i8.p0i8.i32(i8, i8, i32, i1)
				declare void @sret_func(%struct.a* sret)
				declare i32 @callee_byval(i32** byval %a)
				declare i32 @foo(i32)
				declare i32 @foo2(i32, i32)
				declare i32 @foo7(i32, i32, i32, i32, i32, i32, i32)

				attributes #0 = { nounwind "disable-tail-calls"="false"
				"no-frame-pointer-elim"="false" }
				attributes #1 = { nounwind "disable-tail-calls"="false"
				"no-frame-pointer-elim"="true" }

This is an archive of the discontinued LLVM Phabricator instance.

[Sparc] Add tail call support
ClosedPublic

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Diff Detail

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Diff 180816

lib/Target/Sparc/DelaySlotFiller.cpp

lib/Target/Sparc/SparcCallingConv.td

lib/Target/Sparc/SparcFrameLowering.cpp

lib/Target/Sparc/SparcISelLowering.h

lib/Target/Sparc/SparcISelLowering.cpp

lib/Target/Sparc/SparcInstrInfo.td

test/CodeGen/SPARC/2011-01-11-Call.ll

test/CodeGen/SPARC/2011-01-19-DelaySlot.ll

test/CodeGen/SPARC/tailcall.ll

This is an archive of the discontinued LLVM Phabricator instance.

[Sparc] Add tail call supportClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 180816

lib/Target/Sparc/DelaySlotFiller.cpp

lib/Target/Sparc/SparcCallingConv.td

lib/Target/Sparc/SparcFrameLowering.cpp

lib/Target/Sparc/SparcISelLowering.h

lib/Target/Sparc/SparcISelLowering.cpp

lib/Target/Sparc/SparcInstrInfo.td

test/CodeGen/SPARC/2011-01-11-Call.ll

test/CodeGen/SPARC/2011-01-19-DelaySlot.ll

test/CodeGen/SPARC/tailcall.ll

[Sparc] Add tail call support
ClosedPublic