[GISel]: Remove an incorrect assert in CallLowering

[aditya_nandakumar]

Summary

Asserting if any extend of vectors should be up to the target's legalizer/target specific code.

I suspect this was moved around from AArch64 during refactoring and stayed as is in generic code.

This assert fires if we compile the following llvm ir
define <4 x i1> @foo() {
entry:

ret <4 x i1> zeroinitializer

}
llc -mtriple=x86_64-linux-gnu -o - -global-isel

If required I can add a test that IRTranslation for above doesn't crash and produces ANYEXT. I haven't added as this seemed overkill for removing an assert.

[dsanders]

If required I can add a test that IRTranslation for above doesn't crash and produces ANYEXT. I haven't added as this seemed overkill for removing an assert.

It uncovers a previously unsupported case so I think we should have a testcase for it

[aditya_nandakumar]

Thanks Daniel. Added test case.

[dsanders]

Sorry for being so slow to get back to you on this. I hadn't realized I didn't say 'LGTM with a test case' or something to that effect.

LGTM

[aditya_nandakumar]

Submitted in r343325

lib/CodeGen/GlobalISel/CallLowering.cpp

unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
   switch (VA.getLocInfo()) {
   default: break;
   case CCValAssign::Full:
   case CCValAssign::BCvt:
     // FIXME: bitconverting between vector types may or may not be a
     // nop in big-endian situations.
     return ValReg;
   case CCValAssign::AExt: {
-    assert(!VA.getLocVT().isVector() && "unexpected vector extend");
     auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
     return MIB->getOperand(0).getReg();
   }
   case CCValAssign::SExt: {
     unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
     MIRBuilder.buildSExt(NewReg, ValReg);
     return NewReg;
   }
   case CCValAssign::ZExt: {
     unsigned NewReg = MRI.createGenericVirtualRegister(LocTy);
     MIRBuilder.buildZExt(NewReg, ValReg);
     return NewReg;
   }
   }
   llvm_unreachable("unable to extend register");
 }