[llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC.

[mattd]

Summary

This patch introduces llvm-mca as a library. The driver (llvm-mca.cpp), views, and stats, are not part of the library.
Those are separate components that are not required for the functioning of llvm-mca.

The directory has been organized as follows:
All library source files now reside in:

• lib/HardwareUnits/ - All subclasses of HardwareUnit (these represent the simulated hardware components of a backend). (LSUnit does not inherit from HardwareUnit, but Scheduler does which uses LSUnit).
• lib/Stages/ - All subclasses of the pipeline stages.
• lib/ - This is the root of the library and contains library code that does not fit into the Stages or HardwareUnit subdirs.

All library header files now reside in the include directory and mimic the same layout as the lib directory mentioned above.

In the (near) future we would like to move the library (include and lib) contents from tools and into the core of llvm somewhere.
That change would allow various analysis and optimization passes to make use of MCA functionality for things like cost modeling.

I left all of the non-library code just where it has always been, in the root of the llvm-mca directory.
The include directives for the non-library source file have been updated to refer to the llvm-mca library headers.
I updated the llvm-mca/CMakeLists.txt file to include the library headers, but I made the non-library code
explicitly reference the library's 'include' directory. Once we eventually (hopefully) migrate the MCA library
components into llvm the include directives used by the non-library source files will be updated to point to the
proper location in llvm.

[mattd]

tools/llvm-mca/PipelinePrinter.h

21 ↗

(On Diff #161349)

As I mentioned in the description. Once we move llvm-mca into a core llvm library, these 'include/' subdirectories will be updated to reference that location. For now, I left the include subdirectory explicit, even though the CMake file already includes that subdirectory.

[mattd]

• Tossed in an LLVMBuild.txt for the library.
• Added library dependencies to the cmake.

[andreadb]

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

I would like to place the Views and Stats into separate (non-library) directories, just to keep things better organized, but that would be a separate patch.

Any reasons why it cannot be done as part of this patch?

[mattd]

In D50929#1205986, @andreadb wrote:

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

I am fine with that, I'll move those utility pieces outside of the library.

I would like to place the Views and Stats into separate (non-library) directories, just to keep things better organized, but that would be a separate patch.

Any reasons why it cannot be done as part of this patch?

I was just trying to isolate this patch to the addition of a library, but I am happy to move those files in this patch too.

[mattd]

• Updated per comments from the last spin:
  • Moved CodeRegion out of the library.
  • Added Views and Stats directories to cleanup the layout (Views and Stats are not part of the library).

[mattd]

• Move the Resource classes into their own file.

[mattd]

Rebased this diff after reorganizing the llvm-mca directory some.

[andreadb]

Hi Matt.

Thanks for this refactoring.
The change looks good to me.

Please update https://bugs.llvm.org/show_bug.cgi?id=37696 once you have committed this change. Thanks!

(also: unrelated to this patch. When you have time, could you please update https://bugs.llvm.org/show_bug.cgi?id=37835 ?).

-Andrea

tools/llvm-mca/CMakeLists.txt

+include_directories(include)
+
 set(LLVM_LINK_COMPONENTS
   AllTargetsAsmPrinters
   AllTargetsAsmParsers
   AllTargetsDescs
   AllTargetsDisassemblers
   AllTargetsInfos
   MC
   MCParser
   Support
   )
 
 add_llvm_tool(llvm-mca
   llvm-mca.cpp
   CodeRegion.cpp
-  Context.cpp
-  DispatchStage.cpp
-  ExecuteStage.cpp
-  FetchStage.cpp
-  HWEventListener.cpp
-  HardwareUnit.cpp
-  InstrBuilder.cpp
-  Instruction.cpp
-  InstructionTables.cpp
-  LSUnit.cpp
-  Pipeline.cpp
   PipelinePrinter.cpp
-  RegisterFile.cpp
-  ResourceManager.cpp
-  RetireControlUnit.cpp
-  RetireStage.cpp
-  Scheduler.cpp
-  Stage.cpp
-  Support.cpp
   Views/DispatchStatistics.cpp
   Views/InstructionInfoView.cpp
   Views/RegisterFileStatistics.cpp
   Views/ResourcePressureView.cpp
   Views/RetireControlUnitStatistics.cpp
   Views/SchedulerStatistics.cpp
   Views/SummaryView.cpp
   Views/TimelineView.cpp
   Views/View.cpp
   )
+
+set(LLVM_MCA_SOURCE_DIR ${CURRENT_SOURCE_DIR})
+add_subdirectory(lib)
+target_link_libraries(llvm-mca PRIVATE LLVMMCA)

tools/llvm-mca/include/Context.h

 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
 #define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include "InstrBuilder.h"
 #include "Pipeline.h"
 #include "SourceMgr.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <memory>
 

tools/llvm-mca/include/HardwareUnits/LSUnit.h

 /// A Load/Store unit class that models load/store queues and that implements
 /// a simple weak memory consistency model.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_LSUNIT_H
 #define LLVM_TOOLS_LLVM_MCA_LSUNIT_H
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include <set>
 
 namespace mca {
 
 class InstRef;
 struct InstrDesc;
 
 /// A Load/Store Unit implementing a load and store queues.

tools/llvm-mca/include/HardwareUnits/RegisterFile.h

 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 #define LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/Error.h"
 
 namespace mca {
 
 class ReadState;

tools/llvm-mca/include/HardwareUnits/RetireControlUnit.h

 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include "Instruction.h"
 #include "llvm/MC/MCSchedule.h"
 #include <vector>
 
 namespace mca {
 
 /// This class tracks which instructions are in-flight (i.e., dispatched but not
 /// retired) in the OoO backend.

tools/llvm-mca/include/HardwareUnits/Scheduler.h

 ///
 /// A scheduler for Processor Resource Units and Processor Resource Groups.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
 #define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
 
-#include "HardwareUnit.h"
-#include "LSUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
+#include "HardwareUnits/LSUnit.h"
 #include "ResourceManager.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace mca {
 
 class SchedulerStrategy {
 public:

tools/llvm-mca/include/Pipeline.h

 /// This file implements an ordered container of stages that simulate the
 /// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
-#include "Scheduler.h"
-#include "Stage.h"
+#include "HardwareUnits/Scheduler.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Error.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;

tools/llvm-mca/include/Stages/DispatchStage.h

 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 
 #include "HWEventListener.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
 #include "Instruction.h"
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are

tools/llvm-mca/include/Stages/ExecuteStage.h

 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 
+#include "HardwareUnits/Scheduler.h"
 #include "Instruction.h"
-#include "Scheduler.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/ArrayRef.h"
 
 namespace mca {
 
 class ExecuteStage final : public Stage {
   Scheduler &HWS;
 
   llvm::Error issueInstruction(InstRef &IR);

tools/llvm-mca/include/Stages/FetchStage.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 
 #include "InstrBuilder.h"
 #include "SourceMgr.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include <map>
 
 namespace mca {
 
 class FetchStage final : public Stage {
   std::unique_ptr<Instruction> CurrentInstruction;
   using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
   InstMap Instructions;

tools/llvm-mca/include/Stages/InstructionTables.h

 /// See the description of command-line flag -instruction-tables in
 /// docs/CommandGuide/lvm-mca.rst
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
 
+#include "HardwareUnits/Scheduler.h"
 #include "InstrBuilder.h"
-#include "Scheduler.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace mca {
 
 class InstructionTables final : public Stage {
   const llvm::MCSchedModel &SM;
   InstrBuilder &IB;

tools/llvm-mca/include/Stages/RetireStage.h

 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "Stage.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
+#include "Stages/Stage.h"
 
 namespace mca {
 
 class RetireStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 

tools/llvm-mca/lib/CMakeLists.txt

+include_directories(${LLVM_MCA_SOURCE_DIR}/include)
+
+add_library(LLVMMCA
+  STATIC
+  Context.cpp
+  HWEventListener.cpp
+  HardwareUnits/HardwareUnit.cpp
+  HardwareUnits/LSUnit.cpp
+  HardwareUnits/RegisterFile.cpp
+  HardwareUnits/ResourceManager.cpp
+  HardwareUnits/RetireControlUnit.cpp
+  HardwareUnits/Scheduler.cpp
+  InstrBuilder.cpp
+  Instruction.cpp
+  Pipeline.cpp
+  Stages/DispatchStage.cpp
+  Stages/ExecuteStage.cpp
+  Stages/FetchStage.cpp
+  Stages/InstructionTables.cpp
+  Stages/RetireStage.cpp
+  Stages/Stage.cpp
+  Support.cpp
+  )
+
+llvm_update_compile_flags(LLVMMCA)
+llvm_map_components_to_libnames(libs
+  CodeGen
+  MC
+  Support
+  )
+
+target_link_libraries(LLVMMCA ${libs})
+set_target_properties(LLVMMCA PROPERTIES FOLDER "Libraries")

tools/llvm-mca/lib/Context.cpp

 /// This file defines a class for holding ownership of various simulated
 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Context.h"
-#include "DispatchStage.h"
-#include "ExecuteStage.h"
-#include "FetchStage.h"
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "RetireStage.h"
-#include "Scheduler.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
+#include "HardwareUnits/Scheduler.h"
+#include "Stages/DispatchStage.h"
+#include "Stages/ExecuteStage.h"
+#include "Stages/FetchStage.h"
+#include "Stages/RetireStage.h"
 
 namespace mca {
 
 using namespace llvm;
 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {

tools/llvm-mca/lib/HardwareUnits/HardwareUnit.cpp

 //===------------------------- HardwareUnit.cpp -----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the anchor for the base class that describes
 /// simulated hardware units.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 
 namespace mca {
 
 // Pin the vtable with this method.
 HardwareUnit::~HardwareUnit() = default;
 
 } // namespace mca

tools/llvm-mca/lib/HardwareUnits/LSUnit.cpp

 //===----------------------- LSUnit.cpp --------------------------*- C++-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A Load-Store Unit for the llvm-mca tool.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "LSUnit.h"
+#include "HardwareUnits/LSUnit.h"
 #include "Instruction.h"
-
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {

tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

 //===--------------------- RegisterFile.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a register mapping file class.  This class is responsible
 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RegisterFile.h"
+#include "HardwareUnits/RegisterFile.h"
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {

tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp

 //===--------------------- ResourceManager.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// The classes here represent processor resource units and their management
 /// strategy.  These classes are managed by the Scheduler.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "ResourceManager.h"
+#include "HardwareUnits/ResourceManager.h"
 #include "Support.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 using namespace llvm;
 

tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp

 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RetireControlUnit.h"
+#include "HardwareUnits/RetireControlUnit.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp

 //===--------------------- Scheduler.cpp ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // A scheduler for processor resource units and processor resource groups.
 //
 //===----------------------------------------------------------------------===//
 
-#include "Scheduler.h"
+#include "HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"

tools/llvm-mca/lib/LLVMBuild.txt

+;===- ./tools/llvm-mca/lib/LLVMBuild.txt -----------------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = MCA
+parent = Libraries
+required_libraries = CodeGen MC Support

tools/llvm-mca/lib/Stages/DispatchStage.cpp

 /// This file models the dispatch component of an instruction pipeline.
 ///
 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "DispatchStage.h"
+#include "Stages/DispatchStage.h"
 #include "HWEventListener.h"
-#include "Scheduler.h"
+#include "HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/lib/Stages/ExecuteStage.cpp

 ///
 /// This file defines the execution stage of an instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "ExecuteStage.h"
+#include "Stages/ExecuteStage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 using namespace llvm;

tools/llvm-mca/lib/Stages/FetchStage.cpp

 //===---------------------- FetchStage.cpp ----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the Fetch stage of an instruction pipeline.  Its sole
 /// purpose in life is to produce instructions for the rest of the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "FetchStage.h"
+#include "Stages/FetchStage.h"
 
 namespace mca {
 
 bool FetchStage::hasWorkToComplete() const {
   return CurrentInstruction.get() || SM.hasNext();
 }
 
 bool FetchStage::isAvailable(const InstRef & /* unused */) const {

tools/llvm-mca/lib/Stages/InstructionTables.cpp

 ///
 /// This file implements the method InstructionTables::execute().
 /// Method execute() prints a theoretical resource pressure distribution based
 /// on the information available in the scheduling model, and without running
 /// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "InstructionTables.h"
+#include "Stages/InstructionTables.h"
 
 namespace mca {
 
 using namespace llvm;
 
 Error InstructionTables::execute(InstRef &IR) {
   ArrayRef<uint64_t> Masks = IB.getProcResourceMasks();
   const InstrDesc &Desc = IR.getInstruction()->getDesc();

tools/llvm-mca/lib/Stages/RetireStage.cpp

 //===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the retire stage of an instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RetireStage.h"
+#include "Stages/RetireStage.h"
 #include "HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 llvm::Error RetireStage::cycleStart() {

tools/llvm-mca/lib/Stages/Stage.cpp

 //===---------------------- Stage.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stage.h"
+#include "Stages/Stage.h"
 
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::~Stage() = default;
 
 void Stage::addListener(HWEventListener *Listener) {
   Listeners.insert(Listener);
 }
 
 } // namespace mca

tools/llvm-mca/llvm-mca.cpp

 //
 // The target defaults to the host target.
 // The cpu defaults to the 'native' host cpu.
 // The output defaults to standard output.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeRegion.h"
-#include "Context.h"
-#include "FetchStage.h"
-#include "InstructionTables.h"
-#include "Pipeline.h"
 #include "PipelinePrinter.h"
+#include "Stages/FetchStage.h"
+#include "Stages/InstructionTables.h"
 #include "Views/DispatchStatistics.h"
 #include "Views/InstructionInfoView.h"
 #include "Views/RegisterFileStatistics.h"
 #include "Views/ResourcePressureView.h"
 #include "Views/RetireControlUnitStatistics.h"
 #include "Views/SchedulerStatistics.h"
 #include "Views/SummaryView.h"
 #include "Views/TimelineView.h"
+#include "include/Context.h"
+#include "include/Pipeline.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"