[llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC.

[mattd]

Summary

This patch introduces llvm-mca as a library. The driver (llvm-mca.cpp), views, and stats, are not part of the library.
Those are separate components that are not required for the functioning of llvm-mca.

The directory has been organized as follows:
All library source files now reside in:

• lib/HardwareUnits/ - All subclasses of HardwareUnit (these represent the simulated hardware components of a backend). (LSUnit does not inherit from HardwareUnit, but Scheduler does which uses LSUnit).
• lib/Stages/ - All subclasses of the pipeline stages.
• lib/ - This is the root of the library and contains library code that does not fit into the Stages or HardwareUnit subdirs.

All library header files now reside in the include directory and mimic the same layout as the lib directory mentioned above.

In the (near) future we would like to move the library (include and lib) contents from tools and into the core of llvm somewhere.
That change would allow various analysis and optimization passes to make use of MCA functionality for things like cost modeling.

I left all of the non-library code just where it has always been, in the root of the llvm-mca directory.
The include directives for the non-library source file have been updated to refer to the llvm-mca library headers.
I updated the llvm-mca/CMakeLists.txt file to include the library headers, but I made the non-library code
explicitly reference the library's 'include' directory. Once we eventually (hopefully) migrate the MCA library
components into llvm the include directives used by the non-library source files will be updated to point to the
proper location in llvm.

[mattd]

tools/llvm-mca/PipelinePrinter.h

21

As I mentioned in the description. Once we move llvm-mca into a core llvm library, these 'include/' subdirectories will be updated to reference that location. For now, I left the include subdirectory explicit, even though the CMake file already includes that subdirectory.

[mattd]

• Tossed in an LLVMBuild.txt for the library.
• Added library dependencies to the cmake.

[andreadb]

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

I would like to place the Views and Stats into separate (non-library) directories, just to keep things better organized, but that would be a separate patch.

Any reasons why it cannot be done as part of this patch?

[mattd]

In D50929#1205986, @andreadb wrote:

My opinion is that CodeRegion.h and CodeRegion.cpp should not be part of the library. Those files implement a class which is meant to be used by the llvm-mca driver only to mark regions of code. A different utility class/approach should be used when llvm-mca is used as a library.

I am fine with that, I'll move those utility pieces outside of the library.

I would like to place the Views and Stats into separate (non-library) directories, just to keep things better organized, but that would be a separate patch.

Any reasons why it cannot be done as part of this patch?

I was just trying to isolate this patch to the addition of a library, but I am happy to move those files in this patch too.

[mattd]

• Updated per comments from the last spin:
  • Moved CodeRegion out of the library.
  • Added Views and Stats directories to cleanup the layout (Views and Stats are not part of the library).

[mattd]

• Move the Resource classes into their own file.

[mattd]

Rebased this diff after reorganizing the llvm-mca directory some.

[andreadb]

Hi Matt.

Thanks for this refactoring.
The change looks good to me.

Please update https://bugs.llvm.org/show_bug.cgi?id=37696 once you have committed this change. Thanks!

(also: unrelated to this patch. When you have time, could you please update https://bugs.llvm.org/show_bug.cgi?id=37835 ?).

-Andrea

tools/llvm-mca/CMakeLists.txt

+include_directories(include)
+
 set(LLVM_LINK_COMPONENTS
   AllTargetsAsmPrinters
   AllTargetsAsmParsers
   AllTargetsDescs
   AllTargetsDisassemblers
   AllTargetsInfos
   MC
   MCParser
   Support
   )
 
 add_llvm_tool(llvm-mca
-  CodeRegion.cpp
-  Context.cpp
-  DispatchStage.cpp
-  DispatchStatistics.cpp
-  ExecuteStage.cpp
-  FetchStage.cpp
-  HWEventListener.cpp
-  HardwareUnit.cpp
-  InstrBuilder.cpp
-  Instruction.cpp
-  InstructionInfoView.cpp
-  InstructionTables.cpp
-  LSUnit.cpp
   llvm-mca.cpp
-  Pipeline.cpp
+  CodeRegion.cpp
   PipelinePrinter.cpp
-  RegisterFile.cpp
-  RegisterFileStatistics.cpp
-  ResourcePressureView.cpp
-  RetireControlUnit.cpp
-  RetireControlUnitStatistics.cpp
-  RetireStage.cpp
-  Scheduler.cpp
-  SchedulerStatistics.cpp
-  Stage.cpp
-  Support.cpp
-  SummaryView.cpp
-  TimelineView.cpp
-  View.cpp
+  Stats/DispatchStatistics.cpp
+  Stats/RegisterFileStatistics.cpp
+  Stats/RetireControlUnitStatistics.cpp
+  Stats/SchedulerStatistics.cpp
+  Views/InstructionInfoView.cpp
+  Views/ResourcePressureView.cpp
+  Views/SummaryView.cpp
+  Views/TimelineView.cpp
+  Views/View.cpp
   )
+
+set(LLVM_MCA_SOURCE_DIR ${CURRENT_SOURCE_DIR})
+add_subdirectory(lib)
+target_link_libraries(llvm-mca PRIVATE LLVMMCA)

tools/llvm-mca/PipelinePrinter.h

 ///
 /// PipelinePrinter allows the customization of the performance report.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 
-#include "Pipeline.h"
-#include "View.h"
+#include "Views/View.h"
+#include "include/Pipeline.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 /// A printer class that knows how to collects statistics on the

tools/llvm-mca/PipelinePrinter.cpp

 //===--------------------- PipelinePrinter.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the PipelinePrinter interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "PipelinePrinter.h"
-#include "View.h"
+#include "Views/View.h"
 
 namespace mca {
 
 using namespace llvm;
 
 void PipelinePrinter::printReport(llvm::raw_ostream &OS) const {
   for (const auto &V : Views)
     V->printView(OS);
 }
 } // namespace mca.

tools/llvm-mca/Stats/DispatchStatistics.h

 ///  0,              15  (11.5%)
 ///  2,              4  (3.1%)
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H
 
-#include "View.h"
+#include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
 class DispatchStatistics : public View {
   unsigned NumDispatched;

tools/llvm-mca/Stats/DispatchStatistics.cpp

 //===--------------------- DispatchStatistics.cpp ---------------------*- C++
 //-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the DispatchStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "DispatchStatistics.h"
+#include "Stats/DispatchStatistics.h"
 #include "llvm/Support/Format.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void DispatchStatistics::onEvent(const HWStallEvent &Event) {
   if (Event.Type < HWStallEvent::LastGenericEvent)

tools/llvm-mca/Stats/RegisterFileStatistics.h

 ///    Total number of mappings created: 6
 ///    Max number of mappings used:      3
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_REGISTERFILESTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_REGISTERFILESTATISTICS_H
 
-#include "View.h"
+#include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
 class RegisterFileStatistics : public View {
   const llvm::MCSubtargetInfo &STI;
 

tools/llvm-mca/Stats/RegisterFileStatistics.cpp

 //===--------------------- RegisterFileStatistics.cpp -----------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the RegisterFileStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RegisterFileStatistics.h"
+#include "Stats/RegisterFileStatistics.h"
 #include "llvm/Support/Format.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void RegisterFileStatistics::initializeRegisterFileInfo() {
   const MCSchedModel &SM = STI.getSchedModel();

tools/llvm-mca/Stats/RetireControlUnitStatistics.h

 ///  2,           1  (0.8%)
 ///  4,           3  (2.3%)
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRECONTROLUNITSTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRECONTROLUNITSTATISTICS_H
 
-#include "View.h"
+#include "Views/View.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
 class RetireControlUnitStatistics : public View {
   using Histogram = std::map<unsigned, unsigned>;
   Histogram RetiredPerCycle;

tools/llvm-mca/Stats/RetireControlUnitStatistics.cpp

 //===--------------------- RetireControlUnitStatistics.cpp ------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the RetireControlUnitStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RetireControlUnitStatistics.h"
+#include "Stats/RetireControlUnitStatistics.h"
 #include "llvm/Support/Format.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void RetireControlUnitStatistics::onEvent(const HWInstructionEvent &Event) {
   if (Event.Type == HWInstructionEvent::Retired)

tools/llvm-mca/Stats/SchedulerStatistics.h

 /// JFPU01,  18/18
 /// JLSAGU,  0/12
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H
 
-#include "View.h"
+#include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
 class SchedulerStatistics : public View {
   const llvm::MCSchedModel &SM;

tools/llvm-mca/Stats/SchedulerStatistics.cpp

 //===--------------------- SchedulerStatistics.cpp --------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the SchedulerStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "SchedulerStatistics.h"
+#include "Stats/SchedulerStatistics.h"
 #include "llvm/Support/Format.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void SchedulerStatistics::onEvent(const HWInstructionEvent &Event) {
   if (Event.Type == HWInstructionEvent::Issued)

tools/llvm-mca/Views/InstructionInfoView.h

 ///  1      3     1.00                      vhaddps %xmm2, %xmm2, %xmm3
 ///  1      3     1.00                      vhaddps %xmm3, %xmm3, %xmm4
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTIONINFOVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTIONINFOVIEW_H
 
-#include "SourceMgr.h"
-#include "View.h"
+#include "Views/View.h"
+#include "include/SourceMgr.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {

tools/llvm-mca/Views/InstructionInfoView.cpp

 //===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the InstructionInfoView API.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "InstructionInfoView.h"
+#include "Views/InstructionInfoView.h"
 
 namespace mca {
 
 using namespace llvm;
 
 void InstructionInfoView::printView(raw_ostream &OS) const {
   std::string Buffer;
   raw_string_ostream TempStream(Buffer);

tools/llvm-mca/Views/ResourcePressureView.h

 /// per iteration. Consequently, the resource pressure on JFPU0 is of 2cy per
 /// iteration.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RESOURCEPRESSUREVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_RESOURCEPRESSUREVIEW_H
 
-#include "SourceMgr.h"
-#include "View.h"
+#include "Views/View.h"
+#include "include/SourceMgr.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
 /// This class collects resource pressure statistics and it is able to print

tools/llvm-mca/Views/ResourcePressureView.cpp

 //===--------------------- ResourcePressureView.cpp -------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements methods in the ResourcePressureView interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "ResourcePressureView.h"
+#include "Views/ResourcePressureView.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 using namespace llvm;
 
 void ResourcePressureView::initialize() {

tools/llvm-mca/Views/SummaryView.h

 /// The summary view collects a few performance numbers. The two main
 /// performance indicators are 'Total Cycles' and IPC (Instructions Per Cycle).
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SUMMARYVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_SUMMARYVIEW_H
 
-#include "SourceMgr.h"
-#include "View.h"
+#include "Views/View.h"
+#include "include/SourceMgr.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 /// A view that collects and prints a few performance numbers.
 class SummaryView : public View {

tools/llvm-mca/Views/SummaryView.cpp

 //===--------------------- SummaryView.cpp -------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the functionalities used by the SummaryView to print
 /// the report information.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "SummaryView.h"
-#include "Support.h"
+#include "Views/SummaryView.h"
+#include "include/Support.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Format.h"
 
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
 using namespace llvm;

tools/llvm-mca/Views/TimelineView.h

 /// That is expected because instruction 5 cannot transition to the "ready"
 /// state until %xmm4 is written by instruction 4.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
 
-#include "SourceMgr.h"
-#include "View.h"
+#include "Views/View.h"
+#include "include/SourceMgr.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/raw_ostream.h"
 #include <map>
 
 namespace mca {
 

tools/llvm-mca/Views/TimelineView.cpp

 //===--------------------- TimelineView.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \brief
 ///
 /// This file implements the TimelineView interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "TimelineView.h"
+#include "Views/TimelineView.h"
 
 using namespace llvm;
 
 namespace mca {
 
 void TimelineView::initialize(unsigned MaxIterations) {
   unsigned NumInstructions =
       AsmSequence.getNumIterations() * AsmSequence.size();

tools/llvm-mca/Views/View.h

 /// This file defines the main interface for Views. Each view contributes a
 /// portion of the final report generated by the tool.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_VIEW_H
 #define LLVM_TOOLS_LLVM_MCA_VIEW_H
 
-#include "HWEventListener.h"
+#include "include/HWEventListener.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 class View : public HWEventListener {
 public:
   virtual void printView(llvm::raw_ostream &OS) const = 0;
   virtual ~View() = default;
   void anchor() override;
 };
 } // namespace mca
 
 #endif

tools/llvm-mca/Views/View.cpp

 //===----------------------- View.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the virtual anchor method in View.h to pin the vtable.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "View.h"
+#include "Views/View.h"
 
 namespace mca {
 
 void View::anchor() {}
 } // namespace mca

tools/llvm-mca/include/Context.h

 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
 #define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include "InstrBuilder.h"
 #include "Pipeline.h"
 #include "SourceMgr.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <memory>
 

tools/llvm-mca/include/HardwareUnits/RegisterFile.h

 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 #define LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/Error.h"
 
 namespace mca {
 
 class ReadState;

tools/llvm-mca/include/HardwareUnits/ResourceManager.h

-//===--------------------- Scheduler.h ------------------------*- C++ -*-===//
+//===--------------------- ResourceManager.h --------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// A scheduler for Processor Resource Units and Processor Resource Groups.
+/// The classes here represent processor resource units and their management
+/// strategy.  These classes are managed by the Scheduler.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
-#define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+#ifndef LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H
+#define LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H
 
-#include "HardwareUnit.h"
 #include "Instruction.h"
-#include "LSUnit.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include <map>
+#include "llvm/MC/MCSchedule.h"
 
 namespace mca {
 
 /// Used to notify the internal state of a processor resource.
 ///
 /// A processor resource is available if it is not reserved, and there are
 /// available slots in the buffer.  A processor resource is unavailable if it
 /// is either reserved, or the associated buffer is full. A processor resource
public:
   void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &ResourcesFreed);
 
 #ifndef NDEBUG
   void dump() const {
     for (const std::unique_ptr<ResourceState> &Resource : Resources)
       Resource->dump();
   }
 #endif
-}; // namespace mca
-
-class SchedulerStrategy {
-public:
-  SchedulerStrategy() = default;
-  virtual ~SchedulerStrategy();
-
-  /// Returns true if Lhs should take priority over Rhs.
-  ///
-  /// This method is used by class Scheduler to select the "best" ready
-  /// instruction to issue to the underlying pipelines.
-  virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const = 0;
-};
-
-/// Default instruction selection strategy used by class Scheduler.
-class DefaultSchedulerStrategy : public SchedulerStrategy {
-  /// This method ranks instructions based on their age, and the number of known
-  /// users. The lower the rank value, the better.
-  int computeRank(const InstRef &Lhs) const {
-    return Lhs.getSourceIndex() - Lhs.getInstruction()->getNumUsers();
-  }
-
-public:
-  DefaultSchedulerStrategy() = default;
-  virtual ~DefaultSchedulerStrategy();
-
-  bool compare(const InstRef &Lhs, const InstRef &Rhs) const override {
-    int LhsRank = computeRank(Lhs);
-    int RhsRank = computeRank(Rhs);
-
-    /// Prioritize older instructions over younger instructions to minimize the
-    /// pressure on the reorder buffer.
-    if (LhsRank == RhsRank)
-      return Lhs.getSourceIndex() < Rhs.getSourceIndex();
-    return LhsRank < RhsRank;
-  }
-};
-
-/// Class Scheduler is responsible for issuing instructions to pipeline
-/// resources.
-///
-/// Internally, it delegates to a ResourceManager the management of processor
-/// resources. This class is also responsible for tracking the progress of
-/// instructions from the dispatch stage, until the write-back stage.
-///
-/// An instruction dispatched to the Scheduler is initially placed into either
-/// the 'WaitSet' or the 'ReadySet' depending on the availability of the input
-/// operands.
-///
-/// An instruction is moved from the WaitSet to the ReadySet when register
-/// operands become available, and all memory dependencies are met.
-/// Instructions that are moved from the WaitSet to the ReadySet transition
-/// in state from 'IS_AVAILABLE' to 'IS_READY'.
-///
-/// On every cycle, the Scheduler checks if it can promote instructions from the
-/// WaitSet to the ReadySet.
-///
-/// An Instruction is moved from the ReadySet the `IssuedSet` when it is issued
-/// to a (one or more) pipeline(s). This event also causes an instruction state
-/// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
-/// leaves the IssuedSet when it reaches the write-back stage.
-class Scheduler : public HardwareUnit {
-  LSUnit *LSU;
-
-  // Instruction selection strategy for this Scheduler.
-  std::unique_ptr<SchedulerStrategy> Strategy;
-
-  // Hardware resources that are managed by this scheduler.
-  std::unique_ptr<ResourceManager> Resources;
-
-  std::vector<InstRef> WaitSet;
-  std::vector<InstRef> ReadySet;
-  std::vector<InstRef> IssuedSet;
-
-  /// Verify the given selection strategy and set the Strategy member
-  /// accordingly.  If no strategy is provided, the DefaultSchedulerStrategy is
-  /// used.
-  void initializeStrategy(std::unique_ptr<SchedulerStrategy> S);
-
-  /// Issue an instruction without updating the ready queue.
-  void issueInstructionImpl(
-      InstRef &IR,
-      llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
-
-  // Identify instructions that have finished executing, and remove them from
-  // the IssuedSet. References to executed instructions are added to input
-  // vector 'Executed'.
-  void updateIssuedSet(llvm::SmallVectorImpl<InstRef> &Executed);
-
-  // Try to promote instructions from WaitSet to ReadySet.
-  // Add promoted instructions to the 'Ready' vector in input.
-  void promoteToReadySet(llvm::SmallVectorImpl<InstRef> &Ready);
-
-public:
-  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu)
-      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
-    initializeStrategy(nullptr);
-  }
-  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu,
-            std::unique_ptr<SchedulerStrategy> SelectStrategy)
-      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
-    initializeStrategy(std::move(SelectStrategy));
-  }
-  Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit *Lsu,
-            std::unique_ptr<SchedulerStrategy> SelectStrategy)
-      : LSU(Lsu), Resources(std::move(RM)) {
-    initializeStrategy(std::move(SelectStrategy));
-  }
-
-  // Stalls generated by the scheduler.
-  enum Status {
-    SC_AVAILABLE,
-    SC_LOAD_QUEUE_FULL,
-    SC_STORE_QUEUE_FULL,
-    SC_BUFFERS_FULL,
-    SC_DISPATCH_GROUP_STALL,
-  };
-
-  /// Check if the instruction in 'IR' can be dispatched and returns an answer
-  /// in the form of a Status value.
-  ///
-  /// The DispatchStage is responsible for querying the Scheduler before
-  /// dispatching new instructions. This routine is used for performing such
-  /// a query.  If the instruction 'IR' can be dispatched, then true is
-  /// returned, otherwise false is returned with Event set to the stall type.
-  /// Internally, it also checks if the load/store unit is available.
-  Status isAvailable(const InstRef &IR) const;
-
-  /// Reserves buffer and LSUnit queue resources that are necessary to issue
-  /// this instruction.
-  ///
-  /// Returns true if instruction IR is ready to be issued to the underlying
-  /// pipelines. Note that this operation cannot fail; it assumes that a
-  /// previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`.
-  void dispatch(const InstRef &IR);
-
-  /// Returns true if IR is ready to be executed by the underlying pipelines.
-  /// This method assumes that IR has been previously dispatched.
-  bool isReady(const InstRef &IR) const;
-
-  /// Issue an instruction and populates a vector of used pipeline resources,
-  /// and a vector of instructions that transitioned to the ready state as a
-  /// result of this event.
-  void
-  issueInstruction(InstRef &IR,
-                   llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Used,
-                   llvm::SmallVectorImpl<InstRef> &Ready);
-
-  /// Returns true if IR has to be issued immediately, or if IR is a zero
-  /// latency instruction.
-  bool mustIssueImmediately(const InstRef &IR) const;
-
-  /// This routine notifies the Scheduler that a new cycle just started.
-  ///
-  /// It notifies the underlying ResourceManager that a new cycle just started.
-  /// Vector `Freed` is populated with resourceRef related to resources that
-  /// have changed in state, and that are now available to new instructions.
-  /// Instructions executed are added to vector Executed, while vector Ready is
-  /// populated with instructions that have become ready in this new cycle.
-  void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &Freed,
-                  llvm::SmallVectorImpl<InstRef> &Ready,
-                  llvm::SmallVectorImpl<InstRef> &Executed);
-
-  /// Convert a resource mask into a valid llvm processor resource identifier.
-  unsigned getResourceID(uint64_t Mask) const {
-    return Resources->resolveResourceMask(Mask);
-  }
-
-  /// Select the next instruction to issue from the ReadySet. Returns an invalid
-  /// instruction reference if there are no ready instructions, or if processor
-  /// resources are not available.
-  InstRef select();
-
-#ifndef NDEBUG
-  // Update the ready queues.
-  void dump() const;
-
-  // This routine performs a sanity check.  This routine should only be called
-  // when we know that 'IR' is not in the scheduler's instruction queues.
-  void sanityCheck(const InstRef &IR) const {
-    assert(llvm::find(WaitSet, IR) == WaitSet.end());
-    assert(llvm::find(ReadySet, IR) == ReadySet.end());
-    assert(llvm::find(IssuedSet, IR) == IssuedSet.end());
-  }
-#endif // !NDEBUG
 };
 } // namespace mca
 
-#endif // LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+#endif // LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H

tools/llvm-mca/include/HardwareUnits/Scheduler.h

+//===--------------------- Scheduler.h ------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// A scheduler for Processor Resource Units and Processor Resource Groups.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+#define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
+
+#include "HardwareUnit.h"
+#include "HardwareUnits/ResourceManager.h"
+#include "HardwareUnits/LSUnit.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/MC/MCSchedule.h"
+
+namespace mca {
+
+class SchedulerStrategy {
+public:
+  SchedulerStrategy() = default;
+  virtual ~SchedulerStrategy();
+
+  /// Returns true if Lhs should take priority over Rhs.
+  ///
+  /// This method is used by class Scheduler to select the "best" ready
+  /// instruction to issue to the underlying pipelines.
+  virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const = 0;
+};
+
+/// Default instruction selection strategy used by class Scheduler.
+class DefaultSchedulerStrategy : public SchedulerStrategy {
+  /// This method ranks instructions based on their age, and the number of known
+  /// users. The lower the rank value, the better.
+  int computeRank(const InstRef &Lhs) const {
+    return Lhs.getSourceIndex() - Lhs.getInstruction()->getNumUsers();
+  }
+
+public:
+  DefaultSchedulerStrategy() = default;
+  virtual ~DefaultSchedulerStrategy();
+
+  bool compare(const InstRef &Lhs, const InstRef &Rhs) const override {
+    int LhsRank = computeRank(Lhs);
+    int RhsRank = computeRank(Rhs);
+
+    /// Prioritize older instructions over younger instructions to minimize the
+    /// pressure on the reorder buffer.
+    if (LhsRank == RhsRank)
+      return Lhs.getSourceIndex() < Rhs.getSourceIndex();
+    return LhsRank < RhsRank;
+  }
+};
+
+/// Class Scheduler is responsible for issuing instructions to pipeline
+/// resources.
+///
+/// Internally, it delegates to a ResourceManager the management of processor
+/// resources. This class is also responsible for tracking the progress of
+/// instructions from the dispatch stage, until the write-back stage.
+///
+/// An instruction dispatched to the Scheduler is initially placed into either
+/// the 'WaitSet' or the 'ReadySet' depending on the availability of the input
+/// operands.
+///
+/// An instruction is moved from the WaitSet to the ReadySet when register
+/// operands become available, and all memory dependencies are met.
+/// Instructions that are moved from the WaitSet to the ReadySet transition
+/// in state from 'IS_AVAILABLE' to 'IS_READY'.
+///
+/// On every cycle, the Scheduler checks if it can promote instructions from the
+/// WaitSet to the ReadySet.
+///
+/// An Instruction is moved from the ReadySet the `IssuedSet` when it is issued
+/// to a (one or more) pipeline(s). This event also causes an instruction state
+/// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
+/// leaves the IssuedSet when it reaches the write-back stage.
+class Scheduler : public HardwareUnit {
+  LSUnit *LSU;
+
+  // Instruction selection strategy for this Scheduler.
+  std::unique_ptr<SchedulerStrategy> Strategy;
+
+  // Hardware resources that are managed by this scheduler.
+  std::unique_ptr<ResourceManager> Resources;
+
+  std::vector<InstRef> WaitSet;
+  std::vector<InstRef> ReadySet;
+  std::vector<InstRef> IssuedSet;
+
+  /// Verify the given selection strategy and set the Strategy member
+  /// accordingly.  If no strategy is provided, the DefaultSchedulerStrategy is
+  /// used.
+  void initializeStrategy(std::unique_ptr<SchedulerStrategy> S);
+
+  /// Issue an instruction without updating the ready queue.
+  void issueInstructionImpl(
+      InstRef &IR,
+      llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
+
+  // Identify instructions that have finished executing, and remove them from
+  // the IssuedSet. References to executed instructions are added to input
+  // vector 'Executed'.
+  void updateIssuedSet(llvm::SmallVectorImpl<InstRef> &Executed);
+
+  // Try to promote instructions from WaitSet to ReadySet.
+  // Add promoted instructions to the 'Ready' vector in input.
+  void promoteToReadySet(llvm::SmallVectorImpl<InstRef> &Ready);
+
+public:
+  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu)
+      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
+    initializeStrategy(nullptr);
+  }
+  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu,
+            std::unique_ptr<SchedulerStrategy> SelectStrategy)
+      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
+    initializeStrategy(std::move(SelectStrategy));
+  }
+  Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit *Lsu,
+            std::unique_ptr<SchedulerStrategy> SelectStrategy)
+      : LSU(Lsu), Resources(std::move(RM)) {
+    initializeStrategy(std::move(SelectStrategy));
+  }
+
+  // Stalls generated by the scheduler.
+  enum Status {
+    SC_AVAILABLE,
+    SC_LOAD_QUEUE_FULL,
+    SC_STORE_QUEUE_FULL,
+    SC_BUFFERS_FULL,
+    SC_DISPATCH_GROUP_STALL,
+  };
+
+  /// Check if the instruction in 'IR' can be dispatched and returns an answer
+  /// in the form of a Status value.
+  ///
+  /// The DispatchStage is responsible for querying the Scheduler before
+  /// dispatching new instructions. This routine is used for performing such
+  /// a query.  If the instruction 'IR' can be dispatched, then true is
+  /// returned, otherwise false is returned with Event set to the stall type.
+  /// Internally, it also checks if the load/store unit is available.
+  Status isAvailable(const InstRef &IR) const;
+
+  /// Reserves buffer and LSUnit queue resources that are necessary to issue
+  /// this instruction.
+  ///
+  /// Returns true if instruction IR is ready to be issued to the underlying
+  /// pipelines. Note that this operation cannot fail; it assumes that a
+  /// previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`.
+  void dispatch(const InstRef &IR);
+
+  /// Returns true if IR is ready to be executed by the underlying pipelines.
+  /// This method assumes that IR has been previously dispatched.
+  bool isReady(const InstRef &IR) const;
+
+  /// Issue an instruction and populates a vector of used pipeline resources,
+  /// and a vector of instructions that transitioned to the ready state as a
+  /// result of this event.
+  void
+  issueInstruction(InstRef &IR,
+                   llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Used,
+                   llvm::SmallVectorImpl<InstRef> &Ready);
+
+  /// Returns true if IR has to be issued immediately, or if IR is a zero
+  /// latency instruction.
+  bool mustIssueImmediately(const InstRef &IR) const;
+
+  /// This routine notifies the Scheduler that a new cycle just started.
+  ///
+  /// It notifies the underlying ResourceManager that a new cycle just started.
+  /// Vector `Freed` is populated with resourceRef related to resources that
+  /// have changed in state, and that are now available to new instructions.
+  /// Instructions executed are added to vector Executed, while vector Ready is
+  /// populated with instructions that have become ready in this new cycle.
+  void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &Freed,
+                  llvm::SmallVectorImpl<InstRef> &Ready,
+                  llvm::SmallVectorImpl<InstRef> &Executed);
+
+  /// Convert a resource mask into a valid llvm processor resource identifier.
+  unsigned getResourceID(uint64_t Mask) const {
+    return Resources->resolveResourceMask(Mask);
+  }
+
+  /// Select the next instruction to issue from the ReadySet. Returns an invalid
+  /// instruction reference if there are no ready instructions, or if processor
+  /// resources are not available.
+  InstRef select();
+
+#ifndef NDEBUG
+  // Update the ready queues.
+  void dump() const;
+
+  // This routine performs a sanity check.  This routine should only be called
+  // when we know that 'IR' is not in the scheduler's instruction queues.
+  void sanityCheck(const InstRef &IR) const {
+    assert(llvm::find(WaitSet, IR) == WaitSet.end());
+    assert(llvm::find(ReadySet, IR) == ReadySet.end());
+    assert(llvm::find(IssuedSet, IR) == IssuedSet.end());
+  }
+#endif // !NDEBUG
+};
+} // namespace mca
+
+#endif // LLVM_TOOLS_LLVM_MCA_SCHEDULER_H

tools/llvm-mca/include/Pipeline.h

 /// This file implements an ordered container of stages that simulate the
 /// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
-#include "Scheduler.h"
-#include "Stage.h"
+#include "HardwareUnits/Scheduler.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Error.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;

tools/llvm-mca/include/Stages/DispatchStage.h

 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 
 #include "HWEventListener.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
 #include "Instruction.h"
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are

tools/llvm-mca/include/Stages/ExecuteStage.h

 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 
+#include "HardwareUnits/Scheduler.h"
 #include "Instruction.h"
-#include "Scheduler.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/ArrayRef.h"
 
 namespace mca {
 
 class ExecuteStage final : public Stage {
   Scheduler &HWS;
 
   llvm::Error issueInstruction(InstRef &IR);

tools/llvm-mca/include/Stages/FetchStage.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 
 #include "InstrBuilder.h"
 #include "SourceMgr.h"
-#include "Stage.h"
+#include "Stages/Stage.h"
 #include <map>
 
 namespace mca {
 
 class FetchStage final : public Stage {
   std::unique_ptr<Instruction> CurrentInstruction;
   using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
   InstMap Instructions;

tools/llvm-mca/include/Stages/InstructionTables.h

 /// See the description of command-line flag -instruction-tables in
 /// docs/CommandGuide/lvm-mca.rst
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
 
+#include "HardwareUnits/Scheduler.h"
 #include "InstrBuilder.h"
-#include "Scheduler.h"
-#include "Stage.h"
-#include "View.h"
+#include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace mca {
 
 class InstructionTables final : public Stage {
   const llvm::MCSchedModel &SM;
   InstrBuilder &IB;

tools/llvm-mca/include/Stages/RetireStage.h

 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "Stage.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
+#include "Stages/Stage.h"
 
 namespace mca {
 
 class RetireStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 

tools/llvm-mca/lib/CMakeLists.txt

+include_directories(${LLVM_MCA_SOURCE_DIR}/include)
+
+add_library(LLVMMCA
+  STATIC
+  Context.cpp
+  HWEventListener.cpp
+  HardwareUnits/HardwareUnit.cpp
+  HardwareUnits/LSUnit.cpp
+  HardwareUnits/RegisterFile.cpp
+  HardwareUnits/ResourceManager.cpp
+  HardwareUnits/RetireControlUnit.cpp
+  HardwareUnits/Scheduler.cpp
+  InstrBuilder.cpp
+  Instruction.cpp
+  Pipeline.cpp
+  Stages/DispatchStage.cpp
+  Stages/ExecuteStage.cpp
+  Stages/FetchStage.cpp
+  Stages/InstructionTables.cpp
+  Stages/RetireStage.cpp
+  Stages/Stage.cpp
+  Support.cpp
+  )
+
+llvm_update_compile_flags(LLVMMCA)
+llvm_map_components_to_libnames(libs
+  CodeGen
+  MC
+  Support
+  )
+
+target_link_libraries(LLVMMCA ${libs})
+set_target_properties(LLVMMCA PROPERTIES FOLDER "Libraries")

tools/llvm-mca/lib/Context.cpp

 /// This file defines a class for holding ownership of various simulated
 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Context.h"
-#include "DispatchStage.h"
-#include "ExecuteStage.h"
-#include "FetchStage.h"
-#include "RegisterFile.h"
-#include "RetireControlUnit.h"
-#include "RetireStage.h"
-#include "Scheduler.h"
+#include "HardwareUnits/RegisterFile.h"
+#include "HardwareUnits/RetireControlUnit.h"
+#include "HardwareUnits/Scheduler.h"
+#include "Stages/DispatchStage.h"
+#include "Stages/ExecuteStage.h"
+#include "Stages/FetchStage.h"
+#include "Stages/RetireStage.h"
 
 namespace mca {
 
 using namespace llvm;
 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {

tools/llvm-mca/lib/HardwareUnits/HardwareUnit.cpp

 //===------------------------- HardwareUnit.cpp -----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the anchor for the base class that describes
 /// simulated hardware units.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "HardwareUnit.h"
+#include "HardwareUnits/HardwareUnit.h"
 
 namespace mca {
 
 // Pin the vtable with this method.
 HardwareUnit::~HardwareUnit() = default;
 
 } // namespace mca

tools/llvm-mca/lib/HardwareUnits/LSUnit.cpp

 //===----------------------- LSUnit.cpp --------------------------*- C++-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// A Load-Store Unit for the llvm-mca tool.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "LSUnit.h"
+#include "HardwareUnits/LSUnit.h"
 #include "Instruction.h"
 
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"

tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

 //===--------------------- RegisterFile.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a register mapping file class.  This class is responsible
 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RegisterFile.h"
+#include "HardwareUnits/RegisterFile.h"
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {

tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp

-//===--------------------- Scheduler.cpp ------------------------*- C++ -*-===//
+//===--------------------- ResourceManager.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-//
-// A scheduler for processor resource units and processor resource groups.
-//
+/// \file
+///
+/// The classes here represent processor resource units and their management
+/// strategy.  These classes are managed by the Scheduler.
+///
 //===----------------------------------------------------------------------===//
 
-#include "Scheduler.h"
+#include "HardwareUnits/ResourceManager.h"
 #include "Support.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
-
 ResourceStrategy::~ResourceStrategy() = default;
 
-void Scheduler::initializeStrategy(std::unique_ptr<SchedulerStrategy> S) {
-  // Ensure we have a valid (non-null) strategy object.
-  Strategy = S ? std::move(S) : llvm::make_unique<DefaultSchedulerStrategy>();
-}
-
 void DefaultResourceStrategy::skipMask(uint64_t Mask) {
   NextInSequenceMask &= (~Mask);
   if (!NextInSequenceMask) {
     NextInSequenceMask = ResourceUnitMask ^ RemovedFromNextInSequence;
     RemovedFromNextInSequence = 0;
   }
 }
 

 void DefaultResourceStrategy::used(uint64_t Mask) {
   if (Mask > NextInSequenceMask) {
     RemovedFromNextInSequence |= Mask;
     return;
   }
   skipMask(Mask);
 }
 
-ResourceState::ResourceState(const llvm::MCProcResourceDesc &Desc,
-                             unsigned Index, uint64_t Mask)
+ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index,
+                             uint64_t Mask)
     : ProcResourceDescIndex(Index), ResourceMask(Mask),
       BufferSize(Desc.BufferSize) {
   if (llvm::countPopulation(ResourceMask) > 1)
     ResourceSizeMask = ResourceMask ^ llvm::PowerOf2Floor(ResourceMask);
   else
     ResourceSizeMask = (1ULL << Desc.NumUnits) - 1;
   ReadyMask = ResourceSizeMask;
   AvailableSlots = BufferSize == -1 ? 0U : static_cast<unsigned>(BufferSize);

 
 static std::unique_ptr<ResourceStrategy>
 getStrategyFor(const ResourceState &RS) {
   if (RS.isAResourceGroup() || RS.getNumUnits() > 1)
     return llvm::make_unique<DefaultResourceStrategy>(RS.getReadyMask());
   return std::unique_ptr<ResourceStrategy>(nullptr);
 }
 
-ResourceManager::ResourceManager(const llvm::MCSchedModel &SM)
+ResourceManager::ResourceManager(const MCSchedModel &SM)
     : ProcResID2Mask(SM.getNumProcResourceKinds()) {
   computeProcResourceMasks(SM, ProcResID2Mask);
   Resources.resize(SM.getNumProcResourceKinds());
   Strategies.resize(SM.getNumProcResourceKinds());
 
   for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
     uint64_t Mask = ProcResID2Mask[I];
     unsigned Index = getResourceStateIndex(Mask);
void ResourceManager::reserveResource(uint64_t ResourceID) {
   Resource.setReserved();
 }
 
 void ResourceManager::releaseResource(uint64_t ResourceID) {
   ResourceState &Resource = *Resources[getResourceStateIndex(ResourceID)];
   Resource.clearReserved();
 }
 
-// Anchor the vtable of SchedulerStrategy and DefaultSchedulerStrategy.
-SchedulerStrategy::~SchedulerStrategy() = default;
-DefaultSchedulerStrategy::~DefaultSchedulerStrategy() = default;
-
-#ifndef NDEBUG
-void Scheduler::dump() const {
-  dbgs() << "[SCHEDULER]: WaitSet size is: " << WaitSet.size() << '\n';
-  dbgs() << "[SCHEDULER]: ReadySet size is: " << ReadySet.size() << '\n';
-  dbgs() << "[SCHEDULER]: IssuedSet size is: " << IssuedSet.size() << '\n';
-  Resources->dump();
-}
-#endif
-
-Scheduler::Status Scheduler::isAvailable(const InstRef &IR) const {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-
-  switch (Resources->canBeDispatched(Desc.Buffers)) {
-  case ResourceStateEvent::RS_BUFFER_UNAVAILABLE:
-    return Scheduler::SC_BUFFERS_FULL;
-  case ResourceStateEvent::RS_RESERVED:
-    return Scheduler::SC_DISPATCH_GROUP_STALL;
-  case ResourceStateEvent::RS_BUFFER_AVAILABLE:
-    break;
-  }
-
-  // Give lower priority to LSUnit stall events.
-  switch (LSU->isAvailable(IR)) {
-  case LSUnit::LSU_LQUEUE_FULL:
-    return Scheduler::SC_LOAD_QUEUE_FULL;
-  case LSUnit::LSU_SQUEUE_FULL:
-    return Scheduler::SC_STORE_QUEUE_FULL;
-  case LSUnit::LSU_AVAILABLE:
-    return Scheduler::SC_AVAILABLE;
-  }
-
-  llvm_unreachable("Don't know how to process this LSU state result!");
-}
-
-void Scheduler::issueInstructionImpl(
-    InstRef &IR,
-    SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources) {
-  Instruction *IS = IR.getInstruction();
-  const InstrDesc &D = IS->getDesc();
-
-  // Issue the instruction and collect all the consumed resources
-  // into a vector. That vector is then used to notify the listener.
-  Resources->issueInstruction(D, UsedResources);
-
-  // Notify the instruction that it started executing.
-  // This updates the internal state of each write.
-  IS->execute();
-
-  if (IS->isExecuting())
-    IssuedSet.emplace_back(IR);
-  else if (IS->isExecuted())
-    LSU->onInstructionExecuted(IR);
-}
-
-// Release the buffered resources and issue the instruction.
-void Scheduler::issueInstruction(
-    InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources,
-    SmallVectorImpl<InstRef> &ReadyInstructions) {
-  const Instruction &Inst = *IR.getInstruction();
-  bool HasDependentUsers = Inst.hasDependentUsers();
-
-  Resources->releaseBuffers(Inst.getDesc().Buffers);
-  issueInstructionImpl(IR, UsedResources);
-  // Instructions that have been issued during this cycle might have unblocked
-  // other dependent instructions. Dependent instructions may be issued during
-  // this same cycle if operands have ReadAdvance entries.  Promote those
-  // instructions to the ReadySet and notify the caller that those are ready.
-  if (HasDependentUsers)
-    promoteToReadySet(ReadyInstructions);
-}
-
-void Scheduler::promoteToReadySet(SmallVectorImpl<InstRef> &Ready) {
-  // Scan the set of waiting instructions and promote them to the
-  // ready queue if operands are all ready.
-  unsigned RemovedElements = 0;
-  for (auto I = WaitSet.begin(), E = WaitSet.end(); I != E;) {
-    InstRef &IR = *I;
-    if (!IR.isValid())
-      break;
-
-    // Check if this instruction is now ready. In case, force
-    // a transition in state using method 'update()'.
-    Instruction &IS = *IR.getInstruction();
-    if (!IS.isReady())
-      IS.update();
-
-    // Check if there are still unsolved data dependencies.
-    if (!isReady(IR)) {
-      ++I;
-      continue;
-    }
-
-    Ready.emplace_back(IR);
-    ReadySet.emplace_back(IR);
-
-    IR.invalidate();
-    ++RemovedElements;
-    std::iter_swap(I, E - RemovedElements);
-  }
-
-  WaitSet.resize(WaitSet.size() - RemovedElements);
-}
-
-InstRef Scheduler::select() {
-  unsigned QueueIndex = ReadySet.size();
-  for (unsigned I = 0, E = ReadySet.size(); I != E; ++I) {
-    const InstRef &IR = ReadySet[I];
-    if (QueueIndex == ReadySet.size() ||
-        Strategy->compare(IR, ReadySet[QueueIndex])) {
-      const InstrDesc &D = IR.getInstruction()->getDesc();
-      if (Resources->canBeIssued(D))
-        QueueIndex = I;
-    }
-  }
-
-  if (QueueIndex == ReadySet.size())
-    return InstRef();
-
-  // We found an instruction to issue.
-  InstRef IR = ReadySet[QueueIndex];
-  std::swap(ReadySet[QueueIndex], ReadySet[ReadySet.size() - 1]);
-  ReadySet.pop_back();
-  return IR;
-}
-
-void Scheduler::updateIssuedSet(SmallVectorImpl<InstRef> &Executed) {
-  unsigned RemovedElements = 0;
-  for (auto I = IssuedSet.begin(), E = IssuedSet.end(); I != E;) {
-    InstRef &IR = *I;
-    if (!IR.isValid())
-      break;
-    Instruction &IS = *IR.getInstruction();
-    if (!IS.isExecuted()) {
-      LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
-                        << " is still executing.\n");
-      ++I;
-      continue;
-    }
-
-    // Instruction IR has completed execution.
-    LSU->onInstructionExecuted(IR);
-    Executed.emplace_back(IR);
-    ++RemovedElements;
-    IR.invalidate();
-    std::iter_swap(I, E - RemovedElements);
-  }
-
-  IssuedSet.resize(IssuedSet.size() - RemovedElements);
-}
-
-void Scheduler::cycleEvent(SmallVectorImpl<ResourceRef> &Freed,
-                           SmallVectorImpl<InstRef> &Executed,
-                           SmallVectorImpl<InstRef> &Ready) {
-  // Release consumed resources.
-  Resources->cycleEvent(Freed);
-
-  // Propagate the cycle event to the 'Issued' and 'Wait' sets.
-  for (InstRef &IR : IssuedSet)
-    IR.getInstruction()->cycleEvent();
-
-  updateIssuedSet(Executed);
-
-  for (InstRef &IR : WaitSet)
-    IR.getInstruction()->cycleEvent();
-
-  promoteToReadySet(Ready);
-}
-
-bool Scheduler::mustIssueImmediately(const InstRef &IR) const {
-  // Instructions that use an in-order dispatch/issue processor resource must be
-  // issued immediately to the pipeline(s). Any other in-order buffered
-  // resources (i.e. BufferSize=1) is consumed.
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  return Desc.isZeroLatency() || Resources->mustIssueImmediately(Desc);
-}
-
-void Scheduler::dispatch(const InstRef &IR) {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  Resources->reserveBuffers(Desc.Buffers);
-
-  // If necessary, reserve queue entries in the load-store unit (LSU).
-  bool IsMemOp = Desc.MayLoad || Desc.MayStore;
-  if (IsMemOp)
-    LSU->dispatch(IR);
-
-  if (!isReady(IR)) {
-    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
-    WaitSet.push_back(IR);
-    return;
-  }
-
-  // Don't add a zero-latency instruction to the Ready queue.
-  // A zero-latency instruction doesn't consume any scheduler resources. That is
-  // because it doesn't need to be executed, and it is often removed at register
-  // renaming stage. For example, register-register moves are often optimized at
-  // register renaming stage by simply updating register aliases. On some
-  // targets, zero-idiom instructions (for example: a xor that clears the value
-  // of a register) are treated specially, and are often eliminated at register
-  // renaming stage.
-  if (!mustIssueImmediately(IR)) {
-    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the ReadySet\n");
-    ReadySet.push_back(IR);
-  }
-}
-
-bool Scheduler::isReady(const InstRef &IR) const {
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-  bool IsMemOp = Desc.MayLoad || Desc.MayStore;
-  return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
-}
-
 } // namespace mca

tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp

 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RetireControlUnit.h"
+#include "HardwareUnits/RetireControlUnit.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp

+//===--------------------- Scheduler.cpp ------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// A scheduler for processor resource units and processor resource groups.
+//
+//===----------------------------------------------------------------------===//
+
+#include "HardwareUnits/Scheduler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+namespace mca {
+
+using namespace llvm;
+
+#define DEBUG_TYPE "llvm-mca"
+
+void Scheduler::initializeStrategy(std::unique_ptr<SchedulerStrategy> S) {
+  // Ensure we have a valid (non-null) strategy object.
+  Strategy = S ? std::move(S) : llvm::make_unique<DefaultSchedulerStrategy>();
+}
+
+// Anchor the vtable of SchedulerStrategy and DefaultSchedulerStrategy.
+SchedulerStrategy::~SchedulerStrategy() = default;
+DefaultSchedulerStrategy::~DefaultSchedulerStrategy() = default;
+
+#ifndef NDEBUG
+void Scheduler::dump() const {
+  dbgs() << "[SCHEDULER]: WaitSet size is: " << WaitSet.size() << '\n';
+  dbgs() << "[SCHEDULER]: ReadySet size is: " << ReadySet.size() << '\n';
+  dbgs() << "[SCHEDULER]: IssuedSet size is: " << IssuedSet.size() << '\n';
+  Resources->dump();
+}
+#endif
+
+Scheduler::Status Scheduler::isAvailable(const InstRef &IR) const {
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
+
+  switch (Resources->canBeDispatched(Desc.Buffers)) {
+  case ResourceStateEvent::RS_BUFFER_UNAVAILABLE:
+    return Scheduler::SC_BUFFERS_FULL;
+  case ResourceStateEvent::RS_RESERVED:
+    return Scheduler::SC_DISPATCH_GROUP_STALL;
+  case ResourceStateEvent::RS_BUFFER_AVAILABLE:
+    break;
+  }
+
+  // Give lower priority to LSUnit stall events.
+  switch (LSU->isAvailable(IR)) {
+  case LSUnit::LSU_LQUEUE_FULL:
+    return Scheduler::SC_LOAD_QUEUE_FULL;
+  case LSUnit::LSU_SQUEUE_FULL:
+    return Scheduler::SC_STORE_QUEUE_FULL;
+  case LSUnit::LSU_AVAILABLE:
+    return Scheduler::SC_AVAILABLE;
+  }
+
+  llvm_unreachable("Don't know how to process this LSU state result!");
+}
+
+void Scheduler::issueInstructionImpl(
+    InstRef &IR,
+    SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources) {
+  Instruction *IS = IR.getInstruction();
+  const InstrDesc &D = IS->getDesc();
+
+  // Issue the instruction and collect all the consumed resources
+  // into a vector. That vector is then used to notify the listener.
+  Resources->issueInstruction(D, UsedResources);
+
+  // Notify the instruction that it started executing.
+  // This updates the internal state of each write.
+  IS->execute();
+
+  if (IS->isExecuting())
+    IssuedSet.emplace_back(IR);
+  else if (IS->isExecuted())
+    LSU->onInstructionExecuted(IR);
+}
+
+// Release the buffered resources and issue the instruction.
+void Scheduler::issueInstruction(
+    InstRef &IR, SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources,
+    SmallVectorImpl<InstRef> &ReadyInstructions) {
+  const Instruction &Inst = *IR.getInstruction();
+  bool HasDependentUsers = Inst.hasDependentUsers();
+
+  Resources->releaseBuffers(Inst.getDesc().Buffers);
+  issueInstructionImpl(IR, UsedResources);
+  // Instructions that have been issued during this cycle might have unblocked
+  // other dependent instructions. Dependent instructions may be issued during
+  // this same cycle if operands have ReadAdvance entries.  Promote those
+  // instructions to the ReadySet and notify the caller that those are ready.
+  if (HasDependentUsers)
+    promoteToReadySet(ReadyInstructions);
+}
+
+void Scheduler::promoteToReadySet(SmallVectorImpl<InstRef> &Ready) {
+  // Scan the set of waiting instructions and promote them to the
+  // ready queue if operands are all ready.
+  unsigned RemovedElements = 0;
+  for (auto I = WaitSet.begin(), E = WaitSet.end(); I != E;) {
+    InstRef &IR = *I;
+    if (!IR.isValid())
+      break;
+
+    // Check if this instruction is now ready. In case, force
+    // a transition in state using method 'update()'.
+    Instruction &IS = *IR.getInstruction();
+    if (!IS.isReady())
+      IS.update();
+
+    // Check if there are still unsolved data dependencies.
+    if (!isReady(IR)) {
+      ++I;
+      continue;
+    }
+
+    Ready.emplace_back(IR);
+    ReadySet.emplace_back(IR);
+
+    IR.invalidate();
+    ++RemovedElements;
+    std::iter_swap(I, E - RemovedElements);
+  }
+
+  WaitSet.resize(WaitSet.size() - RemovedElements);
+}
+
+InstRef Scheduler::select() {
+  unsigned QueueIndex = ReadySet.size();
+  for (unsigned I = 0, E = ReadySet.size(); I != E; ++I) {
+    const InstRef &IR = ReadySet[I];
+    if (QueueIndex == ReadySet.size() ||
+        Strategy->compare(IR, ReadySet[QueueIndex])) {
+      const InstrDesc &D = IR.getInstruction()->getDesc();
+      if (Resources->canBeIssued(D))
+        QueueIndex = I;
+    }
+  }
+
+  if (QueueIndex == ReadySet.size())
+    return InstRef();
+
+  // We found an instruction to issue.
+  InstRef IR = ReadySet[QueueIndex];
+  std::swap(ReadySet[QueueIndex], ReadySet[ReadySet.size() - 1]);
+  ReadySet.pop_back();
+  return IR;
+}
+
+void Scheduler::updateIssuedSet(SmallVectorImpl<InstRef> &Executed) {
+  unsigned RemovedElements = 0;
+  for (auto I = IssuedSet.begin(), E = IssuedSet.end(); I != E;) {
+    InstRef &IR = *I;
+    if (!IR.isValid())
+      break;
+    Instruction &IS = *IR.getInstruction();
+    if (!IS.isExecuted()) {
+      LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
+                        << " is still executing.\n");
+      ++I;
+      continue;
+    }
+
+    // Instruction IR has completed execution.
+    LSU->onInstructionExecuted(IR);
+    Executed.emplace_back(IR);
+    ++RemovedElements;
+    IR.invalidate();
+    std::iter_swap(I, E - RemovedElements);
+  }
+
+  IssuedSet.resize(IssuedSet.size() - RemovedElements);
+}
+
+void Scheduler::cycleEvent(SmallVectorImpl<ResourceRef> &Freed,
+                           SmallVectorImpl<InstRef> &Executed,
+                           SmallVectorImpl<InstRef> &Ready) {
+  // Release consumed resources.
+  Resources->cycleEvent(Freed);
+
+  // Propagate the cycle event to the 'Issued' and 'Wait' sets.
+  for (InstRef &IR : IssuedSet)
+    IR.getInstruction()->cycleEvent();
+
+  updateIssuedSet(Executed);
+
+  for (InstRef &IR : WaitSet)
+    IR.getInstruction()->cycleEvent();
+
+  promoteToReadySet(Ready);
+}
+
+bool Scheduler::mustIssueImmediately(const InstRef &IR) const {
+  // Instructions that use an in-order dispatch/issue processor resource must be
+  // issued immediately to the pipeline(s). Any other in-order buffered
+  // resources (i.e. BufferSize=1) is consumed.
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
+  return Desc.isZeroLatency() || Resources->mustIssueImmediately(Desc);
+}
+
+void Scheduler::dispatch(const InstRef &IR) {
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
+  Resources->reserveBuffers(Desc.Buffers);
+
+  // If necessary, reserve queue entries in the load-store unit (LSU).
+  bool IsMemOp = Desc.MayLoad || Desc.MayStore;
+  if (IsMemOp)
+    LSU->dispatch(IR);
+
+  if (!isReady(IR)) {
+    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
+    WaitSet.push_back(IR);
+    return;
+  }
+
+  // Don't add a zero-latency instruction to the Ready queue.
+  // A zero-latency instruction doesn't consume any scheduler resources. That is
+  // because it doesn't need to be executed, and it is often removed at register
+  // renaming stage. For example, register-register moves are often optimized at
+  // register renaming stage by simply updating register aliases. On some
+  // targets, zero-idiom instructions (for example: a xor that clears the value
+  // of a register) are treated specially, and are often eliminated at register
+  // renaming stage.
+  if (!mustIssueImmediately(IR)) {
+    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the ReadySet\n");
+    ReadySet.push_back(IR);
+  }
+}
+
+bool Scheduler::isReady(const InstRef &IR) const {
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
+  bool IsMemOp = Desc.MayLoad || Desc.MayStore;
+  return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
+}
+
+} // namespace mca

tools/llvm-mca/lib/LLVMBuild.txt

+;===- ./tools/llvm-mca/lib/LLVMBuild.txt -----------------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = MCA
+parent = Libraries
+required_libraries = CodeGen MC Support

tools/llvm-mca/lib/Stages/DispatchStage.cpp

 /// This file models the dispatch component of an instruction pipeline.
 ///
 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "DispatchStage.h"
+#include "Stages/DispatchStage.h"
 #include "HWEventListener.h"
-#include "Scheduler.h"
+#include "HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/lib/Stages/ExecuteStage.cpp

 ///
 /// This file defines the execution stage of an instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "ExecuteStage.h"
+#include "Stages/ExecuteStage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 using namespace llvm;

tools/llvm-mca/lib/Stages/FetchStage.cpp

 //===---------------------- FetchStage.cpp ----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the Fetch stage of an instruction pipeline.  Its sole
 /// purpose in life is to produce instructions for the rest of the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "FetchStage.h"
+#include "Stages/FetchStage.h"
 
 namespace mca {
 
 bool FetchStage::hasWorkToComplete() const {
   return CurrentInstruction.get() || SM.hasNext();
 }
 
 bool FetchStage::isAvailable(const InstRef & /* unused */) const {

tools/llvm-mca/lib/Stages/InstructionTables.cpp

 ///
 /// This file implements the method InstructionTables::execute().
 /// Method execute() prints a theoretical resource pressure distribution based
 /// on the information available in the scheduling model, and without running
 /// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "InstructionTables.h"
+#include "Stages/InstructionTables.h"
 
 namespace mca {
 
 using namespace llvm;
 
 Error InstructionTables::execute(InstRef &IR) {
   ArrayRef<uint64_t> Masks = IB.getProcResourceMasks();
   const InstrDesc &Desc = IR.getInstruction()->getDesc();

tools/llvm-mca/lib/Stages/RetireStage.cpp

 //===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the retire stage of an instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "RetireStage.h"
+#include "Stages/RetireStage.h"
 #include "HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 llvm::Error RetireStage::cycleStart() {

tools/llvm-mca/lib/Stages/Stage.cpp

 //===---------------------- Stage.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Stage.h"
+#include "Stages/Stage.h"
 
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::~Stage() = default;
 
 void Stage::addListener(HWEventListener *Listener) {
   Listeners.insert(Listener);
 }
 
 } // namespace mca

tools/llvm-mca/llvm-mca.cpp

 //
 // The target defaults to the host target.
 // The cpu defaults to the 'native' host cpu.
 // The output defaults to standard output.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeRegion.h"
-#include "Context.h"
-#include "DispatchStatistics.h"
-#include "FetchStage.h"
-#include "InstructionInfoView.h"
-#include "InstructionTables.h"
-#include "Pipeline.h"
 #include "PipelinePrinter.h"
-#include "RegisterFileStatistics.h"
-#include "ResourcePressureView.h"
-#include "RetireControlUnitStatistics.h"
-#include "SchedulerStatistics.h"
-#include "SummaryView.h"
-#include "TimelineView.h"
+#include "Stats/DispatchStatistics.h"
+#include "Stats/RegisterFileStatistics.h"
+#include "Stats/RetireControlUnitStatistics.h"
+#include "Stats/SchedulerStatistics.h"
+#include "Views/InstructionInfoView.h"
+#include "Views/ResourcePressureView.h"
+#include "Views/SummaryView.h"
+#include "Views/TimelineView.h"
+#include "include/Context.h"
+#include "include/Pipeline.h"
+#include "include/Stages/FetchStage.h"
+#include "include/Stages/InstructionTables.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"