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Differential D50437

[mips] Implement pll.ps, plu.ps and some of the missing cvt.* instructions
ClosedPublic

Authored by abeserminji on Aug 8 2018, 4:27 AM.
Tokens
"Like" token, awarded by xiangzhai.

Details

Reviewers
atanasyan
smaksimovic
petarj
Commits
rGf8f00e5065f7: [mips] Add missing instructions
rL340920: [mips] Add missing instructions
Summary

Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.

Diff Detail

Repository
rL LLVM

Event Timeline

abeserminji created this revision.Aug 8 2018, 4:27 AM
Herald added subscribers: jrtc27, arichardson, sdardis. · View Herald TranscriptAug 8 2018, 4:27 AM
abeserminji updated this revision to Diff 159882.Aug 9 2018, 2:53 AM

Fix forgotten TODOs.

atanasyan accepted this revision.Aug 14 2018, 10:42 PM

LGTM

This revision is now accepted and ready to land.Aug 14 2018, 10:42 PM
abeserminji planned changes to this revision.Aug 20 2018, 3:54 AM

After reviewing the instruction manual again, I noticed the following in the Restrictions section:
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
Which makes some of the definitions in the patch wrong. Should fix that.

abeserminji updated this revision to Diff 161474.Aug 20 2018, 7:36 AM

Removed instruction definitions for FP32, which would, by the statement in the instruction manual, cause an unpredictable results.

This revision is now accepted and ready to land.Aug 20 2018, 7:36 AM
abeserminji updated this revision to Diff 162329.Aug 24 2018, 1:19 AM

Fix predicates and update tests.

smaksimovic accepted this revision.Aug 24 2018, 2:01 AM

LGTM

abeserminji updated this revision to Diff 162845.Aug 28 2018, 6:31 AM
abeserminji edited the summary of this revision. (Show Details)

Removed unnecessary changes.
Description updated.

Closed by commit rL340920: [mips] Add missing instructions (authored by abeserminji). · Explain WhyAug 29 2018, 4:35 AM
This revision was automatically updated to reflect the committed changes.
xiangzhai awarded a token.Sep 3 2018, 7:34 PM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
32 lines
test/
MC/
Disassembler/
Mips/
mips32r2/
7 lines
7 lines
mips32r3/
7 lines
7 lines
mips32r5/
7 lines
7 lines
Mips/
mips1/
5 lines
5 lines
mips2/
5 lines
5 lines
mips3/
5 lines
5 lines
mips4/
5 lines
5 lines
mips64r2/
5 lines
10 lines
mips64r3/
5 lines
10 lines
mips64r5/
5 lines
10 lines
mips64r6/
3 lines

Diff 163050

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
[(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
HARDFLOAT, HARDFLOAT,
NeverHasSideEffects; NeverHasSideEffects;
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
[(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
HARDFLOAT {
let isCommutable = IsComm;
}
multiclass ABSS_M<string opstr, InstrItinClass Itin, multiclass ABSS_M<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> { SDPatternOperator OpNode= null_frag> {
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
FGR_32; FGR_32;
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
string DecoderNamespace = "MipsFP64"; string DecoderNamespace = "MipsFP64";
} }
} }
▲ Show 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
} }
let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2C, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2D, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x28, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,
ADDS_FM<0x26, 16>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
}
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
▲ Show 20 Lines • Show All 494 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

llvm/trunk/test/MC/Mips/mips1/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Show All 27 Lines

llvm/trunk/test/MC/Mips/mips1/invalid-mips5.s

Show All 9 Lines# RUN: FileCheck %s < %t1
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 37 Lines# RUN: FileCheck %s < %t1
movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 14 Lines

llvm/trunk/test/MC/Mips/mips2/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

llvm/trunk/test/MC/Mips/mips2/invalid-mips5.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 35 Lines# RUN: FileCheck %s < %t1
movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Show All 32 Lines

llvm/trunk/test/MC/Mips/mips3/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

llvm/trunk/test/MC/Mips/mips3/invalid-mips5.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Show All 28 Lines

llvm/trunk/test/MC/Mips/mips4/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

llvm/trunk/test/MC/Mips/mips4/invalid-mips5.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
No newline at end of file

llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s

Show All 22 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
Show All 15 Lines

llvm/trunk/test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Linesa:
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesa:
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
▲ Show 20 Lines • Show All 191 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s

Show All 25 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
Show All 15 Lines

llvm/trunk/test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Linesa:
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Linesa:
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
▲ Show 20 Lines • Show All 186 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s

Show All 25 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
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llvm/trunk/test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Linesa:
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
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nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s

Show All 22 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction