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[mips] Implement pll.ps, plu.ps and some of the missing cvt.* instructions
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Authored by abeserminji on Aug 8 2018, 4:27 AM.

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Summary

Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.

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abeserminji created this revision.Aug 8 2018, 4:27 AM

Fix forgotten TODOs.

This revision is now accepted and ready to land.Aug 14 2018, 10:42 PM
abeserminji planned changes to this revision.Aug 20 2018, 3:54 AM

After reviewing the instruction manual again, I noticed the following in the Restrictions section:
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
Which makes some of the definitions in the patch wrong. Should fix that.

Removed instruction definitions for FP32, which would, by the statement in the instruction manual, cause an unpredictable results.

This revision is now accepted and ready to land.Aug 20 2018, 7:36 AM

Fix predicates and update tests.

abeserminji edited the summary of this revision. (Show Details)

Removed unnecessary changes.
Description updated.

This revision was automatically updated to reflect the committed changes.