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Differential D50437

[mips] Implement pll.ps, plu.ps and some of the missing cvt.* instructions
ClosedPublic

Authored by abeserminji on Aug 8 2018, 4:27 AM.
Tokens
"Like" token, awarded by xiangzhai.

Details

Reviewers
atanasyan
smaksimovic
petarj
Commits
rGf8f00e5065f7: [mips] Add missing instructions
rL340920: [mips] Add missing instructions
Summary

Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.

Diff Detail

Repository
rL LLVM

Event Timeline

abeserminji created this revision.Aug 8 2018, 4:27 AM
Herald added subscribers: jrtc27, arichardson, sdardis. · View Herald TranscriptAug 8 2018, 4:27 AM
abeserminji updated this revision to Diff 159882.Aug 9 2018, 2:53 AM

Fix forgotten TODOs.

atanasyan accepted this revision.Aug 14 2018, 10:42 PM

LGTM

This revision is now accepted and ready to land.Aug 14 2018, 10:42 PM
abeserminji planned changes to this revision.Aug 20 2018, 3:54 AM

After reviewing the instruction manual again, I noticed the following in the Restrictions section:
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
Which makes some of the definitions in the patch wrong. Should fix that.

abeserminji updated this revision to Diff 161474.Aug 20 2018, 7:36 AM

Removed instruction definitions for FP32, which would, by the statement in the instruction manual, cause an unpredictable results.

This revision is now accepted and ready to land.Aug 20 2018, 7:36 AM
abeserminji updated this revision to Diff 162329.Aug 24 2018, 1:19 AM

Fix predicates and update tests.

smaksimovic accepted this revision.Aug 24 2018, 2:01 AM

LGTM

abeserminji updated this revision to Diff 162845.Aug 28 2018, 6:31 AM
abeserminji edited the summary of this revision. (Show Details)

Removed unnecessary changes.
Description updated.

Closed by commit rL340920: [mips] Add missing instructions (authored by abeserminji). · Explain WhyAug 29 2018, 4:35 AM
This revision was automatically updated to reflect the committed changes.
xiangzhai awarded a token.Sep 3 2018, 7:34 PM

Revision Contents

PathSize
lib/
Target/
Mips/
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7 lines
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test/
MC/
Disassembler/
Mips/
mips3/
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mips32r2/
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7 lines
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mips32r3/
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mips32r5/
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Mips/
mips1/
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mips2/
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mips3/
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mips32r2/
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mips32r3/
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mips32r5/
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mips4/
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mips5/
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mips64/
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mips64r2/
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mips64r3/
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mips64r5/
5 lines
12 lines
mips64r6/
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Diff 159681

lib/Target/Mips/MipsInstrFPU.td

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class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
[(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
HARDFLOAT, HARDFLOAT,
NeverHasSideEffects; NeverHasSideEffects;
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
[(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
HARDFLOAT {
let isCommutable = IsComm;
}
multiclass ABSS_M<string opstr, InstrItinClass Itin, multiclass ABSS_M<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> { SDPatternOperator OpNode= null_frag> {
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
FGR_32; FGR_32;
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
string DecoderNamespace = "MipsFP64"; string DecoderNamespace = "MipsFP64";
} }
} }
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let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
def CVT_D32_L : ABSS_FT<"cvt.d.l", AFGR64Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_32;
def CVT_S_L32 : ABSS_FT<"cvt.s.l", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_32;
} }
let AdditionalPredicates = [NotInMicroMips] in {
def PLL_PS32 : ADDS_FT<"pll.ps", AFGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2C, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_32;
def PLU_PS32 : ADDS_FT<"plu.ps", AFGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2D, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_32;
def CVT_S_PU32 : ABSS_FT<"cvt.s.pu", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_32;
def CVT_S_PL32 : ABSS_FT<"cvt.s.pl", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x28, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_32;
def CVT_PS_S32 : CVT_PS_S_FT<"cvt.ps.s", AFGR64Opnd, FGR32Opnd, II_CVT, 0>,
ADDS_FM<0x26, 16>,
INSN_MIPS3_32R2_NOT_64R6, FGR_32;
}
let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2C, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_64;
def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
ADDS_FM<0x2D, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_64;
def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_64;
def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x28, 22>,
INSN_MIPS3_32R2_NOT_64R6, FGR_64;
def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,
ADDS_FM<0x26, 16>,
INSN_MIPS3_32R2_NOT_64R6, FGR_64;
}
}
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_L64 : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64; ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
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lib/Target/Mips/MipsInstrInfo.td

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} }
// The portions of MIPS-III that were also added to MIPS32 // The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32R2 { class INSN_MIPS3_32R2 {
list<Predicate> InsnPredicates = [HasMips3_32r2]; list<Predicate> InsnPredicates = [HasMips3_32r2];
list<Predicate> EncodingPredicates = [HasStdEnc]; list<Predicate> EncodingPredicates = [HasStdEnc];
} }
// The portions of MIPS-III that were also added to MIPS32 but were removed in
// MIPS64r6.
class INSN_MIPS3_32R2_NOT_64R6 {
list<Predicate> InsnPredicates = [HasMips3_32r2, NotMips64r6];
list<Predicate> EncodingPredicates = [HasStdEnc];
}
// The portions of MIPS-IV that were also added to MIPS32. // The portions of MIPS-IV that were also added to MIPS32.
class INSN_MIPS4_32 { class INSN_MIPS4_32 {
list <Predicate> InsnPredicates = [HasMips4_32]; list <Predicate> InsnPredicates = [HasMips4_32];
list<Predicate> EncodingPredicates = [HasStdEnc]; list<Predicate> EncodingPredicates = [HasStdEnc];
} }
// The portions of MIPS-IV that were also added to MIPS32 but were removed in // The portions of MIPS-IV that were also added to MIPS32 but were removed in
// MIPS32r6 and MIPS64r6. // MIPS32r6 and MIPS64r6.
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lib/Target/Mips/MipsSEInstrInfo.cpp

Show First 20 Lines • Show All 440 Lines • ▼ Show 20 Linesbool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case Mips::PseudoCVT_S_W: case Mips::PseudoCVT_S_W:
expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
break; break;
case Mips::PseudoCVT_D32_W: case Mips::PseudoCVT_D32_W:
Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
break; break;
case Mips::PseudoCVT_S_L: case Mips::PseudoCVT_S_L:
expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); // if (64)
expandCvtFPInt(MBB, MI, Mips::CVT_S_L64, Mips::DMTC1, true);
// else
// expandCvtFPInt(MBB, MI, Mips::CVT_S_L32, Mips::DMTC1, true);
break; break;
case Mips::PseudoCVT_D64_W: case Mips::PseudoCVT_D64_W:
Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
break; break;
case Mips::PseudoCVT_D64_L: case Mips::PseudoCVT_D64_L:
// if (64)
expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
// else
// expandCvtFPInt(MBB, MI, Mips::CVT_D32_L, Mips::DMTC1, true);
break; break;
case Mips::BuildPairF64: case Mips::BuildPairF64:
expandBuildPairF64(MBB, MI, isMicroMips, false); expandBuildPairF64(MBB, MI, isMicroMips, false);
break; break;
case Mips::BuildPairF64_64: case Mips::BuildPairF64_64:
expandBuildPairF64(MBB, MI, isMicroMips, true); expandBuildPairF64(MBB, MI, isMicroMips, true);
break; break;
case Mips::ExtractElementF64: case Mips::ExtractElementF64:
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lib/Target/Mips/MipsSchedule.td

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def II_NMADD_S : InstrItinClass; def II_NMADD_S : InstrItinClass;
def II_NMSUB_D : InstrItinClass; def II_NMSUB_D : InstrItinClass;
def II_NMSUB_S : InstrItinClass; def II_NMSUB_S : InstrItinClass;
def II_NOR : InstrItinClass; def II_NOR : InstrItinClass;
def II_NOT : InstrItinClass; def II_NOT : InstrItinClass;
def II_OR : InstrItinClass; def II_OR : InstrItinClass;
def II_ORI : InstrItinClass; def II_ORI : InstrItinClass;
def II_POP : InstrItinClass; def II_POP : InstrItinClass;
def II_PL : InstrItinClass;
def II_RDHWR : InstrItinClass; def II_RDHWR : InstrItinClass;
def II_RESTORE : InstrItinClass; def II_RESTORE : InstrItinClass;
def II_RECIP_S : InstrItinClass; def II_RECIP_S : InstrItinClass;
def II_RECIP_D : InstrItinClass; def II_RECIP_D : InstrItinClass;
def II_RINT_S : InstrItinClass; def II_RINT_S : InstrItinClass;
def II_RINT_D : InstrItinClass; def II_RINT_D : InstrItinClass;
def II_ROTR : InstrItinClass; def II_ROTR : InstrItinClass;
def II_ROTRV : InstrItinClass; def II_ROTRV : InstrItinClass;
▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Linesdef MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>, InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>, InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_PL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>, InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>,
InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>, InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>,
InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>, InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>, InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>,
InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>, InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>, InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>,
InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>, InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>,
InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>,
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test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt

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0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16 0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0x25 0x7e 0x20 0x46 # CHECK: cvt.l.d $f24, $f15 0x25 0x7e 0x20 0x46 # CHECK: cvt.l.d $f24, $f15
0xe5 0xea 0x00 0x46 # CHECK: cvt.l.s $f11, $f29 0xe5 0xea 0x00 0x46 # CHECK: cvt.l.s $f11, $f29
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30 0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0x46 0x20 0x46 # CHECK: cvt.s.d $f26, $f8 0xa0 0x46 0x20 0x46 # CHECK: cvt.s.d $f26, $f8
0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15 0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15
0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14 0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14
0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24 0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra 0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705 0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705 0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705 0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705 0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705 0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586 0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra 0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
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test/MC/Disassembler/Mips/mips3/valid-mips3.txt

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0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4
0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7
0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8
0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10
0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14
0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14
0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14
0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15 0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18
0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22
0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23
0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24
0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24
0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0
0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16
0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14 0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14 0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7 0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14 0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14 0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x60 0x7e 0x41 # CHECK: di $fp 0x00 0x60 0x7e 0x41 # CHECK: di $fp
0x00 0x60 0x60 0x41 # CHECK: di 0x00 0x60 0x60 0x41 # CHECK: di
0x20 0x60 0x6e 0x41 # CHECK: ei $14 0x20 0x60 0x6e 0x41 # CHECK: ei $14
0x20 0x60 0x60 0x41 # CHECK: ei 0x20 0x60 0x60 0x41 # CHECK: ei
0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14 0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7 0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
0x4c 0x01 0x00 0x08 # CHECK: j 1328 0x4c 0x01 0x00 0x08 # CHECK: j 1328
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9
0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16
0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20
0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24
0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero 0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero
0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28
▲ Show 20 Lines • Show All 169 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6 0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0 0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4 0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4 0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2 0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16 0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16 0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14 0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14 0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7 0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14 0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14 0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x60 0x7e 0x41 # CHECK: di $fp 0x00 0x60 0x7e 0x41 # CHECK: di $fp
0x00 0x60 0x60 0x41 # CHECK: di 0x00 0x60 0x60 0x41 # CHECK: di
0x20 0x60 0x6e 0x41 # CHECK: ei $14 0x20 0x60 0x6e 0x41 # CHECK: ei $14
0x20 0x60 0x60 0x41 # CHECK: ei 0x20 0x60 0x60 0x41 # CHECK: ei
0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14 0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7 0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
0x4c 0x01 0x00 0x08 # CHECK: j 1328 0x4c 0x01 0x00 0x08 # CHECK: j 1328
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9
0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16
0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20
0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24
0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero 0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero
0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28
▲ Show 20 Lines • Show All 169 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14 0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6 0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0 0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4 0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4 0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2 0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16 0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16 0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt

Show All 9 Lines
0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4
0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4
0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2
0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2
0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2
0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2
0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2
0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0
0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt

Show All 9 Lines
0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4
0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4
0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2
0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2
0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2
0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2
0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2
0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0
0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14 0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14 0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7 0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14 0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14 0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20
0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
0x00 0x60 0x7e 0x41 # CHECK: di $fp 0x00 0x60 0x7e 0x41 # CHECK: di $fp
0x00 0x60 0x60 0x41 # CHECK: di 0x00 0x60 0x60 0x41 # CHECK: di
0x20 0x60 0x6e 0x41 # CHECK: ei $14 0x20 0x60 0x6e 0x41 # CHECK: ei $14
0x20 0x60 0x60 0x41 # CHECK: ei 0x20 0x60 0x60 0x41 # CHECK: ei
0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14 0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7 0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
0x4c 0x01 0x00 0x08 # CHECK: j 1328 0x4c 0x01 0x00 0x08 # CHECK: j 1328
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9
0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16
0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20
0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24
0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero 0x46 0x00 0xc5 0x53 # CHECK: movn.s $f21, $f24, $zero
0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28 0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2 0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0 0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4 0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4 0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2 0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16 0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6 0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16 0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16 0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5

test/MC/Mips/mips1/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
Show All 27 Lines

test/MC/Mips/mips2/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips3/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

test/MC/Mips/mips32r2/valid-xfail.s

Show All 26 Lines# XFAIL: *
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0 dmt $k0
dvpe $s6 dvpe $s6
emt $8 emt $8
evpe $v0 evpe $v0
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
fork $s2,$8,$a0 fork $s2,$8,$a0
iret iret
Show All 14 Lines# XFAIL: *
movz.ps $f18,$f17,$ra movz.ps $f18,$f17,$ra
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
Show All 19 Lines

test/MC/Mips/mips32r3/valid-xfail.s

Show All 26 Lines# XFAIL: *
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0 dmt $k0
dvpe $s6 dvpe $s6
emt $8 emt $8
evpe $v0 evpe $v0
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
fork $s2,$8,$a0 fork $s2,$8,$a0
iret iret
Show All 14 Lines# XFAIL: *
movz.ps $f18,$f17,$ra movz.ps $f18,$f17,$ra
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
Show All 19 Lines

test/MC/Mips/mips32r5/valid-xfail.s

Show All 26 Lines# XFAIL: *
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0 dmt $k0
dvpe $s6 dvpe $s6
emt $8 emt $8
evpe $v0 evpe $v0
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
fork $s2,$8,$a0 fork $s2,$8,$a0
iret iret
Show All 14 Lines# XFAIL: *
movz.ps $f18,$f17,$ra movz.ps $f18,$f17,$ra
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
Show All 19 Lines

test/MC/Mips/mips4/invalid-mips5-wrong-error.s

Show All 19 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid-xfail.s

Show All 20 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
madd.ps $f22,$f3,$f14,$f3 madd.ps $f22,$f3,$f14,$f3
mov.ps $f22,$f17 mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6 movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3 movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2 movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra movz.ps $f18,$f17,$ra
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Linesa:
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c] round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c]
# CHECK: # <MCInst #{{.*}} ROUND_W_D64 # CHECK: # <MCInst #{{.*}} ROUND_W_D64
round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc] round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

test/MC/Mips/mips64/valid-xfail.s

Show All 23 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
madd.ps $f22,$f3,$f14,$f3 madd.ps $f22,$f3,$f14,$f3
mov.ps $f22,$f17 mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6 movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3 movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2 movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra movz.ps $f18,$f17,$ra
msgn.qh $v0,$v24,$v20 msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
sub.ps $f5,$f14,$f26 sub.ps $f5,$f14,$f26

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Linesa:
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop nop
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5] recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
round.l.d $f12,$f1 round.l.d $f12,$f1
round.l.s $f25,$f5 round.l.s $f25,$f5
round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c] round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c]
# CHECK: # <MCInst #{{.*}} ROUND_W_D64 # CHECK: # <MCInst #{{.*}} ROUND_W_D64
round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc] round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid-xfail.s

Show All 22 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
Show All 15 Lines

test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesa:
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
▲ Show 20 Lines • Show All 191 Lines • Show Last 20 Lines

test/MC/Mips/mips64r3/valid-xfail.s

Show All 25 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
Show All 15 Lines

test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Linesa:
nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
▲ Show 20 Lines • Show All 186 Lines • Show Last 20 Lines

test/MC/Mips/mips64r5/valid-xfail.s

Show All 25 Lines# XFAIL: *
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
drorv $at,$a1,$s7 drorv $at,$a1,$s7
dvpe $s6 dvpe $s6
emt $8 emt $8
Show All 19 Lines# XFAIL: *
msgn.qh $v12,$v21,$v0[1] msgn.qh $v12,$v21,$v0[1]
msub.ps $f12,$f14,$f29,$f17 msub.ps $f12,$f14,$f29,$f17
mtc0 $9,c0_datahi1 mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7 mtgc0 $s4,$21,7
mul.ps $f14,$f0,$f16 mul.ps $f14,$f0,$f16
neg.ps $f19,$f13 neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25 nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17 nmsub.ps $f6,$f12,$f14,$f17
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15 preceq.w.phr $s5,$15
pul.ps $f9,$f30,$f26 pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2 puu.ps $f24,$f9,$f2
rdpgpr $s3,$9 rdpgpr $s3,$9
rorv $13,$a3,$s5 rorv $13,$a3,$s5
sbe $s7,33($s1) sbe $s7,33($s1)
sce $sp,189($10) sce $sp,189($10)
Show All 15 Lines

test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Linesa:
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25] cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5] cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0] cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0] cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L # CHECK: # <MCInst #{{[0-9]+}} CVT_S_L64
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0] cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W # CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24] cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
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nor $a3,$zero,$a3 nor $a3,$zero,$a3
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $12,$s0,$sp or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5] recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
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test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s

Show All 22 Lines .set noat
c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction