[MIPS GlobalISel] Select bitwise instructions

[Petar.Avramovic]

Summary

Select bitwise instructions for i32.

[atanasyan]

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

1

Is this ll file really generated by update_mir_test_check.py?

[Petar.Avramovic]

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

1

Yes, partially. I wrote ll input and script generated this test file.

[atanasyan]

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

1

I mean why don’t you use update_llc_test_check.py?

[Petar.Avramovic]

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

1

When we stop after some function pass in llc update_mir_test_check.py is used to generate mir test. However when we let llc run until the end update_llc_test_check.py is used, such tests are located in Mips/GlobalISel/llvm-ir/. Remaining folders in Mips/GlobalISel/ contain mir tests for each Global ISel function pass.

[atanasyan]

LGTM

lib/Target/Mips/MipsLegalizerInfo.cpp

MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   const LLT s32 = LLT::scalar(32);
   const LLT p0 = LLT::pointer(0, 32);
 
   getActionDefinitionsBuilder(G_ADD).legalFor({s32});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForCartesianProduct({p0, s32}, {p0});
 
+  getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR})
+      .legalFor({s32});
+
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({s32});
 
   getActionDefinitionsBuilder(G_GEP)
       .legalFor({{p0, s32}});
 
   getActionDefinitionsBuilder(G_FRAME_INDEX)
       .legalFor({p0});
 
   getActionDefinitionsBuilder(G_GLOBAL_VALUE)
       .legalFor({p0});
 
   computeTables();
   verify(*ST.getInstrInfo());
 }

lib/Target/Mips/MipsRegisterBankInfo.cpp

MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
 
   switch (Opc) {
   case G_ADD:
   case G_LOAD:
   case G_STORE:
   case G_GEP:
+  case G_AND:
+  case G_OR:
+  case G_XOR:
+  case G_SHL:
+  case G_ASHR:
+  case G_LSHR:
     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
     break;
   case G_CONSTANT:
   case G_FRAME_INDEX:
   case G_GLOBAL_VALUE:
     OperandsMapping =
         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
     break;
   default:
     return getInvalidInstructionMapping();
   }
 
   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
                                NumOperands);
 }

test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @and(i32, i32) {entry: ret void}
+  define void @or(i32, i32) {entry: ret void}
+  define void @xor(i32, i32) {entry: ret void}
+  define void @shl(i32) {entry: ret void}
+  define void @ashr(i32) {entry: ret void}
+  define void @lshr(i32) {entry: ret void}
+  define void @shlv(i32, i32) {entry: ret void}
+  define void @ashrv(i32, i32) {entry: ret void}
+  define void @lshrv(i32, i32) {entry: ret void}
+
+...
+---
+name:            and
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: and
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_AND %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            or
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: or
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[OR]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_OR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            xor
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: xor
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[XOR]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_XOR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shl
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: shl
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
+    ; MIPS32: $v0 = COPY [[SLL]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 1
+    %2:gprb(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ashr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
+    ; MIPS32: $v0 = COPY [[SRA]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 1
+    %2:gprb(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: lshr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
+    ; MIPS32: $v0 = COPY [[SRL]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 1
+    %2:gprb(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shlv
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: shlv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[SLLV]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashrv
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ashrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SRAV:%[0-9]+]]:gpr32 = SRAV [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[SRAV]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshrv
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: lshrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SRLV:%[0-9]+]]:gpr32 = SRLV [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[SRLV]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...

test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+define i32 @and(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: and
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+  ; MIPS32:   $v0 = COPY [[AND]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %and = and i32 %b, %a
+  ret i32 %and
+}
+
+define i32 @or(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: or
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+  ; MIPS32:   $v0 = COPY [[OR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %or = or i32 %b, %a
+  ret i32 %or
+}
+
+define i32 @xor(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: xor
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+  ; MIPS32:   $v0 = COPY [[XOR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %xor = xor i32 %b, %a
+  ret i32 %xor
+}
+
+define i32 @shl(i32 %a) {
+  ; MIPS32-LABEL: name: shl
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
+  ; MIPS32:   $v0 = COPY [[SHL]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shl = shl i32 %a, 1
+  ret i32 %shl
+}
+
+define i32 @ashr(i32 %a) {
+  ; MIPS32-LABEL: name: ashr
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]]
+  ; MIPS32:   $v0 = COPY [[ASHR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shr = ashr i32 %a, 1
+  ret i32 %shr
+}
+
+define i32 @lshr(i32 %a) {
+  ; MIPS32-LABEL: name: lshr
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; MIPS32:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]]
+  ; MIPS32:   $v0 = COPY [[LSHR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shr = lshr i32 %a, 1
+  ret i32 %shr
+}
+
+define i32 @shlv(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: shlv
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
+  ; MIPS32:   $v0 = COPY [[SHL]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shl = shl i32 %a, %b
+  ret i32 %shl
+}
+
+define i32 @ashrv(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: ashrv
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
+  ; MIPS32:   $v0 = COPY [[ASHR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shr = ashr i32 %a, %b
+  ret i32 %shr
+}
+
+define i32 @lshrv(i32 %a, i32 %b) {
+  ; MIPS32-LABEL: name: lshrv
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]]
+  ; MIPS32:   $v0 = COPY [[LSHR]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %shr = lshr i32 %a, %b
+  ret i32 %shr
+}
+

test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @and(i32, i32) {entry: ret void}
+  define void @or(i32, i32) {entry: ret void}
+  define void @xor(i32, i32) {entry: ret void}
+  define void @shl(i32) {entry: ret void}
+  define void @ashr(i32) {entry: ret void}
+  define void @lshr(i32) {entry: ret void}
+  define void @shlv(i32, i32) {entry: ret void}
+  define void @ashrv(i32, i32) {entry: ret void}
+  define void @lshrv(i32, i32) {entry: ret void}
+
+...
+---
+name:            and
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: and
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_AND %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            or
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: or
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[OR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_OR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            xor
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: xor
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[XOR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_XOR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shl
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: shl
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[SHL]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashr
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ashr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[ASHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshr
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: lshr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[LSHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shlv
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: shlv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[SHL]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashrv
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ashrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[ASHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshrv
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: lshrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[LSHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...

test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32 @and(i32 %a, i32 %b) {
+; MIPS32-LABEL: and:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    and $2, $5, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %and = and i32 %b, %a
+  ret i32 %and
+}
+
+define i32 @or(i32 %a, i32 %b) {
+; MIPS32-LABEL: or:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    or $2, $5, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %or = or i32 %b, %a
+  ret i32 %or
+}
+
+define i32 @xor(i32 %a, i32 %b) {
+; MIPS32-LABEL: xor:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $2, $5, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %xor = xor i32 %b, %a
+  ret i32 %xor
+}
+
+define i32 @shl(i32 %a) {
+; MIPS32-LABEL: shl:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $2, $4, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shl = shl i32 %a, 1
+  ret i32 %shl
+}
+
+define i32 @ashr(i32 %a) {
+; MIPS32-LABEL: ashr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sra $2, $4, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shr = ashr i32 %a, 1
+  ret i32 %shr
+}
+
+define i32 @lshr(i32 %a) {
+; MIPS32-LABEL: lshr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    srl $2, $4, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shr = lshr i32 %a, 1
+  ret i32 %shr
+}
+
+define i32 @shlv(i32 %a, i32 %b) {
+; MIPS32-LABEL: shlv:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sllv $2, $4, $5
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shl = shl i32 %a, %b
+  ret i32 %shl
+}
+
+define i32 @ashrv(i32 %a, i32 %b) {
+; MIPS32-LABEL: ashrv:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    srav $2, $4, $5
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shr = ashr i32 %a, %b
+  ret i32 %shr
+}
+
+define i32 @lshrv(i32 %a, i32 %b) {
+; MIPS32-LABEL: lshrv:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    srlv $2, $4, $5
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %shr = lshr i32 %a, %b
+  ret i32 %shr
+}
+

test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+
+  define void @and(i32, i32) {entry: ret void}
+  define void @or(i32, i32) {entry: ret void}
+  define void @xor(i32, i32) {entry: ret void}
+  define void @shl(i32) {entry: ret void}
+  define void @ashr(i32) {entry: ret void}
+  define void @lshr(i32) {entry: ret void}
+  define void @shlv(i32, i32) {entry: ret void}
+  define void @ashrv(i32, i32) {entry: ret void}
+  define void @lshrv(i32, i32) {entry: ret void}
+
+...
+---
+name:            and
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: and
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_AND %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            or
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: or
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[OR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_OR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            xor
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: xor
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[XOR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_XOR %1, %0
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shl
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: shl
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[SHL]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashr
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ashr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[ASHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshr
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: lshr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]]
+    ; MIPS32: $v0 = COPY [[LSHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            shlv
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: shlv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[SHL]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_SHL %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ashrv
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ashrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[ASHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_ASHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            lshrv
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: lshrv
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[LSHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...