[MIPS GlobalISel] Lower pointer arguments

[Petar.Avramovic]

Summary

Add support for lowering pointer arguments.
Changing type from pointer to integer is already done in MipsTargetLowering::getRegisterTypeForCallingConv.

[Petar.Avramovic]

Does anybody have any comment?

[atanasyan]

lib/Target/Mips/MipsCallLowering.cpp

189

Maybe a stupid question - why does this function return true for pointer types of any size (32/64) and the only size of integer type (32)?

[Petar.Avramovic]

lib/Target/Mips/MipsCallLowering.cpp

189

As MipsCallLowering class is incomplete, it can only lower i32 and pointer arguments at this moment.
isSupportedType is used for quick exit until we can lower arguments of any type.

[atanasyan]

lib/Target/Mips/MipsCallLowering.cpp

189

What happens if we try to generate 64-bit code with 64-bit pointers - will the isSupportedType be called or not?

[Petar.Avramovic]

lib/Target/Mips/MipsCallLowering.cpp

189

In that case isSupportedType will be called, later TLI.getRegisterTypeForCallingConv will change pointer type to appropriate integer type(i64 in this case) and forward it to the calling convention.
However attempt to generate code for MIPS 64 will fail elsewhere as globalisel for MIPS is incomplete. At first, we add code and test for MIPS 32.

[atanasyan]

LGTM

lib/Target/Mips/MipsCallLowering.cpp

189

Thanks for the explanation. I just want to be sure that we cannot silently produce incorrect code.

lib/Target/Mips/MipsCallLowering.cpp

if (!assign(ArgLocs[i], Args[i].Reg))
       return false;
   }
   return true;
 }
 
 static bool isSupportedType(Type *T) {
   if (T->isIntegerTy() && T->getScalarSizeInBits() == 32)
     return true;
+  if (T->isPointerTy())
+    return true;
   return false;
 }
 
 bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                    const Value *Val, unsigned VReg) const {
 
   MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
 

lib/Target/Mips/MipsLegalizerInfo.cpp

MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   using namespace TargetOpcode;
 
   const LLT s32 = LLT::scalar(32);
   const LLT p0 = LLT::pointer(0, 32);
 
   getActionDefinitionsBuilder(G_ADD).legalFor({s32});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
-      .legalFor({{s32, p0}});
+      .legalForCartesianProduct({p0, s32}, {p0});
 
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({s32});
 
   getActionDefinitionsBuilder(G_GEP)
       .legalFor({{p0, s32}});
 
   getActionDefinitionsBuilder(G_FRAME_INDEX)
       .legalFor({p0});
 
   computeTables();
   verify(*ST.getInstrInfo());
 }

test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LW]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LW1]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %3:gprb(s32) = COPY $a3
+    %5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:gprb(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...

test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+
+define i32 @ptr_arg_in_regs(i32* %p) {
+  ; MIPS32-LABEL: name: ptr_arg_in_regs
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+  ; MIPS32:   $v0 = COPY [[LOAD]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {
+  ; MIPS32-LABEL: name: ptr_arg_on_stack
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+  ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+  ; MIPS32:   $v0 = COPY [[LOAD1]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i8* @ret_ptr(i8* %p) {
+  ; MIPS32-LABEL: name: ret_ptr
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+  ; MIPS32:   $v0 = COPY [[COPY]](p0)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  ret i8* %p
+}

test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD1]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    %3:_(s32) = COPY $a3
+    %5:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...

test/CodeGen/Mips/GlobalISel/llvm-ir/pointers.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32 @ptr_arg_in_regs(i32* %p) {
+; MIPS32-LABEL: ptr_arg_in_regs:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lw $2, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {
+; MIPS32-LABEL: ptr_arg_on_stack:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $1, $sp, 16
+; MIPS32-NEXT:    lw $1, 0($1)
+; MIPS32-NEXT:    lw $2, 0($1)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i8* @ret_ptr(i8* %p) {
+; MIPS32-LABEL: ret_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    move $2, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i8* %p
+}

test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+    ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD1]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    %3:_(s32) = COPY $a3
+    %5:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...