[TableGen] FixedLenDecoderEmitter: allow for dummy operand in MCInst

[tpr]

Summary

Normally a "dummy" operand, one named in InOperandList or OutOperandList
but with no bits in the instruction encoding, is not included in an
MCInst, and the autogenerated decoding code for the disassembler
generated by FixedLenDecodeEmitter reflects that: for any such dummy
operand, no MCOperand is pushed onto the MCInst.

I have a case where it would help commoning up of essentially the same
instruction between different variants of the cpu to have a dummy
operand represented in the MCInst.

Thus I have added a new field in an instruction "hasDummyOperands".
Normally 0, when set to 1 it causes the disassembler to push an
immediate zero MCOperand for any dummy operand.

There is no test for this, but a future AMDGPU commit will use it and
thus exercise it in its tests.

Change-Id: I82b7e1f75b466f24889434c1733c6dd78ec91dbd

[tpr]

The AMDGPU change that uses this is D49029.

[arsenm]

include/llvm/Target/Target.td

585–589

Dummy operand seems like the wrong name for this. Also can't this property be inferred already by checking which operands appear in the encodings? Why does an explicit bit need to be added for it?

[tpr]

include/llvm/Target/Target.td

585–589

If there is an operand that does not appear in the instruction encoding, does the MCInst decoder leave a gap for it by adding a dummy operand, or not? The latter is the current behavior, and there is some code relying on that. The new hasDummyOperands tells it to do the first behavior.

Suggestions welcome for better name.

[arsenm]

include/llvm/Target/Target.td

585–589

IncludeUnencodedOperands or something like that?

[tpr]

V2: Renamed to UseUnencodedOperands.

[tpr]

Actually I renamed it to IncludeUnencodedOperands.

[kparzysz]

Why do you need this? Do you have MCInsts with operands that are not encoded?

[tpr]

Yes we do in AMDGPU. See D49029 for a simple example of where we can use this mechanism to replace a hack where the disassembler has to manually insert an operand. I think there are some in ARM as well.

[tpr]

Ping.

[nhaehnle]

As far as I can tell, there are four kinds of operands when it comes to fixed-length encoding / decoding:

1. Normal operands that are used and encoded and decoded normally using the automatic machinery.
2. Tied operands.
3. Operands that are used, but for some reason need a special mechanism for encoding and decoding.
4. Operands that aren't used and aren't encoded / decoded.

As far as I can tell, this new mechanism would only make sense for the last category of operands. The obvious question is: why do we have such operands in the first place?

From the other patch, an example of this is the src2_modifier on multiply-accumulate V_MAC & friends instructions in AMDGPU. But since this operand isn't actually ever used, why don't we remove it instead?

Would it be possible to remove src2_modifiers from V_MAC_* instead? It seems odd to me to have operands in a MachineInstruction that are not actually ever used and must be 0.

include/llvm/Target/Target.td

class Instruction {
   /// by TableGen.
   bit UseNamedOperandTable = 0;
 
   /// Should FastISel ignore this instruction. For certain ISAs, they have
   /// instructions which map to the same ISD Opcode, value type operands and
   /// instruction selection predicates. FastISel cannot handle such cases, but
   /// SelectionDAG can.
   bit FastISelShouldIgnore = 0;
+
+  /// Normally an unencoded operand (an operand named in InOperandList or
+  /// OutOperandList but not appearing in the instruction encoding) does not
+  /// appear in the MCInst. Setting this to 1 means that the disassembler
+  /// pushes an immediate 0 operand onto the MCInst for such an operand.
+  bit IncludeUnencodedOperands = 0;
 }
 
 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
 /// Which instruction it expands to and how the operands map from the
 /// pseudo.
 class PseudoInstExpansion<dag Result> {
   dag ResultInst = Result;     // The instruction to generate.
   bit isPseudo = 1;

utils/TableGen/FixedLenDecoderEmitter.cpp

for (unsigned bi = 0; bi < Bits.getNumBits(); ++bi) {
       } else {
         ++Width;
       }
     }
 
     if (Base != ~0U)
       OpInfo.addField(Base, Width, Offset);
 
-    if (OpInfo.numFields() > 0)
+    // For an operand with no bits in the instruction encoding, push it only if
+    // IncludeUnencodedOperands is true.
+    if (OpInfo.numFields() > 0 || Def.getValueAsBit("IncludeUnencodedOperands"))
       InsnOperands.push_back(OpInfo);
   }
 
   Operands[Opc] = InsnOperands;
 
 #if 0
   LLVM_DEBUG({
       // Dumps the instruction encoding bits.