[DAGCombiner][X86][PowerPC][ARM][AMDGPU][Sparc] Replace (sub C, X) with (xor X, C) if there is no chance of a borrow during the subtraction.

[craig.topper]

Summary

This is definitely helpful on X86 where there is no subtract from an immediate instruction. So turning it into xor allows the immediate to fold.

Some of the PowerPC changes are regressions, but we may be able to fix them with other folds.

[spatel]

Looks like a generally good fold to me - prefer bitwise logic because that's the cheapest ALU op possible.

Adding some PowerPC reviewers to see if they're ok with the regression or if that must be fixed first.

[arsenm]

test/CodeGen/AMDGPU/ds-sub-offset.ll

26

This is worse in terms of code size, so ideally there would be an undo-combine for this during selection

[craig.topper]

I made an X86 specific change for this directly in isel. Abandoning.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
     VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
     if (TN->getVT() == MVT::i1) {
       SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
                                  DAG.getConstant(1, DL, VT));
       return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
     }
   }
 
+  // sub C, X -> xor X, C if there's no chance any bit will need to borrow
+  // from an adjacent bit.
+  if (ConstantSDNode *N0C = getAsNonOpaqueConstant(N0)) {
+    KnownBits Known;
+    DAG.computeKnownBits(N1, Known);
+    // Ensure all possible ones have a corresponding one in the constant.
+    if ((~Known.Zero).isSubsetOf(N0C->getAPIntValue()))
+      return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
+  }
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitSUBC(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N0.getValueType();
   SDLoc DL(N);

test/CodeGen/AMDGPU/ds-sub-offset.ll

entry:
   %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
   %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
   store i32 123, i32 addrspace(3)* %arrayidx
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
-; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
-; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
+; GCN-DAG: v_xor_b32_e32 [[NEG:v[0-9]+]], 0xffff, [[SCALED]]
 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
-; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535
+; GCN: ds_write_b8 [[NEG]], [[K]]
 define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
   %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
   %neg = sub i32 0, %x.i
   %shl = shl i32 %neg, 2
   %add = add i32 65535, %shl
   %ptr = inttoptr i32 %add to i8 addrspace(3)*
   store i8 13, i8 addrspace(3)* %ptr
   ret void
define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
   %add = add i32 1019, %shl
   %ptr = inttoptr i32 %add to i64 addrspace(3)*
   store i64 123, i64 addrspace(3)* %ptr, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
-; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
-; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]]
+; GCN-DAG: v_xor_b32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]]
 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
 define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 {
   %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
   %neg = sub i32 0, %x.i
   %shl = shl i32 %neg, 2
   %add = add i32 1020, %shl
   %ptr = inttoptr i32 %add to i64 addrspace(3)*
   store i64 123, i64 addrspace(3)* %ptr, align 4
   ret void
 }
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
 attributes #2 = { nounwind convergent }

test/CodeGen/ARM/intrinsics-overflow.ll

define i32 @usub_overflow(i32 %a, i32 %b) #0 {
   %2 = zext i1 %1 to i32
   ret i32 %2
 
   ; CHECK-LABEL: usub_overflow:
 
   ; ARM: subs    r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
   ; ARM: mov     r[[R2:[0-9]+]], #0
   ; ARM: adc     r[[R0]], r[[R2]], #0
-  ; ARM: rsb     r[[R0]], r[[R0]], #1
+  ; ARM: eor     r[[R0]], r[[R0]], #1
 
   ; THUMBV6: movs    r[[R2:[0-9]+]], #0
   ; THUMBV6: subs    r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
   ; THUMBV6: adcs    r[[R2]], r[[R2]]
   ; THUMBV6: movs    r[[R0]], #1
-  ; THUMBV6: subs    r[[R0]], r[[R0]], r[[R2]]
+  ; THUMBV6: eors    r[[R0]], r[[R2]]
 
   ; THUMBV7: subs    r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
   ; THUMBV7: mov.w   r[[R2:[0-9]+]], #0
   ; THUMBV7: adc     r[[R0]], r[[R2]], #0
-  ; THUMBV7: rsb.w   r[[R0]], r[[R0]], #1
+  ; THUMBV7: eor     r[[R0]], r[[R0]], #1
 
   ; We should know that the overflow is just 1 bit,
   ; no need to clear any other bit
   ; CHECK-NOT: and
 }
 
 define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
   %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)

test/CodeGen/PowerPC/bool-math.ll

; CHECK-NEXT:    blr
   %z = zext i1 %c to i8
   %r = sub i8 47, %z
   ret i8 %r
 }
 
 define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
-; CHECK-NEXT:    subfic 3, 3, 27
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 27
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %z = zext i1 %c to i8
   %r = add i8 %z, 26
   ret i8 %r
 }
 
 define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_wider_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
-; CHECK-NEXT:    subfic 3, 3, 27
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 27
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %z = zext i1 %c to i32
   %r = add i32 %z, 26
   ret i32 %r
 }
 
 define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
-; CHECK-NEXT:    subfic 3, 3, 43
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 43
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %z = zext i1 %c to i8
   %r = add i8 %z, 42
   ret i8 %r
 }
 
 define i32 @low_bit_select_constants_bigger_false_same_size_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_same_size_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    subfic 3, 3, 43
+; CHECK-NEXT:    xori 3, 3, 43
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %r = select i1 %c, i32 42, i32 43
   ret i32 %r
 }
 
 define i64 @low_bit_select_constants_bigger_false_wider_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_wider_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    subfic 3, 3, 27
+; CHECK-NEXT:    xori 3, 3, 27
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %r = select i1 %c, i64 26, i64 27
   ret i64 %r
 }
 
 define i16 @low_bit_select_constants_bigger_false_narrower_result(i32 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_false_narrower_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
-; CHECK-NEXT:    clrlwi 3, 3, 31
-; CHECK-NEXT:    subfic 3, 3, 37
+; CHECK-NEXT:    xori 3, 3, 65535
+; CHECK-NEXT:    xoris 3, 3, 65535
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 37
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %r = select i1 %c, i16 36, i16 37
   ret i16 %r
 }
 
 define i8 @low_bit_select_constants_bigger_true_same_size_result(i8 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_same_size_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
-; CHECK-NEXT:    subfic 3, 3, -29
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 65507
+; CHECK-NEXT:    xoris 3, 3, 65535
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %r = select i1 %c, i8 227, i8 226
   ret i8 %r
 }
 
 define i32 @low_bit_select_constants_bigger_true_wider_result(i8 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_wider_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    subfic 3, 3, 227
+; CHECK-NEXT:    xori 3, 3, 227
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %r = select i1 %c, i32 227, i32 226
   ret i32 %r
 }
 
 define i8 @low_bit_select_constants_bigger_true_narrower_result(i16 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_narrower_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
-; CHECK-NEXT:    subfic 3, 3, 41
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xori 3, 3, 41
 ; CHECK-NEXT:    blr
   %a = and i16 %x, 1
   %c = icmp eq i16 %a, 0
   %r = select i1 %c, i8 41, i8 40
   ret i8 %r
 }
 

test/CodeGen/PowerPC/select_const.ll

; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 121, i8 23
   %bo = srem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_urem_constant:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
-; ALL-NEXT:    subfic 3, 3, 3
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    xori 3, 3, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @urem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: urem_constant_sel_constants:
; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_and_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_and_constant:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
-; ALL-NEXT:    subfic 3, 3, 5
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    xori 3, 3, 5
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
; NO_ISEL-NEXT:    blr
   ret i8 %bo
 }
 
 define i8 @shl_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: shl_constant_sel_constants:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
 ; ALL-NEXT:    li 4, 1
-; ALL-NEXT:    subfic 3, 3, 3
+; ALL-NEXT:    xori 3, 3, 3
 ; ALL-NEXT:    slw 3, 4, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 2, i8 3
   %bo = shl i8 1, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
; NO_ISEL-NEXT:    blr
   ret i8 %bo
 }
 
 define i8 @lshr_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: lshr_constant_sel_constants:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
 ; ALL-NEXT:    li 4, 64
-; ALL-NEXT:    subfic 3, 3, 3
+; ALL-NEXT:    xori 3, 3, 3
 ; ALL-NEXT:    srw 3, 4, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 2, i8 3
   %bo = lshr i8 64, %sel
   ret i8 %bo
 }
 
 
 define i8 @sel_constants_ashr_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_ashr_constant:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    neg 3, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = ashr i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @ashr_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: ashr_constant_sel_constants:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
 ; ALL-NEXT:    li 4, -128
-; ALL-NEXT:    subfic 3, 3, 3
+; ALL-NEXT:    xori 3, 3, 3
 ; ALL-NEXT:    sraw 3, 4, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 2, i8 3
   %bo = ashr i8 128, %sel
   ret i8 %bo
 }
 
 define double @sel_constants_fadd_constant(i1 %cond) {

test/CodeGen/SPARC/64bit.ll

entry:
   %arraydecay = getelementptr inbounds [32 x i8], [32 x i8]* %b, i64 0, i64 0
   call void @g(i8* %arraydecay) #2
   ret void
 }
 
 declare void @g(i8*)
 
 ; CHECK: expand_setcc
-; CHECK: cmp %i0, 1
-; CHECK: movl %xcc, 1,
+; CHECK: cmp %i0, 0
+; CHECK: movg %xcc, 1,
 define i32 @expand_setcc(i64 %a) {
   %cond = icmp sle i64 %a, 0
   %cast2 = zext i1 %cond to i32
   %RV = sub i32 1, %cast2
   ret i32 %RV
 }
 
 ; CHECK: spill_i64

test/CodeGen/X86/bool-math.ll

; CHECK-NEXT:    retq
   %r = sub i8 47, %z
   ret i8 %r
 }
 
 define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    movb $27, %al
-; CHECK-NEXT:    subb %dil, %al
+; CHECK-NEXT:    xorb $27, %dil
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %z = zext i1 %c to i8
   %r = add i8 %z, 26
   ret i8 %r
 }
 
 define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_wider_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andl $1, %edi
-; CHECK-NEXT:    movl $27, %eax
-; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    xorl $27, %edi
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %z = zext i1 %c to i32
   %r = add i32 %z, 26
   ret i32 %r
 }
 
 define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andl $1, %edi
-; CHECK-NEXT:    movb $43, %al
-; CHECK-NEXT:    subb %dil, %al
+; CHECK-NEXT:    xorb $43, %dil
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %z = zext i1 %c to i8
   %r = add i8 %z, 42
   ret i8 %r
 }
 
; CHECK-NEXT:    retq
   %r = select i1 %c, i16 36, i16 37
   ret i16 %r
 }
 
 define i8 @low_bit_select_constants_bigger_true_same_size_result(i8 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_same_size_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    movb $-29, %al
-; CHECK-NEXT:    subb %dil, %al
+; CHECK-NEXT:    xorb $-29, %dil
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %r = select i1 %c, i8 227, i8 226
   ret i8 %r
 }
 
 define i32 @low_bit_select_constants_bigger_true_wider_result(i8 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_wider_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andl $1, %edi
-; CHECK-NEXT:    movl $227, %eax
-; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    xorl $227, %edi
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i8 %x, 1
   %c = icmp eq i8 %a, 0
   %r = select i1 %c, i32 227, i32 226
   ret i32 %r
 }
 
 define i8 @low_bit_select_constants_bigger_true_narrower_result(i16 %x) {
 ; CHECK-LABEL: low_bit_select_constants_bigger_true_narrower_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andl $1, %edi
-; CHECK-NEXT:    movb $41, %al
-; CHECK-NEXT:    subb %dil, %al
+; CHECK-NEXT:    xorb $41, %dil
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %a = and i16 %x, 1
   %c = icmp eq i16 %a, 0
   %r = select i1 %c, i8 41, i8 40
   ret i8 %r
 }
 

test/CodeGen/X86/dagcombine-select.ll

; CHECK-NEXT:    retq
   %bo = shl i32 %sel, 8
   ret i32 %bo
 }
 
 define i32 @shl_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: shl_constant_sel_constants:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    movb $3, %cl
-; CHECK-NEXT:    subb %dil, %cl
+; CHECK-NEXT:    xorb $3, %dil
 ; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    movl %edi, %ecx
 ; CHECK-NEXT:    shll %cl, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = shl i32 1, %sel
   ret i32 %bo
 }
 
 define i32 @lshr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: lshr_constant_sel_constants:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    movb $3, %cl
-; CHECK-NEXT:    subb %dil, %cl
+; CHECK-NEXT:    xorb $3, %dil
 ; CHECK-NEXT:    movl $64, %eax
+; CHECK-NEXT:    movl %edi, %ecx
 ; CHECK-NEXT:    shrl %cl, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = lshr i32 64, %sel
   ret i32 %bo
 }
 
 define i32 @ashr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: ashr_constant_sel_constants:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    movb $3, %cl
-; CHECK-NEXT:    subb %dil, %cl
+; CHECK-NEXT:    xorb $3, %dil
 ; CHECK-NEXT:    movl $128, %eax
+; CHECK-NEXT:    movl %edi, %ecx
 ; CHECK-NEXT:    shrl %cl, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = ashr i32 128, %sel
   ret i32 %bo
 }
 
 define double @fsub_constant_sel_constants(i1 %cond) {