[PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores

[syzaara]

Summary

The X-form TLS load/store instructions added for optimizing the initial-exec sequence in https://reviews.llvm.org/rL327635 fail to assemble.
llvm-mc fails with the error: invalid operand for instruction.
This patch adds these instructions into a block with isAsmParserOnly, similar to how ADD8TLS_ is currently handled.

[hfinkel]

LGTM

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C, DISP_1C],
     (instregex "DCB(F|T|ST)(EP)?$"),
     (instregex "DCBZ(L)?(EP)?$"),
     (instregex "DCBTST(EP)?$"),
     (instregex "CP_COPY(8)?$"),
     (instregex "CP_PASTE(8)?$"),
     (instregex "ICBI(EP)?$"),
     (instregex "ICBT(LS)?$"),
     (instregex "LBARX(L)?$"),
-    (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?$"),
-    (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?$"),
+    (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"),
+    (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"),
     (instregex "LH(A|B)RX(L)?(8)?$"),
-    (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?$"),
+    (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
     (instregex "LWARX(L)?$"),
     (instregex "LWBRX(8)?$"),
-    (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?$"),
+    (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
     CP_ABORT,
     DARN,
     EnforceIEIO,
     ISYNC,
     MSGSYNC,
     TLBSYNC,
     SYNC,
     LMW,

 def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     (instregex "STF(S|D|IWX|SX|DX)$"),
     (instregex "STXS(D|DX|SPX|IWX|IBX|IHX|SP)(v)?$"),
     (instregex "STW(8)?$"),
     (instregex "(D|X)FSTORE(f32|f64)$"),
     (instregex "ST(W|H|D)BRX$"),
     (instregex "ST(B|H|D)(8)?$"),
-    (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?$"),
+    (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"),
     STIWX,
     SLBIEG,
     STMW,
     STSWI,
     TLBIE
 )>;
 
 // Vector Store Instruction

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
                           "subfze", "$rT, $rA", IIC_IntGeneral,
                           [(set i64:$rT, (sube 0, i64:$rA))]>;
 }
 } // isCodeGenOnly
 
 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
 // previous definition must be marked as CodeGen only to prevent decoding
 // conflicts.
-let isAsmParserOnly = 1 in
+let isAsmParserOnly = 1 in {
 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
                         "add $rT, $rA, $rB", IIC_IntSimple, []>;
 
+let mayLoad = 1 in {
+def LBZXTLS_ : XForm_1<31,  87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LWZXTLS_ : XForm_1<31,  23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>;
+def LDXTLS_  : XForm_1<31,  21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64;
+}
+
+let mayStore = 1 in {
+def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "stbx $rS, $rA, $rB", IIC_LdStStore, []>,
+                      PPC970_DGroup_Cracked;
+def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "sthx $rS, $rA, $rB", IIC_LdStStore, []>,
+                      PPC970_DGroup_Cracked;
+def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+                      "stwx $rS, $rA, $rB", IIC_LdStStore, []>,
+                      PPC970_DGroup_Cracked;
+def STDXTLS_  : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB),
+                       "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64,
+                       PPC970_DGroup_Cracked;
+                         PPC970_DGroup_Cracked;
+}
+}
+
 let isCommutable = 1 in {
 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                        "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
                        [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                        "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
                        [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
 } // isCommutable

llvm/test/MC/PowerPC/ppc64-tls-relocs-01.s

 # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
 # RUN: llvm-readobj -r | FileCheck %s
 
         .text
         addis 3, 13, t@tprel@ha
         addi 3, 3, t@tprel@l
-
+        addis 3, 2, t@got@tprel@ha
+        ld 3, t@got@tprel@l(3)
+        lwzx 4, 3, t@tls
+        lhzx 4, 3, t@tls
+        lbzx 4, 3, t@tls
+        ldx 4, 3, t@tls
+        stbx 4, 3, t@tls
+        sthx 4, 3, t@tls
+        stwx 4, 3, t@tls
+        stdx 4, 3, t@tls
         .type t,@object
         .section .tbss,"awT",@nobits
         .globl t
         .align 2
 t:
         .long 0
         .size t, 4
 
 # Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
 # against the thread-local symbol 't'.
 # CHECK:      Relocations [
 # CHECK:        Section ({{[0-9]+}}) .rela.text {
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:   }