[PowerPC][TLS] Add additional TLS X-Form loads/store instructions

[amyk]

Summary

This patch is a follow up to D43315, and adds the following new load/store
TLS specific instructions for integer and floating point scalar types:

LHAXTLS
LWAXTLS
LHAXTLS_32
LWAXTLS_32
LFSXTLS
LFDXTLS
STFSXTLS
STFDXTLS

These instructions can be used to optimized TLS sequences when D-Form
loads/stores follow an ADD_TLS instruction.

Duplicate versions of these instructions are also added within an isAsmParserOnly=1
block (similar to D47382) to allow llvm-mc to assemble these instructions.

[lei]

I don't know why adding new instructions would change where some older instructions are located in P10InstrResources.td, but since that is auto generated I will assume it is a separate issue that need to be looked into.
LGTM other then a nit.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

784–788

I feel like this should be indented thus instead....

[amyk]

Address nit comment regarding indentation in PPCISelDAGToDAG.cpp.

[amyk]

Update indentation/condition checks for sign extending loads in tryTLSXFormLoad()

[amyk]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

784–788

Discussed this and we agreed to check this to an if/else instead.

[kamaub]

This LGTM, thank you.

llvm/lib/Target/PowerPC/P10InstrResources.td

 
 // 6 Cycles Load operations, 1 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read],
       (instrs
     LBZ, LBZ8,
     LD,  LDtoc,  LDtocBA,  LDtocCPT,  LDtocJTI,  LDtocL, SPILLTOVSR_LD,
     LDBRX,
      DFLOADf32, DFLOADf64, LFD,
-    LFDX,  XFLOADf32, XFLOADf64,
     LFIWAX, LIWAX,
     LFIWZX, LIWZX,
     LHA, LHA8,
-    LHAX, LHAX8,
     LHBRX, LHBRX8,
     LHZ, LHZ8,
     LVEBX,
     LVEHX,
     LVEWX,
     LVX,
     LVXL,
     LWA, LWA_32,
-    LWAX, LWAX_32,
+    LWAX, LWAXTLS, LWAXTLS_, LWAXTLS_32, LWAX_32,
     LWBRX, LWBRX8,
     LWZ, LWZ8,  LWZtoc, LWZtocL,
     LXSD,
     LXSDX,
     LXSIBZX,
     LXSIHZX,
     LXSIWAX,
     LXSIWZX,

 // 6 Cycles Load operations, 2 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read],
       (instrs
     DCBT,
     DCBTST,
     ICBT,
     LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32,
     LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX,
+    LFDX, LFDXTLS, LFDXTLS_,  XFLOADf32, XFLOADf64,
+    LHAX, LHAX8, LHAXTLS, LHAXTLS_, LHAXTLS_32,
     LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32,
     LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32,
     LXVL,
     LXVLL
 )>;
 
 // 2-way crack instructions
 // 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 2 input operands
def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read],
     PLXVP, PLXVPpc
 )>;
 
 // 2-way crack instructions
 // 6 Cycles Load operations, and 4 Cycles ALU2 operations, 1 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C],
       (instrs
     LFS,
-    LFSX,
     LXSSP,
     LXSSPX
 )>;
 
+// 2-way crack instructions
+// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 2 input operands
+def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C],
+      (instrs
+    LFSX, LFSXTLS, LFSXTLS_
+)>;
+
 // 4-way crack instructions
 // 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 1 input operands
 def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY],
       (instrs
     LFSU,
     LFSUX
 )>;
 
def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read],
     STBUX, STBUX8,
     SPILLTOVSR_ST, STD,
     STDBRX,
     STDU,
     STDUX,
      DFSTOREf32, DFSTOREf64, STFD,
     STFDU,
     STFDUX,
-    STFDX,
     STFIWX, STIWX,
     STFS,
     STFSU,
     STFSUX,
-    STFSX,
     STH, STH8,
     STHBRX,
     STHU, STHU8,
     STHUX, STHUX8,
     STVEBX,
     STVEHX,
     STVEWX,
     STVX,

 )>;
 
 // 3 Cycles Store operations, 3 input operands
 def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read],
       (instrs
     CP_COPY, CP_COPY8,
     STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32,
     SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_,
+    STFDX, STFDXTLS, STFDXTLS_,
+    STFSX, STFSXTLS, STFSXTLS_,
     STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32,
     STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32,
     STXVL,
     STXVLL
 )>;
 
 // Single crack instructions
 // 3 Cycles Store operations, 0 input operands

llvm/lib/Target/PowerPC/P9InstrResources.td

 )>;
 
 // 4 Cycle Restricted load uses a single slice but the dispatch for the whole
 // superslice.
 def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_3SLOTS_1C],
       (instrs
     LFIWZX,
     LFDX,
+    (instregex "LFDXTLS?(_)?$"),
     LFD
 )>;
 
 // Cracked Load Instructions.
 // Load instructions that can be done in parallel.
 def : InstRW<[P9_LS_4C, P9_LS_4C, IP_AGEN_1C, IP_AGEN_1C,
               DISP_PAIR_1C],
       (instrs

 )>;
 
 // Cracked Load instruction.
 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
               DISP_1C, DISP_1C],
       (instrs
-    (instregex "LHA(X)?(8)?$"),
+    (instregex "LHA(X)?(TLS)?(8)?(_32)?(_)?$"),
     (instregex "CP_PASTE(8)?_rec$"),
-    (instregex "LWA(X)?(_32)?$"),
+    (instregex "LWA(X)?(TLS)?(_32)?(_)?$"),
     TCHECK
 )>;
 
 // Cracked Restricted Load instruction.
 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 // Full 6 dispatches are required as this is both cracked and restricted.
 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,

 // Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
 // cycles. The Load and ALU operations cannot be done at the same time and so
 // their latencies are added.
 // Full 6 dispatches are required as this is a restricted instruction.
 def : InstRW<[P9_LoadAndALU2Op_7C, IP_AGEN_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
     LFSX,
+    (instregex "LFSXTLS?(_)?$"),
     LFS
 )>;
 
 // Cracked Load instruction.
 // Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 // Full 4 dispatches are required as this is a cracked instruction.
 def : InstRW<[P9_LoadAndALU2Op_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
     LXVDSX,
     LXVW4X
 )>;
 
 // Single slice Restricted store operation. The restricted operation requires
 // all three dispatches for the superslice.
 def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C],
       (instrs
-    (instregex "STF(S|D|IWX|SX|DX)$"),
+    (instregex "STF(S|D|IWX|SX|DX|SXTLS|DXTLS|SXTLS_|DXTLS_)$"),
     (instregex "STXS(D|DX|SPX|IWX|IBX|IHX|SP)(v)?$"),
     (instregex "STW(8)?$"),
     (instregex "(D|X)FSTORE(f32|f64)$"),
     (instregex "ST(W|H|D)BRX$"),
     (instregex "ST(B|H|D)(8)?$"),
     (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"),
     STIWX,
     SLBIEG,

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

switch (MemVT.getSimpleVT().SimpleTy) {
     case MVT::i32: {
       Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
       break;
     }
     case MVT::i64: {
       Opcode = PPC::STDXTLS;
       break;
     }
+    case MVT::f32: {
+      Opcode = PPC::STFSXTLS;
+      break;
+    }
+    case MVT::f64: {
+      Opcode = PPC::STFDXTLS;
+      break;
+    }
   }
   SDValue Chain = ST->getChain();
   SDVTList VTs = ST->getVTList();
   SDValue Ops[] = {ST->getValue(), Base.getOperand(0), Base.getOperand(1),
                    Chain};
   SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
   transferMemOperands(ST, MN);
   ReplaceNode(ST, MN);
   return true;
 }
 
 bool PPCDAGToDAGISel::tryTLSXFormLoad(LoadSDNode *LD) {
   SDValue Base = LD->getBasePtr();
   if (Base.getOpcode() != PPCISD::ADD_TLS)
     return false;
   SDValue Offset = LD->getOffset();
   if (!Offset.isUndef())
     return false;
   if (Base.getOperand(1).getOpcode() == PPCISD::TLS_LOCAL_EXEC_MAT_ADDR)
     return false;
 
   SDLoc dl(LD);
   EVT MemVT = LD->getMemoryVT();
   EVT RegVT = LD->getValueType(0);
+  bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
   unsigned Opcode;
   switch (MemVT.getSimpleVT().SimpleTy) {
     default:
       return false;
     case MVT::i8: {
       Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
       break;
     }
     case MVT::i16: {
-      Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
+      if (RegVT == MVT::i32)
+        Opcode = isSExt ? PPC::LHAXTLS_32 : PPC::LHZXTLS_32;
+      else
+        Opcode = isSExt ? PPC::LHAXTLS : PPC::LHZXTLS;
       break;
     }
     case MVT::i32: {
-      Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
+      if (RegVT == MVT::i32)
+        Opcode = isSExt ? PPC::LWAXTLS_32 : PPC::LWZXTLS_32;
+      else
+        Opcode = isSExt ? PPC::LWAXTLS : PPC::LWZXTLS;
       break;
     }
     case MVT::i64: {
       Opcode = PPC::LDXTLS;
       break;
     }
+    case MVT::f32: {
+      Opcode = PPC::LFSXTLS;
+      break;
+    }
+    case MVT::f64: {
+      Opcode = PPC::LFDXTLS;
+      break;
+    }
   }
   SDValue Chain = LD->getChain();
   SDVTList VTs = LD->getVTList();
   SDValue Ops[] = {Base.getOperand(0), Base.getOperand(1), Chain};
   SDNode *MN = CurDAG->getMachineNode(Opcode, dl, VTs, Ops);
   transferMemOperands(LD, MN);
   ReplaceNode(LD, MN);
   return true;

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def ADD8TLS  : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB),
                         "add $RT, $RA, $RB", IIC_IntSimple,
                         [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>;
 let mayLoad = 1 in {
 def LBZXTLS : XForm_1<31,  87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                      "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LWZXTLS : XForm_1<31,  23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                      "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LDXTLS  : XForm_1<31,  21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
 def LBZXTLS_32 : XForm_1<31,  87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                          "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                          "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                         "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LWZXTLS_32 : XForm_1<31,  23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                          "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                         "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
 
 }
+let mayLoad = 1, Predicates = [HasFPU] in {
+def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;
+def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;
+}
 
 let mayStore = 1 in {
 def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                       "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
                       PPC970_DGroup_Cracked;
 def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                       "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
                       PPC970_DGroup_Cracked;

 def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                          "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
                          PPC970_DGroup_Cracked;
 def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                          "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
                          PPC970_DGroup_Cracked;
 
 }
+let mayStore = 1, Predicates = [HasFPU] in {
+def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,
+                       PPC970_DGroup_Cracked;
+def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,
+                       PPC970_DGroup_Cracked;
+}
 
 let isCommutable = 1 in
 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                         "addc", "$RT, $RA, $RB", IIC_IntGeneral,
                         [(set i64:$RT, (addc i64:$RA, i64:$RB))]>,
                         PPC970_DGroup_Cracked;
 
 let Defs = [CARRY] in

 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB),
                         "add $RT, $RA, $RB", IIC_IntSimple, []>;
 
 let mayLoad = 1 in {
 def LBZXTLS_ : XForm_1<31,  87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LWZXTLS_ : XForm_1<31,  23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
+def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                       "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
 def LDXTLS_  : XForm_1<31,  21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
                       "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
 }
 
+let mayLoad = 1, Predicates = [HasFPU] in {
+def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                        "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;
+def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
+                        "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;
+}
+
 let mayStore = 1 in {
 def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                       "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
                       PPC970_DGroup_Cracked;
 def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                       "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
                       PPC970_DGroup_Cracked;
 def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                       "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
                       PPC970_DGroup_Cracked;
 def STDXTLS_  : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
                        "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,
                        PPC970_DGroup_Cracked;
 }
+
+let mayStore = 1, Predicates = [HasFPU] in {
+def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
+                        "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,
+                        PPC970_DGroup_Cracked;
+def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
+                        "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,
+                        PPC970_DGroup_Cracked;
+}
 }
 
 let isCommutable = 1 in {
 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                        "mulhd", "$RT, $RA, $RB", IIC_IntMulHW,
                        [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>;
 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
                        "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU,

llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    mffprd 3, 1
 ; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble1:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    addi 4, 1, -16
+; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-P10-NEXT:    lxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
   ret <2 x double> %vecins
 }

 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
 ; CHECK-64-P10-NEXT:    rlwinm 4, 5, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble2:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    lfd 0, 0(3)
-; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-P10-NEXT:    addi 6, 1, -32
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stxv 34, -32(1)
 ; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-P10-NEXT:    lxv 0, -32(1)
 ; CHECK-32-P10-NEXT:    plfd 1, 1(3), 0
 ; CHECK-32-P10-NEXT:    addi 3, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 0, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 3, 5

 ; CHECK-64-P10-NEXT:    ldx 3, 3, 4
 ; CHECK-64-P10-NEXT:    rlwinm 4, 5, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble3:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    plfd 0, 65536(3), 0
-; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-P10-NEXT:    addi 6, 1, -32
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stxv 34, -32(1)
 ; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-P10-NEXT:    lxv 0, -32(1)
 ; CHECK-32-P10-NEXT:    lfd 1, 0(3)
 ; CHECK-32-P10-NEXT:    addi 3, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 0, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 3, 5

llvm/test/CodeGen/PowerPC/tls-pie-xform.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
 
 @var_char = external thread_local local_unnamed_addr global i8, align 1
 @var_short = external thread_local local_unnamed_addr global i16, align 2
 @var_int = external thread_local local_unnamed_addr global i32, align 4
 @var_long_long = external thread_local local_unnamed_addr global i64, align 8
+@var_float = external thread_local local_unnamed_addr global float, align 4
+@var_double = external thread_local local_unnamed_addr global double, align 8
 
 define dso_local zeroext i8 @test_char_one() {
 ; CHECK-LABEL: test_char_one:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, var_char@got@tprel@ha
 ; CHECK-NEXT:    ld 3, var_char@got@tprel@l(3)
 ; CHECK-NEXT:    lbzx 3, 3, var_char@tls
 ; CHECK-NEXT:    blr
entry:
   ret i8 %add
 }
 
 define dso_local signext i16 @test_short_one() {
 ; CHECK-LABEL: test_short_one:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, var_short@got@tprel@ha
 ; CHECK-NEXT:    ld 3, var_short@got@tprel@l(3)
+; CHECK-NEXT:    lhax 3, 3, var_short@tls
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i16, ptr @var_short, align 2, !tbaa !7
+  ret i16 %0
+}
+
+define dso_local zeroext i16 @test_short_one_zeroext() {
+; CHECK-LABEL: test_short_one_zeroext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_short@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_short@got@tprel@l(3)
 ; CHECK-NEXT:    lhzx 3, 3, var_short@tls
 ; CHECK-NEXT:    blr
 entry:
   %0 = load i16, ptr @var_short, align 2, !tbaa !7
   ret i16 %0
 }
 
 define dso_local void @test_short_two(i32 signext %a) {
entry:
   ret i16 %add
 }
 
 define dso_local signext i32 @test_int_one() {
 ; CHECK-LABEL: test_int_one:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, var_int@got@tprel@ha
 ; CHECK-NEXT:    ld 3, var_int@got@tprel@l(3)
+; CHECK-NEXT:    lwax 3, 3, var_int@tls
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i32, ptr @var_int, align 4, !tbaa !9
+  ret i32 %0
+}
+
+define dso_local zeroext i32 @test_int_one_zeroext() {
+; CHECK-LABEL: test_int_one_zeroext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_int@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_int@got@tprel@l(3)
 ; CHECK-NEXT:    lwzx 3, 3, var_int@tls
 ; CHECK-NEXT:    blr
 entry:
   %0 = load i32, ptr @var_int, align 4, !tbaa !9
   ret i32 %0
 }
 
 define dso_local void @test_int_two(i32 signext %a) {

 ; CHECK-NEXT:    blr
 entry:
   %0 = load i64, ptr @var_long_long, align 8, !tbaa !11
   %add = add nsw i64 %0, %a
   store i64 %add, ptr @var_long_long, align 8, !tbaa !11
   ret i64 %add
 }
 
+define float @test_float_one() {
+; CHECK-LABEL: test_float_one:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_float@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_float@got@tprel@l(3)
+; CHECK-NEXT:    lfsx 1, 3, var_float@tls
+; CHECK-NEXT:    blr
+entry:
+  %0 = load float, ptr @var_float, align 4
+  ret float %0
+}
+
+define void @test_float_two(float %a) {
+; CHECK-LABEL: test_float_two:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_float@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_float@got@tprel@l(3)
+; CHECK-NEXT:    stfsx 1, 3, var_float@tls
+; CHECK-NEXT:    blr
+entry:
+  store float %a, ptr @var_float, align 4
+  ret void
+}
+
+define double @test_double_one() {
+; CHECK-LABEL: test_double_one:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_double@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_double@got@tprel@l(3)
+; CHECK-NEXT:    lfdx 1, 3, var_double@tls
+; CHECK-NEXT:    blr
+entry:
+  %0 = load double, ptr @var_double, align 8
+  ret double %0
+}
+
+define void @test_double_two(double %a) {
+; CHECK-LABEL: test_double_two:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, var_double@got@tprel@ha
+; CHECK-NEXT:    ld 3, var_double@got@tprel@l(3)
+; CHECK-NEXT:    stfdx 1, 3, var_double@tls
+; CHECK-NEXT:    blr
+entry:
+  store double %a, ptr @var_double, align 8
+  ret void
+}
+
 !llvm.module.flags = !{!0, !1, !2}
 
 !0 = !{i32 1, !"wchar_size", i32 4}
 !1 = !{i32 7, !"PIC Level", i32 1}
 !2 = !{i32 7, !"PIE Level", i32 1}
 !4 = !{!5, !5, i64 0}
 !5 = !{!"omnipotent char", !6, i64 0}
 !6 = !{!"Simple C/C++ TBAA"}
 !7 = !{!8, !8, i64 0}
 !8 = !{!"short", !5, i64 0}
 !9 = !{!10, !10, i64 0}
 !10 = !{!"int", !5, i64 0}
 !11 = !{!12, !12, i64 0}
 !12 = !{!"long long", !5, i64 0}

llvm/test/MC/PowerPC/ppc64-tls-relocs-01.s

 # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
 # RUN: llvm-readobj -r - | FileCheck %s
 
         .text
         addis 3, 13, t@tprel@ha
         addi 3, 3, t@tprel@l
         addis 3, 2, t@got@tprel@ha
         ld 3, t@got@tprel@l(3)
         lwzx 4, 3, t@tls
+        lwax 4, 3, t@tls
         lhzx 4, 3, t@tls
+        lhax 4, 3, t@tls
         lbzx 4, 3, t@tls
         ldx 4, 3, t@tls
         stbx 4, 3, t@tls
         sthx 4, 3, t@tls
         stwx 4, 3, t@tls
         stdx 4, 3, t@tls
         .type t,@object
         .section .tbss,"awT",@nobits

 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
 # CHECK-NEXT:   }

llvm/test/MC/PowerPC/ppc64-tls-relocs-double-01.s

+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s
+
+        .text
+        addis 3, 13, myDouble@tprel@ha
+        addi 3, 3, myDouble@tprel@l
+        addis 3, 2, myDouble@got@tprel@ha
+        ld 3, myDouble@got@tprel@l(3)
+        lfdx 4, 3, myDouble@tls
+        stfdx 4, 3, myDouble@tls
+        .type myDouble,@object
+        .section .tbss,"awT",@nobits
+        .globl myDouble
+        .align 2
+
+myDouble:
+  .quad 0
+  .size myDouble, 8
+
+# Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
+# against the thread-local symbol 'myDouble'.
+# CHECK:      Relocations [
+# CHECK:        Section ({{[0-9]+}}) .rela.text {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA myDouble
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO myDouble
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA myDouble 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS myDouble 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS myDouble 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS myDouble 0x0
+# CHECK-NEXT:   }

llvm/test/MC/PowerPC/ppc64-tls-relocs-float-01.s

+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s
+
+        .text
+        addis 3, 13, myFloat@tprel@ha
+        addi 3, 3, myFloat@tprel@l
+        addis 3, 2, myFloat@got@tprel@ha
+        ld 3, myFloat@got@tprel@l(3)
+        lfsx 4, 3, myFloat@tls
+        stfsx 4, 3, myFloat@tls
+        .type myFloat,@object
+        .section .tbss,"awT",@nobits
+        .globl myFloat
+        .align 2
+
+myFloat:
+  .long 0
+  .size myFloat, 4
+
+# Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
+# against the thread-local symbol 'myFloat'.
+# CHECK:      Relocations [
+# CHECK:        Section ({{[0-9]+}}) .rela.text {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA myFloat
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO myFloat
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA myFloat 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS myFloat 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS myFloat 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TLS myFloat 0x0
+# CHECK-NEXT:   }