Teach TargetMachines about -Oz and -Os

[paquette]

Summary

This is the first in a series of patches to turn the MachineOutliner on by default under -Oz for AArch64.

Currently, TargetMachines only know about -O0...-O3. They don't know anything about -Oz or -Os, and size optimization is managed solely by function attributes.

The outliner should be added only at -Oz under only AArch64 by default. With the way things currently work, that would mean the outliner, by default, would have to walk over every function in the module all of the time, and see if any minsize functions exist. This would incur a completely unnecessary compile-time overhead. Thus, this patch teaches Target Machines about size optimization levels.

[paquette]

Updated diff to use -U999999 for context

[paquette]

We decided it'd be better to just use function attributes for the outliner, so I'm abandoning this.

include/llvm-c/TargetMachine.h

 typedef enum {
     LLVMCodeGenLevelNone,
     LLVMCodeGenLevelLess,
     LLVMCodeGenLevelDefault,
     LLVMCodeGenLevelAggressive
 } LLVMCodeGenOptLevel;
 
 typedef enum {
+    LLVMCodeGenSizeLevelNone,
+    LLVMCodeGenSizeLevelOptSize,
+    LLVMCodeGenSizeLevelMinSize
+} LLVMCodeGenSizeOptLevel;
+
+typedef enum {
     LLVMRelocDefault,
     LLVMRelocStatic,
     LLVMRelocPIC,
     LLVMRelocDynamicNoPic
 } LLVMRelocMode;
 
 typedef enum {
     LLVMCodeModelDefault,

 /** Returns if the target has a TargetMachine associated */
 LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T);
 
 /** Returns if the target as an ASM backend (required for emitting output) */
 LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T);
 
 /*===-- Target Machine ----------------------------------------------------===*/
 /** Creates a new llvm::TargetMachine. See llvm::Target::createTargetMachine */
-LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
-  const char *Triple, const char *CPU, const char *Features,
-  LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel);
+LLVMTargetMachineRef
+LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU,
+                        const char *Features, LLVMCodeGenOptLevel Level,
+                        LLVMCodeGenSizeOptLevel SizeLevel, LLVMRelocMode Reloc,
+                        LLVMCodeModel CodeModel);
 
 /** Dispose the LLVMTargetMachineRef instance generated by
   LLVMCreateTargetMachine. */
 void LLVMDisposeTargetMachine(LLVMTargetMachineRef T);
 
 /** Returns the Target used in a TargetMachine */
 LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T);
 

include/llvm/CodeGen/TargetPassConfig.h

public:
   template<typename TMC> TMC &getTM() const {
     return *static_cast<TMC*>(TM);
   }
 
   //
   void setInitialized() { Initialized = true; }
 
   CodeGenOpt::Level getOptLevel() const;
+  CodeGenSizeOpt::Level getSizeOptLevel() const;
 
   /// Describe the status of the codegen
   /// pipeline set by this target pass config.
   /// Having a limited codegen pipeline means that options
   /// have been used to restrict what codegen is doing.
   /// In particular, that means that codegen won't emit
   /// assembly code.
   bool hasLimitedCodeGenPipeline() const;

include/llvm/Support/CodeGen.h

namespace CodeGenOpt {
     enum Level {
       None,        // -O0
       Less,        // -O1
       Default,     // -O2, -Os
       Aggressive   // -O3
     };
   }
 
+  // Code generation size optimization level.
+  namespace CodeGenSizeOpt {
+    enum Level {
+      None,      // -O0...-O3
+      OptSize,   // -Os
+      MinSize    // -Oz
+    };
+  }
+
 }  // end llvm namespace
 
 #endif

include/llvm/Support/TargetRegistry.h

public:
   using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
                                            const Triple &TT);
   using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
   using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
   using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
   using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
                                                        StringRef CPU,
                                                        StringRef Features);
-  using TargetMachineCtorTy = TargetMachine
-      *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
-           const TargetOptions &Options, Optional<Reloc::Model> RM,
-           Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
+  using TargetMachineCtorTy =
+      TargetMachine *(*)(const Target &T, const Triple &TT, StringRef CPU,
+                         StringRef Features, const TargetOptions &Options,
+                         Optional<Reloc::Model> RM,
+                         Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+                         CodeGenSizeOpt::Level SL, bool JIT);
   // If it weren't for layering issues (this header is in llvm/Support, but
   // depends on MC?) this should take the Streamer by value rather than rvalue
   // reference.
   using AsmPrinterCtorTy = AsmPrinter *(*)(
       TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
   using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
                                                const MCSubtargetInfo &STI,
                                                const MCRegisterInfo &MRI,
public:
 
   /// createTargetMachine - Create a target specific machine implementation
   /// for the specified \p Triple.
   ///
   /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
-  TargetMachine *createTargetMachine(StringRef TT, StringRef CPU,
-                                     StringRef Features,
-                                     const TargetOptions &Options,
-                                     Optional<Reloc::Model> RM,
-                                     Optional<CodeModel::Model> CM = None,
-                                     CodeGenOpt::Level OL = CodeGenOpt::Default,
-                                     bool JIT = false) const {
+  TargetMachine *
+  createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
+                      const TargetOptions &Options, Optional<Reloc::Model> RM,
+                      CodeGenSizeOpt::Level SL = CodeGenSizeOpt::None,
     if (!TargetMachineCtorFn)
       return nullptr;
     return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
-                               CM, OL, JIT);
+                               CM, OL, SL, JIT);
   }
 
   /// createMCAsmBackend - Create a target specific assembly parser.
   MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
                                    const MCRegisterInfo &MRI,
                                    const MCTargetOptions &Options) const {
     if (!MCAsmBackendCtorFn)
       return nullptr;
template <class TargetMachineImpl> struct RegisterTargetMachine {
   RegisterTargetMachine(Target &T) {
     TargetRegistry::RegisterTargetMachine(T, &Allocator);
   }
 
 private:
   static TargetMachine *
   Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
             const TargetOptions &Options, Optional<Reloc::Model> RM,
-            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
-    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
+            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+            CodeGenSizeOpt::Level SL, bool JIT) {
+    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT);
   }
 };
 
 /// RegisterMCAsmBackend - Helper template for registering a target specific
 /// assembler backend. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCAsmBackend() {
 ///   extern Target TheFooTarget;

include/llvm/Target/TargetMachine.h

protected: // Can only create subclasses.
   /// instance is created with.
   Triple TargetTriple;
   std::string TargetCPU;
   std::string TargetFS;
 
   Reloc::Model RM = Reloc::Static;
   CodeModel::Model CMModel = CodeModel::Small;
   CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
+  CodeGenSizeOpt::Level SizeOptLevel = CodeGenSizeOpt::None;
 
   /// Contains target specific asm information.
   const MCAsmInfo *AsmInfo;
 
   const MCRegisterInfo *MRI;
   const MCInstrInfo *MII;
   const MCSubtargetInfo *STI;
 
public:
   bool useEmulatedTLS() const;
 
   /// Returns the TLS model which should be used for the given global variable.
   TLSModel::Model getTLSModel(const GlobalValue *GV) const;
 
   /// Returns the optimization level: None, Less, Default, or Aggressive.
   CodeGenOpt::Level getOptLevel() const;
 
+  /// Returns the size optimization level: None, OptSize, or MinSize.
+  /// Default is None.
+  CodeGenSizeOpt::Level getSizeOptLevel() const;
+
   /// \brief Overrides the optimization level.
   void setOptLevel(CodeGenOpt::Level Level);
 
+  /// Overrides the size optimization level.
+  void setSizeOptLevel(CodeGenSizeOpt::Level Level);
+
   void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
   bool getO0WantsFastISel() { return O0WantsFastISel; }
   void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
   void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
 
   bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
 
   bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }

 /// This class describes a target machine that is implemented with the LLVM
 /// target-independent code generator.
 ///
 class LLVMTargetMachine : public TargetMachine {
 protected: // Can only create subclasses.
   LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
                     const Triple &TargetTriple, StringRef CPU, StringRef FS,
                     const TargetOptions &Options, Reloc::Model RM,
-                    CodeModel::Model CM, CodeGenOpt::Level OL);
+                    CodeModel::Model CM, CodeGenOpt::Level OL,
+                    CodeGenSizeOpt::Level SL);
 
   void initAsmInfo();
 
 public:
   /// \brief Get a TargetTransformInfo implementation for the target.
   ///
   /// The TTI returned uses the common code generator to answer queries about
   /// the IR.

lib/CodeGen/LLVMTargetMachine.cpp

void LLVMTargetMachine::initAsmInfo() {
   AsmInfo = TmpAsmInfo;
 }
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
                                      StringRef DataLayoutString,
                                      const Triple &TT, StringRef CPU,
                                      StringRef FS, const TargetOptions &Options,
                                      Reloc::Model RM, CodeModel::Model CM,
-                                     CodeGenOpt::Level OL)
+                                     CodeGenOpt::Level OL,
+                                     CodeGenSizeOpt::Level SL)
     : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
   this->RM = RM;
   this->CMModel = CM;
   this->OptLevel = OL;
+  this->SizeOptLevel = SL;
 
   if (EnableTrapUnreachable)
     this->Options.TrapUnreachable = true;
 }
 
 TargetTransformInfo
 LLVMTargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(BasicTTIImpl(this, F));

lib/CodeGen/TargetPassConfig.cpp

TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
 
   setStartStopPasses();
 }
 
 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
   return TM->getOptLevel();
 }
 
+CodeGenSizeOpt::Level TargetPassConfig::getSizeOptLevel() const {
+  return TM->getSizeOptLevel();
+}
+
 /// Insert InsertedPassID pass after TargetPassID.
 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
                                   IdentifyingPassPtr InsertedPassID,
                                   bool VerifyAfter, bool PrintAfter) {
   assert(((!InsertedPassID.isInstance() &&
            TargetPassID != InsertedPassID.getID()) ||
           (InsertedPassID.isInstance() &&
            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&

lib/ExecutionEngine/TargetSelect.cpp

TargetMachine *EngineBuilder::selectTarget(const Triple &TargetTriple,
   // FIXME: non-iOS ARM FastISel is broken with MCJIT.
   if (TheTriple.getArch() == Triple::arm &&
       !TheTriple.isiOS() &&
       OptLevel == CodeGenOpt::None) {
     OptLevel = CodeGenOpt::Less;
   }
 
   // Allocate a target...
-  TargetMachine *Target =
-      TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr,
-                                     Options, RelocModel, CMModel, OptLevel,
-             /*JIT*/ true);
+  TargetMachine *Target = TheTarget->createTargetMachine(
+      TheTriple.getTriple(), MCPU, FeaturesStr, Options, RelocModel, CMModel,
+      OptLevel, CodeGenSizeOpt::None, /*JIT*/ true);
   Target->Options.EmulatedTLS = EmulatedTLS;
   Target->Options.ExplicitEmulatedTLS = true;
 
   assert(Target && "Could not allocate target machine!");
   return Target;
 }

lib/Target/AArch64/AArch64TargetMachine.h

 protected:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT, bool IsLittleEndian);
 
   ~AArch64TargetMachine() override;
   const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
   // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
   // subtargets are per-function entities based on the target-specific
   // attributes of each function.
   const AArch64Subtarget *getSubtargetImpl() const = delete;
 

 // AArch64 little endian target machine.
 //
 class AArch64leTargetMachine : public AArch64TargetMachine {
   virtual void anchor();
 public:
   AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
                          Optional<Reloc::Model> RM,
-                         Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+                         Optional<CodeModel::Model> CM,
+                         CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
                          bool JIT);
 };
 
 // AArch64 big endian target machine.
 //
 class AArch64beTargetMachine : public AArch64TargetMachine {
   virtual void anchor();
 public:
   AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
                          Optional<Reloc::Model> RM,
-                         Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+                         Optional<CodeModel::Model> CM,
+                         CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
                          bool JIT);
 };
 
 extern cl::opt<bool> WatchBitcodeCompatibility;
 
 } // end namespace llvm
 
 #endif

lib/Target/AArch64/AArch64TargetMachine.cpp

 
 /// Create an AArch64 architecture model.
 ///
 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT,
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT,
                                            bool LittleEndian)
     : LLVMTargetMachine(T,
                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
-                        getEffectiveCodeModel(TT, CM, JIT), OL),
+                        getEffectiveCodeModel(TT, CM, JIT), OL, SL),
       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
   initAsmInfo();
 
   if (TT.isOSBinFormatMachO())
     this->Options.TrapUnreachable = true;
 
   // Enable GlobalISel at or below EnableGlobalISelAt0.
   if (getOptLevel() <= EnableGlobalISelAtO)
AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
 void AArch64leTargetMachine::anchor() { }
 
 AArch64leTargetMachine::AArch64leTargetMachine(
     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Optional<Reloc::Model> RM,
-    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
-    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
+    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+    CodeGenSizeOpt::Level SL, bool JIT)
+    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true)
+    {}
 
 void AArch64beTargetMachine::anchor() { }
 
 AArch64beTargetMachine::AArch64beTargetMachine(
     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Optional<Reloc::Model> RM,
-    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
-    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
+    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+    CodeGenSizeOpt::Level SL, bool JIT)
+    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false)
+    {}
 
 namespace {
 
 /// AArch64 Code Generator Pass Configuration Options.
 class AArch64PassConfig : public TargetPassConfig {
 public:
   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {

lib/Target/AMDGPU/AMDGPUTargetMachine.h

 class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, TargetOptions Options,
                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                    CodeGenOpt::Level OL, bool JIT);
+                    CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   const R600Subtarget *getSubtargetImpl(const Function &) const override;
 
   bool isMachineVerifierClean() const override {
     return false;
   }
 };
 
 //===----------------------------------------------------------------------===//
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
 class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<SISubtarget>> SubtargetMap;
 
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, TargetOptions Options,
                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   const SISubtarget *getSubtargetImpl(const Function &) const override;
 
   bool useIPRA() const override {
     return true;
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      TargetOptions Options,
                                      Optional<Reloc::Model> RM,
                                      Optional<CodeModel::Model> CM,
-                                     CodeGenOpt::Level OL, bool JIT)
-    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
+                                     CodeGenOpt::Level OL,
+                                     CodeGenSizeOpt::Level SL, bool JIT)
+    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL) {
   setRequiresStructuredCFG(true);
 }
 
 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
   const Function &F) const {
   StringRef GPU = getGPUName(F);
   StringRef FS = getFeatureString(F);
 

 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    TargetOptions Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
-    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
+    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, SL, OL, SL) {}
 
 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
   StringRef GPU = getGPUName(F);
   StringRef FS = getFeatureString(F);
 
   SmallString<128> SubtargetKey(GPU);
   SubtargetKey.append(FS);
 

lib/Target/ARC/ARCTargetMachine.h

 class ARCTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   ARCSubtarget Subtarget;
 
 public:
   ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~ARCTargetMachine() override;
 
   const ARCSubtarget *getSubtargetImpl() const { return &Subtarget; }
   const ARCSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 
   // Pass Pipeline Configuration

lib/Target/ARC/ARCTargetMachine.cpp

 }
 
 /// ARCTargetMachine ctor - Create an ILP32 architecture model
 ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T,
                         "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
                         "f32:32:32-i64:32-f64:32-a:0:32-n32",
                         TT, CPU, FS, Options, getRelocModel(RM),
                         getEffectiveCodeModel(CM), OL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();

lib/Target/ARM/ARMTargetMachine.h

protected:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool isLittle);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool isLittle);
   ~ARMBaseTargetMachine() override;
 
   const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
   // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
   // subtargets are per-function entities based on the target-specific
   // attributes of each function.
   const ARMSubtarget *getSubtargetImpl() const = delete;
   bool isLittleEndian() const { return isLittle; }

 
 /// ARM/Thumb little endian target machine.
 ///
 class ARMLETargetMachine : public ARMBaseTargetMachine {
 public:
   ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 };
 
 /// ARM/Thumb big endian target machine.
 ///
 class ARMBETargetMachine : public ARMBaseTargetMachine {
 public:
   ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H

lib/Target/ARM/ARMTargetMachine.cpp

 
 /// Create an ARM architecture model.
 ///
 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool isLittle)
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL,
+                                           bool isLittle)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
-                        getEffectiveCodeModel(CM), OL),
+                        getEffectiveCodeModel(CM), OL, SL),
       TargetABI(computeTargetABI(TT, CPU, Options)),
       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
 
   // Default to triple-appropriate float ABI
   if (Options.FloatABIType == FloatABI::Default) {
     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
         TargetTriple.getEnvironment() == Triple::EABIHF ||
ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(ARMTTIImpl(this, F));
 }
 
 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool JIT)
-    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool JIT)
+    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, true) {}
 
 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool JIT)
-    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool JIT)
+    : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, false) {}
 
 namespace {
 
 /// ARM Code Generator Pass Configuration Options.
 class ARMPassConfig : public TargetPassConfig {
 public:
   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {

lib/Target/AVR/AVRTargetMachine.h

 
 /// A generic AVR implementation.
 class AVRTargetMachine : public LLVMTargetMachine {
 public:
   AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    Optional<Reloc::Model> RM,
                    Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   const AVRSubtarget *getSubtargetImpl() const;
   const AVRSubtarget *getSubtargetImpl(const Function &) const override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return this->TLOF.get();
   }
 

lib/Target/AVR/AVRTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
   return CodeModel::Small;
 }
 
 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
                         getEffectiveRelocModel(RM), getEffectiveCodeModel(CM),
-                        OL),
+                        OL, SL),
       SubTarget(TT, getCPU(CPU), FS, *this) {
   this->TLOF = make_unique<AVRTargetObjectFile>();
   initAsmInfo();
 }
 
 namespace {
 /// AVR Code Generator Pass Configuration Options.
 class AVRPassConfig : public TargetPassConfig {

lib/Target/BPF/BPFTargetMachine.h

 class BPFTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   BPFSubtarget Subtarget;
 
 public:
   BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
   const BPFSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 };
 }
 
 #endif

lib/Target/BPF/BPFTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
   return CodeModel::Small;
 }
 
 BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM), getEffectiveCodeModel(CM),
-                        OL),
+                        OL, SL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 
   BPFMCAsmInfo *MAI = static_cast<BPFMCAsmInfo *>(const_cast<MCAsmInfo *>(AsmInfo));
   MAI->setDwarfUsesRelocationsAcrossSections(!Subtarget.getUseDwarfRIS());
 }
 namespace {

lib/Target/Hexagon/HexagonTargetMachine.h

 class HexagonTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~HexagonTargetMachine() override;
   const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
 
   static unsigned getModuleMatchQuality(const Module &M);
 
   void adjustPassManager(PassManagerBuilder &PMB) override;
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetTransformInfo getTargetTransformInfo(const Function &F) override;

lib/Target/Hexagon/HexagonTargetMachine.cpp

extern "C" void LLVMInitializeHexagonTarget() {
   initializeHexagonVExtractPass(PR);
 }
 
 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
     // Specify the vector alignment explicitly. For v512x1, the calculated
     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
     // the required minimum of 64 bytes.
     : LLVMTargetMachine(
           T,
           "e-m:e-p:32:32:32-a:0-n16:32-"
           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
-          getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
+          getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL),
+          (HexagonNoOpt ? CodeGenSizeOpt::None : SL)),
       TLOF(make_unique<HexagonTargetObjectFile>()) {
   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
   initAsmInfo();
 }
 
 const HexagonSubtarget *
 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
   AttributeList FnAttrs = F.getAttributes();

lib/Target/MSP430/MSP430TargetMachine.h

 class MSP430TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   MSP430Subtarget        Subtarget;
 
 public:
   MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                       StringRef FS, const TargetOptions &Options,
                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                      CodeGenOpt::Level OL, bool JIT);
+                      CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~MSP430TargetMachine() override;
 
   const MSP430Subtarget *getSubtargetImpl(const Function &F) const override {
     return &Subtarget;
   }
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 }; // MSP430TargetMachine.
 
 } // end namespace llvm
 
 #endif

lib/Target/MSP430/MSP430TargetMachine.cpp

static std::string computeDataLayout(const Triple &TT, StringRef CPU,
   return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
 }
 
 MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
                                          StringRef CPU, StringRef FS,
                                          const TargetOptions &Options,
                                          Optional<Reloc::Model> RM,
                                          Optional<CodeModel::Model> CM,
-                                         CodeGenOpt::Level OL, bool JIT)
+                                         CodeGenOpt::Level OL,
+                                         CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
                         Options, getEffectiveRelocModel(RM),
-                        getEffectiveCodeModel(CM), OL),
+                        getEffectiveCodeModel(CM), OL, SL),
       TLOF(make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 MSP430TargetMachine::~MSP430TargetMachine() {}
 
 namespace {

lib/Target/Mips/MipsTargetMachine.h

class MipsTargetMachine : public LLVMTargetMachine {
   MipsSubtarget Mips16Subtarget;
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                    CodeGenOpt::Level OL, bool JIT, bool isLittle);
+                    CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT, bool isLittle);
   ~MipsTargetMachine() override;
 
   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
 
   const MipsSubtarget *getSubtargetImpl() const {
     if (Subtarget)
       return Subtarget;
     return &DefaultSubtarget;

 ///
 class MipsebTargetMachine : public MipsTargetMachine {
   virtual void anchor();
 
 public:
   MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                       StringRef FS, const TargetOptions &Options,
                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                      CodeGenOpt::Level OL, bool JIT);
+                      CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 };
 
 /// Mips32/64 little endian target machine.
 ///
 class MipselTargetMachine : public MipsTargetMachine {
   virtual void anchor();
 
 public:
   MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                       StringRef FS, const TargetOptions &Options,
                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                      CodeGenOpt::Level OL, bool JIT);
+                      CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H

lib/Target/Mips/MipsTargetMachine.cpp

 // offset from the stack/frame pointer, using StackGrowsUp enables
 // an easier handling.
 // Using CodeModel::Large enables different CALL behavior.
 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
                                      Optional<Reloc::Model> RM,
                                      Optional<CodeModel::Model> CM,
-                                     CodeGenOpt::Level OL, bool JIT,
+                                     CodeGenOpt::Level OL,
+                                     CodeGenSizeOpt::Level SL, bool JIT,
                                      bool isLittle)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
                         CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
-                        getEffectiveCodeModel(CM), OL),
+                        getEffectiveCodeModel(CM), OL, SL),
       isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
       ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
       Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
                                            Options.StackAlignmentOverride),
       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
                         isLittle, *this, Options.StackAlignmentOverride),
       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
                       isLittle, *this, Options.StackAlignmentOverride) {
   Subtarget = &DefaultSubtarget;
   initAsmInfo();
 }
 
 MipsTargetMachine::~MipsTargetMachine() = default;
 
 void MipsebTargetMachine::anchor() {}
 
 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
                                          StringRef CPU, StringRef FS,
                                          const TargetOptions &Options,
                                          Optional<Reloc::Model> RM,
                                          Optional<CodeModel::Model> CM,
-                                         CodeGenOpt::Level OL, bool JIT)
-    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
+                                         CodeGenOpt::Level OL,
+                                         CodeGenSizeOpt::Level SL, bool JIT)
+    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {}
 
 void MipselTargetMachine::anchor() {}
 
 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
                                          StringRef CPU, StringRef FS,
                                          const TargetOptions &Options,
                                          Optional<Reloc::Model> RM,
                                          Optional<CodeModel::Model> CM,
-                                         CodeGenOpt::Level OL, bool JIT)
-    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
+                                         CodeGenOpt::Level OL,
+                                         CodeGenSizeOpt::Level SL, bool JIT)
+    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true) {}
 
 const MipsSubtarget *
 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
                         ? CPUAttr.getValueAsString().str()

lib/Target/NVPTX/NVPTXTargetMachine.h

 }; // NVPTXTargetMachine.
 
 class NVPTXTargetMachine32 : public NVPTXTargetMachine {
   virtual void anchor();
 public:
   NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
 };
 
 class NVPTXTargetMachine64 : public NVPTXTargetMachine {
   virtual void anchor();
 public:
   NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/NVPTX/NVPTXTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
   return CodeModel::Small;
 }
 
 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool is64bit)
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool is64bit)
     // The pic relocation model is used regardless of what the client has
     // specified, as it is the only relocation model currently supported.
     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
-                        Reloc::PIC_, getEffectiveCodeModel(CM), OL),
+                        Reloc::PIC_, getEffectiveCodeModel(CM), OL, SL),
       is64bit(is64bit), TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
   if (TT.getOS() == Triple::NVCL)
     drvInterface = NVPTX::NVCL;
   else
     drvInterface = NVPTX::CUDA;
   if (!DisableRequireStructuredCFG)
     setRequiresStructuredCFG(true);
   initAsmInfo();
 }
 
 NVPTXTargetMachine::~NVPTXTargetMachine() = default;
 
 void NVPTXTargetMachine32::anchor() {}
 
 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
-    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+                                           CodeGenOpt::Level OL, 
+                                           CodeGenSizeOpt::Level SL, bool JIT)
+    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, false) {}
 
 void NVPTXTargetMachine64::anchor() {}
 
 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
-    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
+    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, true) {}
 
 namespace {
 
 class NVPTXPassConfig : public TargetPassConfig {
 public:
   NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 

lib/Target/Nios2/Nios2TargetMachine.h

class Nios2TargetMachine : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<Nios2Subtarget>> SubtargetMap;
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   Nios2Subtarget Subtarget;
 
 public:
   Nios2TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~Nios2TargetMachine() override;
 
   const Nios2Subtarget *getSubtargetImpl() const { return &Subtarget; }
   const Nios2Subtarget *getSubtargetImpl(const Function &F) const override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 };
 } // namespace llvm
 
 #endif

lib/Target/Nios2/Nios2TargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
   return CodeModel::Small;
 }
 
 Nios2TargetMachine::Nios2TargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool JIT)
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(
           T, computeDataLayout(), TT, CPU, FS, Options,
           getEffectiveRelocModel(RM),
-          getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL),
+          getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL, SL),
       TLOF(make_unique<Nios2TargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 Nios2TargetMachine::~Nios2TargetMachine() {}
 
 const Nios2Subtarget *

lib/Target/PowerPC/PPCTargetMachine.h

private:
   PPCABI TargetABI;
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   ~PPCTargetMachine() override;
 
   const PPCSubtarget *getSubtargetImpl(const Function &F) const override;
   // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
   // subtargets are per-function entities based on the target-specific
   // attributes of each function.
   const PPCSubtarget *getSubtargetImpl() const = delete;

lib/Target/PowerPC/PPCTargetMachine.cpp

 // string with what are (currently) non-function specific overrides as it goes
 // into the LLVMTargetMachine constructor and then using the stored value in the
 // Subtarget constructor below it.
 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
                         computeFSAdditions(FS, OL, TT), Options,
                         getEffectiveRelocModel(TT, RM),
-                        getEffectiveCodeModel(TT, CM, JIT), OL),
+                        getEffectiveCodeModel(TT, CM, JIT), OL, SL),
       TLOF(createTLOF(getTargetTriple())),
       TargetABI(computeTargetABI(TT, Options)) {
   initAsmInfo();
 }
 
 PPCTargetMachine::~PPCTargetMachine() = default;
 
 const PPCSubtarget *

lib/Target/RISCV/RISCVTargetMachine.h

 class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   RISCVSubtarget Subtarget;
 
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
 
   const RISCVSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 };
 }
 
 #endif

lib/Target/RISCV/RISCVTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
   return CodeModel::Small;
 }
 
 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool JIT)
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
-                        getEffectiveCodeModel(CM), OL),
+                        getEffectiveCodeModel(CM), OL, SL),
       TLOF(make_unique<RISCVELFTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 namespace {
 class RISCVPassConfig : public TargetPassConfig {
 public:

lib/Target/Sparc/SparcTargetMachine.h

class SparcTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   SparcSubtarget Subtarget;
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT, bool is64bit);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                     bool JIT, bool is64bit);
   ~SparcTargetMachine() override;
 
   const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
   const SparcSubtarget *getSubtargetImpl(const Function &) const override;
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 
   bool isMachineVerifierClean() const override {
     return false;
   }
 };
 
 /// Sparc 32-bit target machine
 ///
 class SparcV8TargetMachine : public SparcTargetMachine {
   virtual void anchor();
 public:
   SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
 };
 
 /// Sparc 64-bit target machine
 ///
 class SparcV9TargetMachine : public SparcTargetMachine {
   virtual void anchor();
 public:
   SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
 };
 
 class SparcelTargetMachine : public SparcTargetMachine {
   virtual void anchor();
 
 public:
   SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/Sparc/SparcTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
   }
   return CodeModel::Small;
 }
 
 /// Create an ILP32 architecture model
 SparcTargetMachine::SparcTargetMachine(
     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Optional<Reloc::Model> RM,
-    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
+    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+    CodeGenSizeOpt::Level SL, bool JIT, bool is64bit)
     : LLVMTargetMachine(
           T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
           getEffectiveRelocModel(RM),
           getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT),
-          OL),
+          OL, SL),
       TLOF(make_unique<SparcELFTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
   initAsmInfo();
 }
 
 SparcTargetMachine::~SparcTargetMachine() {}
 
 const SparcSubtarget * 

 
 void SparcV8TargetMachine::anchor() { }
 
 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
-    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
+    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {}
 
 void SparcV9TargetMachine::anchor() { }
 
 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
-    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
+    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, true) {}
 
 void SparcelTargetMachine::anchor() {}
 
 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
-    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
+    : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, SL, JIT, false) {}

lib/Target/SystemZ/SystemZTargetMachine.h

 class SystemZTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   SystemZSubtarget Subtarget;
 
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                       CodeGenOpt::Level OL, bool JIT);
+                       CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL,
+                       bool JIT);
   ~SystemZTargetMachine() override;
 
   const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
 
   const SystemZSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 

lib/Target/SystemZ/SystemZTargetMachine.cpp

static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
   return CodeModel::Small;
 }
 
 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
-                                           CodeGenOpt::Level OL, bool JIT)
+                                           CodeGenOpt::Level OL,
+                                           CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(
           T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
           getEffectiveRelocModel(RM),
           getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL),
       TLOF(llvm::make_unique<TargetLoweringObjectFileELF>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }

lib/Target/TargetMachine.cpp

TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const {
   return Model;
 }
 
 /// Returns the optimization level: None, Less, Default, or Aggressive.
 CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; }
 
 void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; }
 
+/// Returns the size optimization level: None, OptSize, or MinSize.
+/// By default, returns None.
+CodeGenSizeOpt::Level TargetMachine::getSizeOptLevel() const {
+  return SizeOptLevel;
+}
+
+void TargetMachine::setSizeOptLevel(CodeGenSizeOpt::Level Level) {
+  SizeOptLevel = Level;
+}
+
 TargetTransformInfo TargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(F.getParent()->getDataLayout());
 }
 
 void TargetMachine::getNameWithPrefix(SmallVectorImpl<char> &Name,
                                       const GlobalValue *GV, Mangler &Mang,
                                       bool MayAlwaysUsePrivate) const {
   if (MayAlwaysUsePrivate || !GV->hasPrivateLinkage()) {

lib/Target/TargetMachineC.cpp

 LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) {
   return unwrap(T)->hasTargetMachine();
 }
 
 LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) {
   return unwrap(T)->hasMCAsmBackend();
 }
 
-LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
-        const char *Triple, const char *CPU, const char *Features,
-        LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc,
+LLVMTargetMachineRef
+LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU,
+                        const char *Features, LLVMCodeGenOptLevel Level,
+                        LLVMCodeGenSizeOptLevel SizeLevel, LLVMRelocMode Reloc,
                         LLVMCodeModel CodeModel) {
   Optional<Reloc::Model> RM;
   switch (Reloc){
     case LLVMRelocStatic:
       RM = Reloc::Static;
       break;
     case LLVMRelocPIC:
       RM = Reloc::PIC_;
       break;
switch (Level) {
     case LLVMCodeGenLevelAggressive:
       OL = CodeGenOpt::Aggressive;
       break;
     default:
       OL = CodeGenOpt::Default;
       break;
   }
 
+  CodeGenSizeOpt::Level SL;
+  switch (SizeLevel) {
+    case LLVMCodeGenSizeLevelNone:
+      SL = CodeGenSizeOpt::None;
+      break;
+    case LLVMCodeGenSizeLevelOptSize:
+      SL = CodeGenSizeOpt::OptSize;
+      break;
+    case LLVMCodeGenSizeLevelMinSize:
+      SL = CodeGenSizeOpt::MinSize;
+      break;
+  }
+
   TargetOptions opt;
   return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM,
-                                             OL, JIT));
+                                             OL, SL, JIT));
 }
 
 void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) { delete unwrap(T); }
 
 LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) {
   const Target* target = &(unwrap(T)->getTarget());
   return wrap(target);
 }

lib/Target/WebAssembly/WebAssemblyTargetMachine.h

class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
 
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
                            Optional<Reloc::Model> RM,
                            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
-                           bool JIT);
+                           CodeGenSizeOpt::Level SL, bool JIT);
 
   ~WebAssemblyTargetMachine() override;
   const WebAssemblySubtarget *
   getSubtargetImpl(const Function &F) const override;
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
   return *RM;
 }
 
 /// Create an WebAssembly architecture model.
 ///
 WebAssemblyTargetMachine::WebAssemblyTargetMachine(
     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
     const TargetOptions &Options, Optional<Reloc::Model> RM,
-    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+    CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(T,
                         TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
                                          : "e-m:e-p:32:32-i64:64-n32:64-S128",
                         TT, CPU, FS, Options, getEffectiveRelocModel(RM),
-                        CM ? *CM : CodeModel::Large, OL),
+                        CM ? *CM : CodeModel::Large, OL, SL),
       TLOF(TT.isOSBinFormatELF() ?
               static_cast<TargetLoweringObjectFile*>(
                   new WebAssemblyTargetObjectFileELF()) :
               static_cast<TargetLoweringObjectFile*>(
                   new WebAssemblyTargetObjectFile())) {
   // WebAssembly type-checks instructions, but a noreturn function with a return
   // type that doesn't match the context will cause a check failure. So we lower
   // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's

lib/Target/X86/X86TargetMachine.h

 class X86TargetMachine final : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
 
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~X86TargetMachine() override;
 
   const X86Subtarget *getSubtargetImpl(const Function &F) const override;
   // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
   // subtargets are per-function entities based on the target-specific
   // attributes of each function.
   const X86Subtarget *getSubtargetImpl() const = delete;
 

lib/Target/X86/X86TargetMachine.cpp

 
 /// Create an X86 target.
 ///
 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Optional<Reloc::Model> RM,
                                    Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   CodeGenOpt::Level OL,
+                                   CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(
           T, computeDataLayout(TT), TT, CPU, FS, Options,
           getEffectiveRelocModel(TT, RM),
-          getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
+          getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
+          OL, SL),
       TLOF(createTLOF(getTargetTriple())) {
   // Windows stack unwinder gets confused when execution flow "falls through"
   // after a call to 'noreturn' function.
   // To prevent that, we emit a trap for 'unreachable' IR instructions.
   // (which on X86, happens to be the 'ud2' instruction)
   // On PS4, the "return address" of a 'noreturn' call must still be within
   // the calling function, and TrapUnreachable is an easy way to get that.
   // The check here for 64-bit windows is a bit icky, but as we're unlikely

lib/Target/XCore/XCoreTargetMachine.h

 class XCoreTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   XCoreSubtarget Subtarget;
 
 public:
   XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                     CodeGenOpt::Level OL, bool JIT);
+                     CodeGenOpt::Level OL, CodeGenSizeOpt::Level SL, bool JIT);
   ~XCoreTargetMachine() override;
 
   const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
   const XCoreSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 
   // Pass Pipeline Configuration

lib/Target/XCore/XCoreTargetMachine.cpp

 
 /// Create an ILP32 architecture model
 ///
 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        Optional<CodeModel::Model> CM,
-                                       CodeGenOpt::Level OL, bool JIT)
+                                       CodeGenOpt::Level OL,
+                                       CodeGenSizeOpt::Level SL, bool JIT)
     : LLVMTargetMachine(
           T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
-          getEffectiveCodeModel(CM), OL),
+          getEffectiveCodeModel(CM), OL, SL),
       TLOF(llvm::make_unique<XCoreTargetObjectFile>()),
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 XCoreTargetMachine::~XCoreTargetMachine() = default;
 
 namespace {

unittests/CodeGen/MachineInstrTest.cpp

private:
   BogusTargetLowering TL;
   TargetInstrInfo TII;
 };
 
 class BogusTargetMachine : public LLVMTargetMachine {
 public:
   BogusTargetMachine()
       : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
-                          Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
+                          Reloc::Static, CodeModel::Small, CodeGenOpt::Default,
+                          CodeGenSizeOpt::None),
         ST(*this) {}
   ~BogusTargetMachine() override {}
 
   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
     return &ST;
   }
 
 private: