[InstCombine] Remove decanonicalizing transforms of selects

[mkazantsev]

Summary

Currently InstCombine tends to recognize patterns like

%cmp = icmp slt iA %x, 0
%select = select i1 %cmp, iB %A, iB %B

as bit-test against highest bit, and convert it into one of multiple shift-based patterns
which may look differently depending on types iA and iB and values of %A and %B.
It only happens if %A and %B are constants. We observe at least three possible sutiatons:

Case 1:

%c2 = icmp slt %a, 0
%select1 = select %c2, -1, %Greater

converts into

(%a s>> 31) | %Greater

Case 2:

%c2 = icmp slt i32 %a, 0
%select1 = select i1 %c2, i32 %Less, i32 %Greater

converts into

(%a s>> 31) - (%Less - %Greater) + %Greater

or, if it is the equivalent, to

(%a s>> 31) - (%Less - %Greater) | %Greater

Case 3:

%c2 = icmp slt i64 %a, 0
%select1 = select i1 %c2, i32 %Less, i32 %Greater

converts to

(trunc (%a s>> 63) to i32) - (%Less - %Greater) + %Greater

There are possibly more variatons of this. The general idea is that select by comparison with 0 or -1
gets transformed into multiple different patterns, and very small changes in conditions and constants
may change this pattern. There is no clear benefits of that transforms, but the obvious downside of them
is decanonicalization. For example, we have a matcher of three-ways comparison that expects to see the
pattern of the following form:

%c1 = icmp eq %a, 0
%c2 = icmp slt %a, 0
%select1 = select %c2, %Less, %Greater
%select2 = select %c1, %Equal, %select2

This pattern is widely seen across the code: it is a canonical representation of three-ways comparators
that return -1, 0 or 1 if %a is less, equal or greater than zero. In the result of transforms described in
cases 1, 2, 3, the pair of %c2 and %select1 gets transformed into something different (with shifts, casts
and different bit operations). So the three-way comparison pattern cannot be recognized anymore.

This patch removes the transforms that make us replace select by comparison against zero with all this bit
magic. We want to prefer selects over random bit magic as a more canonical form of doing that: select
has more transparent semantics and other parts of InstCombine make use it rather than try to recognize
that some sequence of non-trivial bit instructions actually represents a select by comparison against zero.

It is codegen's work to turn selects into bit operations in the end of pipeline to calculate it efficiently if
shifts are faster than cmoves, but doing so too early has no benifits and has obvious pessimization of other
pattern matchers within instcombine.

In this patch we only stop harmful transforms from happening. The code that turns all this bit magic back
to selects will go in a separate patch.

[lebedev.ri]

test/Transforms/InstCombine/select-of-bittest.ll

662 ↗

(On Diff #143226)

Please use utils/update_test_checks.py.

[mkazantsev]

Formatted tests.

[lebedev.ri]

test/Transforms/InstCombine/select-of-bittest.ll

660 ↗

(On Diff #143266)

For each of those, could you please add vector tests.
Something like:

define i32 @compare_to_zero_mismatched_types_idiomatic_trunc(i64 %x) {
  %cmp = icmp slt i64 %x, 0
  %select1 = select i1 %cmp, i32 -1, i32 1
  ret i32 %select1
}

define <2 x i32> @compare_to_zero_mismatched_types_idiomatic_trunc_splatvec(<2 x i64> %x) {
  %cmp = icmp slt <2 x i64> %x, <i64 0, i64 0>
  %select1 = select <2 x i1> %cmp, <i32 -1, i32 -1>, <i32 1, i32 1>
  ret <2 x i32> %select1
}

define <3 x i32> @compare_to_zero_mismatched_types_idiomatic_trunc_splatvec_undef(<3 x i64> %x) {
  %cmp = icmp slt <3 x i64> %x, <i64 0, i64 undef, i64 0>
  %select1 = select <3 x i1> %cmp, <i32 -1, i64 undef, i32 -1>, <i32 1, i64 undef, i32 1>
  ret <3 x i32> %select1
}

; May be more than one
define <3 x i32> @compare_to_zero_mismatched_types_idiomatic_trunc_nonsplatvec(<3 x i64> %x) {
  %cmp = icmp slt <3 x i64> %x, <i64 0, i64 undef, i64 0>
  %select1 = select <3 x i1> %cmp, <i32 -1, i64 0, i32 1>, <i32 1, i64 0, i32 -1>
  ret <3 x i32> %select1
}

[spatel]

I don't think we should be doing any of these select-of-constant transforms in instcombine.

It's worse for code analysis, more IR instructions, and may be detrimental to perf. Think about the cases where a conditional move executes at the same speed as a simple add (Ryzen?) or we have profile data for the compare, so branch prediction is perfect.

There's lots of code that does this kind of thing in the DAG, and that's where I think it belongs (using target hooks as needed). There was some discussion about this on llvm-dev here:
https://groups.google.com/forum/#!topic/llvm-dev/pid_thv2X-A

So I think we should be removing some of these transforms from instcombine rather than adding to them.

[lebedev.ri]

Other than that inline comment, i think it would be nice to commit
the baseline tests (as of trunk), so the effect of this proposal could be observed.
Even if the code changes won't land, this would at least document the current behavior.

test/Transforms/InstCombine/select-of-bittest.ll

660 ↗

(On Diff #143266)

Oh, also, this is a really bad place to add these tests.
They should either go to a new file, or at least before

; ============================================================================ ;
; Negative tests. Should not be folded.
; ============================================================================ ;

[lebedev.ri]

In D45862#1073841, @spatel wrote:

I don't think we should be doing any of these select-of-constant transforms in instcombine.

It's worse for code analysis, more IR instructions, and may be detrimental to perf. Think about the cases where a conditional move executes at the same speed as a simple add (Ryzen?) or we have profile data for the compare, so branch prediction is perfect.

There's lots of code that does this kind of thing in the DAG, and that's where I think it belongs (using target hooks as needed). There was some discussion about this on llvm-dev here:
https://groups.google.com/forum/#!topic/llvm-dev/pid_thv2X-A

So I think we should be removing some of these transforms from instcombine rather than adding to them.

There is a second side to this though.

Even if all such "performance-degrading" transforms are removed from instcombine
(yes, i think the pass is rather huge and monolithic, this is a problem), it won't solve the problem.
The same 'bad' patterns surely could be produced via some other way.

I don't see how this is any different than lowering intrinsics.
Of course, they are no longer intrinsics, but IR, so optimizations may
break their canonical form, and backend will need to be adjusted
to recognize the IR patters (and potentially recognize the patterns
that did not originate form intrinsics, which is great).

So i'd say this really is backend's (DAGCombine?) problem.
This is just a question of whether or not there is interest to have a high quality codegen,
regardless of the input. It should recognize the 'bad' patterns, and if profitable,
transform to improve 'performance'. In this case, back to select.

And yes, absolutely, this is more complicated than just "stop dealing with it in instcombine" :)

[spatel]

In D45862#1074397, @lebedev.ri wrote:

In D45862#1073841, @spatel wrote:

I don't think we should be doing any of these select-of-constant transforms in instcombine.

It's worse for code analysis, more IR instructions, and may be detrimental to perf. Think about the cases where a conditional move executes at the same speed as a simple add (Ryzen?) or we have profile data for the compare, so branch prediction is perfect.

There's lots of code that does this kind of thing in the DAG, and that's where I think it belongs (using target hooks as needed). There was some discussion about this on llvm-dev here:
https://groups.google.com/forum/#!topic/llvm-dev/pid_thv2X-A

So I think we should be removing some of these transforms from instcombine rather than adding to them.

There is a second side to this though.

Even if all such "performance-degrading" transforms are removed from instcombine
(yes, i think the pass is rather huge and monolithic, this is a problem), it won't solve the problem.
The same 'bad' patterns surely could be produced via some other way.

I don't see how this is any different than lowering intrinsics.
Of course, they are no longer intrinsics, but IR, so optimizations may
break their canonical form, and backend will need to be adjusted
to recognize the IR patters (and potentially recognize the patterns
that did not originate form intrinsics, which is great).

So i'd say this really is backend's (DAGCombine?) problem.
This is just a question of whether or not there is interest to have a high quality codegen,
regardless of the input. It should recognize the 'bad' patterns, and if profitable,
transform to improve 'performance'. In this case, back to select.

And yes, absolutely, this is more complicated than just "stop dealing with it in instcombine" :)

I agree. Let me clarify the suggestion: don't just remove these control-flow to data-flow transforms from instcombine. Canonicalize to the cmp+select form. And then let the DAG convert it back if it's profitable. I did some fraction (what I thought were the most common parts) of this job already following the cited llvm-dev discussion. Here's the direct link to that reply:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html

[mkazantsev]

Hi @spatel @lebedev.ri,

Actually I am absolutely agreed that these transforms produce really bad code which looks like a canonicalization breach. Let me give you a bit more context about my motivation for this change. I basically need that the following pattern was recognized correctly as three-way comparison:

%cmp1 = icmp eq %x, 0
%cmp2 = icmp slt %x, 0
%s1 = select i1 %cmp2, -1, 1
%s2 = select i1 %cmp1, 0, %s1

It is a typical pattern that we see in all comparators. We have a function matchThreeWayIntCompare that used to detect such a pattern. However at some point InstCombine started recognizing the pattern of %cmp2, %s1 as a bit test of the highest bit, removed it and inserted the shift-based bit test instead. Even worse, it does insert *different* patterns for case when both %x and %s1 are i32 or when they are of different types.

The problem is wide-spread across InstCombine: we seem to have *many* transforms of this kind spread across the code. And which of them will be applied is always a surprise: some of them are implemented for general case and some are limited. As result, we might end up with a dozen of different bit-test patterns that all represent a three-ways comparison.

This patch was an attempt to canonicalize all these transforms, so that at least for the same pattern they were done in the same manner regardless of types. Here I was taking an assumption like "okay, we are doing all this bit-test stuff anyways, let's at least do it uniformly". Because now what we have is a counter-canonicalization of this pattern.

I agree that in ideal world we should just remove all this job connected to adding bit-tests instead of this select, or even do it in opposite way (so that bit-tests are converted to select). I see two reasons why it is impossible.

1. We have no idea how it impacts performance in the particular cases for which they were added.
2. We have little understanding of how other transforms and optimizations will react on that, and will we break something or not. I have a crawling suspicion that all this stuff was done for vectorization, and that the vectorizer might expect this bit stuff rather than selects. I need someone familiar with vectorizer's code to confirm or refute that.

I will be totally happy if we decide to not transform selects into bittests. But I am hesitant to make a change this big in the part of code I am unfamiliar with, as well as I am unfamiliar with the reasons why it was done at all and whether it helps the vectorization. So I need the confirmation from vectorizer people that selects there are OK.

For now, my point is the following: yes, we are *already* doing all this bit magic. Yes, it looks like miscanonicalization, and we can discuss getting rid of all such transforms at all. But since we are already doing it and haven't yet decided to clear it off, let's at least do it well. Once we decide that all this stuff is counter-canonical, we can happily remove all this. What do you think of that?

Thanks,
Max

P.S. I've also added Benjamin Kramer who was the original author of this transform to take a look.

[mkazantsev]

You can also have more context of why it was done from the commit messages of: D45854 D45855 D45856 D45863.

[spatel]

In D45862#1074819, @mkazantsev wrote:

For now, my point is the following: yes, we are *already* doing all this bit magic. Yes, it looks like miscanonicalization, and we can discuss getting rid of all such transforms at all. But since we are already doing it and haven't yet decided to clear it off, let's at least do it well. Once we decide that all this stuff is counter-canonical, we can happily remove all this. What do you think of that?

I understand this as a short-term goal and local improvement, but I think if we don't reverse the direction now, we'll never correct it. For example, it took over 5 years to correct:
rL159230
with
rL319964

See also the mentioned commits where we may extend the DAG transforms and possibly solve the patterns that you are looking at:
rL296977
rL311731

You mention the vectorizers as a possible source for wanting to do the bit magic, but I think that most targets would actually do better vectorizing a select at this point because vsel/bsl/blend type of instructions are usually part of a vector ISA. This came up in:
https://bugs.llvm.org/show_bug.cgi?id=6773#c9 (and I'm not locating the review thread, but Roman has proposed tests for the vector cases)

Can you provide an IR -> asm example for one/some of the problem cases that led you to this (or preferably, file bug reports for them)? If we can fix the cases that we know would regress with a reversal of this IR canonicalization, then we should push ahead with that effort and fix instcombine. We can't guarantee that there won't be regressions, but we should be able to fix problems as they are reported.

[spatel]

Also see D24480 and the list of proposals and commits mentioned there.

[mkazantsev]

In D45862#1075265, @spatel wrote:

Can you provide an IR -> asm example for one/some of the problem cases that led you to this (or preferably, file bug reports for them)? If we can fix the cases that we know would regress with a reversal of this IR canonicalization, then we should push ahead with that effort and fix instcombine. We can't guarantee that there won't be regressions, but we should be able to fix problems as they are reported.

Sure, please take a look at https://bugs.llvm.org/show_bug.cgi?id=37147
You can also use tests from D45854 D45855 D45856 D45863 for reference: this is the IR we expect InstCombine to produce.

[mkazantsev]

Just for note: I am not aware of any asm advantages or disadvantages of what we have now in practice. I am only speculating about it in assumption that this bit-test magic was done with some reason. I don't have any real evidence that it is somehow good or bad in asm, but what I know is that does pessimize three-way comparison recognition.

[spatel]

In D45862#1076327, @mkazantsev wrote:

Just for note: I am not aware of any asm advantages or disadvantages of what we have now in practice. I am only speculating about it in assumption that this bit-test magic was done with some reason. I don't have any real evidence that it is somehow good or bad in asm, but what I know is that does pessimize three-way comparison recognition.

I forgot about this, but I think I asked about the same problem as PR37147 here:
http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html

...and the conclusion was that we want selects (or at least nobody strongly opposed that). And so I went to the DAG and made the necessary changes to allow producing good asm for all targets for those patterns (ie, there's a hook to convert those back to bit math). So there should be little risk in removing/inverting the instcombines at this point.

I'm looking closer now at how to replace some of the instcombines now without regressing anything. I expect this is going to take multiple steps to unravel. For example, we even have a 'm_Signum' matcher that's looking for shifts.

[mkazantsev]

Let's try an alternative approach. In this patch we remove harmful transforms that replace selects with random pieces of bit magic.

Here we only stop harmful transforms. The patch that will canonicalize all this bit magic to selects will go separately.

[spatel]

In D45862#1077652, @mkazantsev wrote:

Let's try an alternative approach. In this patch we remove harmful transforms that replace selects with random pieces of bit magic.

Here we only stop harmful transforms. The patch that will canonicalize all this bit magic to selects will go separately.

I agree with this direction (and I have a patch that would do something similar), but this is going too far. We should remove the transforms that are harmful, but without creating known regressions. This requires writing new, more specific folds as we remove the over-reaching logic.

As you can see from test15g and test15h, there are good folds buried in here. Those correspond to something like this:

Name: set_bit_if_masked_val_is_clear
Pre: isPowerOf2(C1) && ((C2 ^ C3) == C1) && (C2 u> C3)
 %t1 = and i8 %x, C1
 %t2 = icmp eq i8 %t1, 0
 %r = select i1 %t2, i8 C2, i8 C3
=>
 %r = xor i8 %t1, C2

Name: set_bit_if_masked_val_is_set
Pre: isPowerOf2(C1) && ((C2 ^ C3) == C1) && (C2 u> C3)
 %t1 = and i8 %x, C1
 %t2 = icmp ne i8 %t1, 0
 %r = select i1 %t2, i8 C2, i8 C3
=>
 %r = or i8 %t1, C3

Name: clear_bit_if_masked_val_is_clear
Pre: isPowerOf2(C1) && ((C2 ^ C3) == C1) && (C3 u> C2)
 %t1 = and i8 %x, C1
 %t2 = icmp eq i8 %t1, 0
 %r = select i1 %t2, i8 C2, i8 C3
=>
 %r = or i8 %t1, C2
 
Name: clear_bit_if_masked_val_is_set
Pre: isPowerOf2(C1) && ((C2 ^ C3) == C1) && (C3 u> C2)
 %t1 = and i8 %x, C1
 %t2 = icmp ne i8 %t1, 0
 %r = select i1 %t2, i8 C2, i8 C3
=>
 %r = xor i8 %t1, C3

https://rise4fun.com/Alive/XG7

To verify that we're doing this properly, we need to add more tests for patterns like this. The current set isn't providing very good coverage.

[mkazantsev]

I am confused. Didn't we agree on that replacement of selects with bit-wise logic, if it's profitable, should be a part of backend's work, and here we want selects because they have a more clear semantics that can be used by other transforms, rather than teaching every single transform to recognize the bit magic as select? You are giving some examples where codegen definitely could do what you are showing.

[spatel]

In D45862#1080423, @mkazantsev wrote:

I am confused. Didn't we agree on that replacement of selects with bit-wise logic, if it's profitable, should be a part of backend's work, and here we want selects because they have a more clear semantics that can be used by other transforms, rather than teaching every single transform to recognize the bit magic as select? You are giving some examples where codegen definitely could do what you are showing.

1. I think it's clearly better for IR to eliminate the select if we can reduce the instruction count too. It can lead to more reduction here in instcombine as seen in test15g. So that's why I'm proposing to add optimizations for these patterns: https://rise4fun.com/Alive/XG7 in D46086 (note that test15g is not regressed there).
2. Even if you disagree with having those transforms, I don't think we should remove it as the first step. We're already going to be at risk for revert due to perf regressions with D46086 even though those are all IR improvements based on our reasoning so far. I'm purposely trying to minimize the diffs in that step, so we have a better chance of pushing this through.

[mkazantsev]

In D45862#1081291, @spatel wrote:

1. I think it's clearly better for IR to eliminate the select if we can reduce the instruction count too.

Not if local improvement on one step will break another step which will break us even more improvement. You save one instruction by doing bit magic and kill the further transform that would eliminate 4 instructions. My point is that the canonicalization is generally a more useful thing in a long run than saving of one or two instructions now and pessimizing another more powerful transform later. Current strategy of saving one instruction by adding this bit magic produces horrible code on the tests I've added.

As for test15g, I will give some more thought to what can be done to it.

In D45862#1081291, @spatel wrote:

So that's why I'm proposing to add optimizations for these patterns: https://rise4fun.com/Alive/XG7 in D46086 (note that test15g is not regressed there).

Why in InstCombine? These transforms are very simple, DAG selector should be able to do what you want, but later. The only possible profit I see from having this done in InstCombine is that it may affect the behavior of inlining/unrolling that calculate cost of the code, but it's only matter of tuning the cost functions if the need shows up.

[spatel]

In D45862#1081907, @mkazantsev wrote:

Current strategy of saving one instruction by adding this bit magic produces horrible code on the tests I've added.

Please commit these tests, so we can see the current output and compare any differences between this patch and the other patch.

[mkazantsev]

In D45862#1081919, @spatel wrote:

In D45862#1081907, @mkazantsev wrote:

Current strategy of saving one instruction by adding this bit magic produces horrible code on the tests I've added.

Please commit these tests, so we can see the current output and compare any differences between this patch and the other patch.

Here it is. Please compare the cases when we compare against zero with cases when we compare against any other value.
https://reviews.llvm.org/rL331100

[mkazantsev]

Updated the patch to show the impact better. Test 15g possibly needs closer evaluation, however it seems to be the only case where the code has become worse. Might be a separate issue.

[spatel]

In D45862#1081927, @mkazantsev wrote:

In D45862#1081919, @spatel wrote:

In D45862#1081907, @mkazantsev wrote:

Current strategy of saving one instruction by adding this bit magic produces horrible code on the tests I've added.

Please commit these tests, so we can see the current output and compare any differences between this patch and the other patch.

Here it is. Please compare the cases when we compare against zero with cases when we compare against any other value.
https://reviews.llvm.org/rL331100

Thanks! I updated D46086. Unless I've missed it, the diffs for the 3-way-compare tests are identical?

[mkazantsev]

Thanks @spatel , pretty much so!

[mkazantsev]

Abandoning in favour of D46086

[spatel]

test/Transforms/InstCombine/unrecognized_three-way-comparison.ll

11–13

Not sure exactly where the logic hole is that caused this, but I moved a fold to InstSimplify in:
rL347896
...and now we get this case and the similar 'compare_against_arbitrary_value_type_mismatch' test.

lib/Transforms/InstCombine/InstCombineSelect.cpp

static Value *foldSelectICmpAnd(SelectInst &Sel, ICmpInst *Cmp,
   Type *SelType = Sel.getType();
   if (SelType->isVectorTy() != Cmp->getType()->isVectorTy())
     return nullptr;
 
   Value *V;
   APInt AndMask;
   bool CreateAnd = false;
   ICmpInst::Predicate Pred = Cmp->getPredicate();
+
+  bool ShouldNotVal = !SelTC->isNullValue();
+  ShouldNotVal ^= Pred == ICmpInst::ICMP_NE;
+  if (ShouldNotVal)
+    return nullptr;
+
   if (ICmpInst::isEquality(Pred)) {
     if (!match(Cmp->getOperand(1), m_Zero()))
       return nullptr;
 
     V = Cmp->getOperand(0);
     const APInt *AndRHS;
     if (!match(V, m_And(m_Value(), m_Power2(AndRHS))))
       return nullptr;
if (ValZeros > AndZeros) {
     V = Builder.CreateShl(V, ValZeros - AndZeros);
   } else if (ValZeros < AndZeros) {
     V = Builder.CreateLShr(V, AndZeros - ValZeros);
     V = Builder.CreateZExtOrTrunc(V, SelType);
   } else {
     V = Builder.CreateZExtOrTrunc(V, SelType);
   }
 
-  // Okay, now we know that everything is set up, we just don't know whether we
-  // have a icmp_ne or icmp_eq and whether the true or false val is the zero.
-  bool ShouldNotVal = !TC.isNullValue();
-  ShouldNotVal ^= Pred == ICmpInst::ICMP_NE;
-  if (ShouldNotVal)
-    V = Builder.CreateXor(V, ValC);
-
   // Apply an offset if needed.
   if (!Offset.isNullValue())
     V = Builder.CreateAdd(V, ConstantInt::get(V->getType(), Offset));
   return V;
 }
 
 /// We want to turn code that looks like this:
 ///   %C = or %A, %B
if (Instruction *NewSel = canonicalizeMinMaxWithConstant(SI, *ICI, Builder))
     return NewSel;
 
   bool Changed = adjustMinMax(SI, *ICI);
 
   ICmpInst::Predicate Pred = ICI->getPredicate();
   Value *CmpLHS = ICI->getOperand(0);
   Value *CmpRHS = ICI->getOperand(1);
 
-  // Transform (X >s -1) ? C1 : C2 --> ((X >>s 31) & (C2 - C1)) + C1
-  // and       (X <s  0) ? C2 : C1 --> ((X >>s 31) & (C2 - C1)) + C1
-  // FIXME: Type and constness constraints could be lifted, but we have to
-  //        watch code size carefully. We should consider xor instead of
-  //        sub/add when we decide to do that.
-  // TODO: Merge this with foldSelectICmpAnd somehow.
-  if (CmpLHS->getType()->isIntOrIntVectorTy() &&
-      CmpLHS->getType() == TrueVal->getType()) {
-    const APInt *C1, *C2;
-    if (match(TrueVal, m_APInt(C1)) && match(FalseVal, m_APInt(C2))) {
-      ICmpInst::Predicate Pred = ICI->getPredicate();
-      Value *X;
-      APInt Mask;
-      if (decomposeBitTestICmp(CmpLHS, CmpRHS, Pred, X, Mask, false)) {
-        if (Mask.isSignMask()) {
-          assert(X == CmpLHS && "Expected to use the compare input directly");
-          assert(ICmpInst::isEquality(Pred) && "Expected equality predicate");
-
-          if (Pred == ICmpInst::ICMP_NE)
-            std::swap(C1, C2);
-
-          // This shift results in either -1 or 0.
-          Value *AShr = Builder.CreateAShr(X, Mask.getBitWidth() - 1);
-
-          // Check if we can express the operation with a single or.
-          if (C2->isAllOnesValue())
-            return replaceInstUsesWith(SI, Builder.CreateOr(AShr, *C1));
-
-          Value *And = Builder.CreateAnd(AShr, *C2 - *C1);
-          return replaceInstUsesWith(SI, Builder.CreateAdd(And,
-                                        ConstantInt::get(And->getType(), *C1)));
-        }
-      }
-    }
-  }
-
   if (Value *V = foldSelectICmpAnd(SI, ICI, Builder))
     return replaceInstUsesWith(SI, V);
 
   // NOTE: if we wanted to, this is where to detect integer MIN/MAX
 
   if (CmpRHS != CmpLHS && isa<Constant>(CmpRHS)) {
     if (CmpLHS == TrueVal && Pred == ICmpInst::ICMP_EQ) {
       // Transform (X == C) ? X : Y -> (X == C) ? C : Y

test/Transforms/InstCombine/rem.ll

 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %A = urem i32 1, %X
   ret i32 %A
 }
 
 define i32 @test18(i16 %x, i32 %y) {
 ; CHECK-LABEL: @test18(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i16 [[X:%.*]], 3
-; CHECK-NEXT:    [[TMP2:%.*]] = and i16 [[TMP1]], 32
-; CHECK-NEXT:    [[TMP3:%.*]] = xor i16 [[TMP2]], 63
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], [[Y:%.*]]
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i16 [[X:%.*]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 63, i32 31
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP3]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %1 = and i16 %x, 4
   %2 = icmp ne i16 %1, 0
   %3 = select i1 %2, i32 32, i32 64
   %4 = urem i32 %y, %3
   ret i32 %4
 }
 

test/Transforms/InstCombine/select-icmp-and.ll

;
   %Y = and i1023 %X, 64
   %t = icmp ne i1023 %Y, 0
   %V = select i1 %t, i1023 64, i1023 0
   ret i1023 %V
 }
 
 define i32 @test35(i32 %x) {
 ; CHECK-LABEL: @test35(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 40
-; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 60
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sge i32 %x, 0
   %cond = select i1 %cmp, i32 60, i32 100
   ret i32 %cond
 }
 
 define <2 x i32> @test35vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test35vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 40, i32 40>
-; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw <2 x i32> [[TMP2]], <i32 60, i32 60>
-; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+; CHECK-NEXT:    ret <2 x i32> [[COND]]
 ;
   %cmp = icmp sge <2 x i32> %x, <i32 0, i32 0>
   %cond = select <2 x i1> %cmp, <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
   ret <2 x i32> %cond
 }
 
 ; Make sure we can still perform this optimization with a truncate present
 define i32 @test35_with_trunc(i64 %x) {
 ; CHECK-LABEL: @test35_with_trunc(
 ; CHECK-NEXT:    [[X1:%.*]] = trunc i64 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X1]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 40
-; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 60
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X1]], -1
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %x1 = trunc i64 %x to i32
   %cmp = icmp sge i32 %x1, 0
   %cond = select i1 %cmp, i32 60, i32 100
   ret i32 %cond
 }
 
 define i32 @test36(i32 %x) {
 ; CHECK-LABEL: @test36(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -40
-; CHECK-NEXT:    [[TMP3:%.*]] = add nsw i32 [[TMP2]], 100
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 60, i32 100
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 0
   %cond = select i1 %cmp, i32 60, i32 100
   ret i32 %cond
 }
 
 define <2 x i32> @test36vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test36vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 -40, i32 -40>
-; CHECK-NEXT:    [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 100, i32 100>
-; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
+; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
+; CHECK-NEXT:    ret <2 x i32> [[COND]]
 ;
   %cmp = icmp slt <2 x i32> %x, <i32 0, i32 0>
   %cond = select <2 x i1> %cmp, <2 x i32> <i32 60, i32 60>, <2 x i32> <i32 100, i32 100>
   ret <2 x i32> %cond
 }
 
 define i32 @test37(i32 %x) {
 ; CHECK-LABEL: @test37(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], 1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 1, i32 -1
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %cond = select i1 %cmp, i32 1, i32 -1
   ret i32 %cond
 }
 
 define <2 x i32> @test37vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test37vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
-; CHECK-NEXT:    [[TMP2:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT:    ret <2 x i32> [[TMP2]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 -1, i32 -1>
+; CHECK-NEXT:    ret <2 x i32> [[COND]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 -1, i32 -1>
   ret <2 x i32> %cond
 }
 
 define i32 @test65(i64 %x) {
 ; CHECK-LABEL: @test65(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 3
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], 42
-; CHECK-NEXT:    ret i32 [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], 16
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = and i64 %x, 16
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test65vec(<2 x i64> %x) {
 ; CHECK-LABEL: @test65vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 3, i64 3>
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP4:%.*]] = xor <2 x i32> [[TMP3]], <i32 42, i32 42>
-; CHECK-NEXT:    ret <2 x i32> [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 16, i64 16>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and <2 x i64> %x, <i64 16, i64 16>
   %2 = icmp ne <2 x i64> %1, zeroinitializer
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test66(i64 %x) {
 ; CHECK-LABEL: @test66(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], 42
-; CHECK-NEXT:    ret i32 [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], 4294967296
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = and i64 %x, 4294967296
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test66vec(<2 x i64> %x) {
 ; CHECK-LABEL: @test66vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 31, i64 31>
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP4:%.*]] = xor <2 x i32> [[TMP3]], <i32 42, i32 42>
-; CHECK-NEXT:    ret <2 x i32> [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 4294967296, i64 4294967296>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and <2 x i64> %x, <i64 4294967296, i64 4294967296>
   %2 = icmp ne <2 x i64> %1, zeroinitializer
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 ; Make sure we don't try to optimize a scalar 'and' with a vector select.
 define <2 x i32> @test66vec_scalar_and(i64 %x) {
 ; CHECK-LABEL: @test66vec_scalar_and(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], 4294967296
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and i64 %x, 4294967296
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test67(i16 %x) {
 ; CHECK-LABEL: @test67(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i16 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = and i16 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = xor i16 [[TMP2]], 42
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
-; CHECK-NEXT:    ret i32 [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i16 [[X:%.*]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
+; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = and i16 %x, 4
   %2 = icmp ne i16 %1, 0
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test67vec(<2 x i16> %x) {
 ; CHECK-LABEL: @test67vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 1, i16 1>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i16> [[TMP1]], <i16 2, i16 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i16> [[TMP2]], <i16 42, i16 42>
-; CHECK-NEXT:    [[TMP4:%.*]] = zext <2 x i16> [[TMP3]] to <2 x i32>
-; CHECK-NEXT:    ret <2 x i32> [[TMP4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i16> [[X:%.*]], <i16 4, i16 4>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i16> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
+; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and <2 x i16> %x, <i16 4, i16 4>
   %2 = icmp ne <2 x i16> %1, zeroinitializer
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test71(i32 %x) {
 ; CHECK-LABEL: @test71(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 42
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 42, i32 40
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = and i32 %x, 128
   %2 = icmp ne i32 %1, 0
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test71vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test71vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i32> [[TMP2]], <i32 42, i32 42>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 128, i32 128>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 42, i32 42>, <2 x i32> <i32 40, i32 40>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and <2 x i32> %x, <i32 128, i32 128>
   %2 = icmp ne <2 x i32> %1, <i32 0, i32 0>
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test72(i32 %x) {
 ; CHECK-LABEL: @test72(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 40, i32 42
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = and i32 %x, 128
   %2 = icmp eq i32 %1, 0
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test72vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test72vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = or <2 x i32> [[TMP2]], <i32 40, i32 40>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 128, i32 128>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = and <2 x i32> %x, <i32 128, i32 128>
   %2 = icmp eq <2 x i32> %1, <i32 0, i32 0>
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test73(i32 %x) {
 ; CHECK-LABEL: @test73(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 6
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 40, i32 42
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = trunc i32 %x to i8
   %2 = icmp sgt i8 %1, -1
   %3 = select i1 %2, i32 40, i32 42
   ret i32 %3
 }
 
 define <2 x i32> @test73vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test73vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = or <2 x i32> [[TMP2]], <i32 40, i32 40>
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i8>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i8> [[TMP1]], <i8 -1, i8 -1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
 ;
   %1 = trunc <2 x i32> %x to <2 x i8>
   %2 = icmp sgt <2 x i8> %1, <i8 -1, i8 -1>
   %3 = select <2 x i1> %2, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %3
 }
 
 define i32 @test74(i32 %x) {
 ; CHECK-LABEL: @test74(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = or i32 [[TMP2]], 40
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 40, i32 42
+; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %1 = icmp sgt i32 %x, -1
   %2 = select i1 %1, i32 40, i32 42
   ret i32 %2
 }
 
 define <2 x i32> @test74vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test74vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = or <2 x i32> [[TMP2]], <i32 40, i32 40>
-; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
+; CHECK-NEXT:    ret <2 x i32> [[TMP2]]
 ;
   %1 = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %2 = select <2 x i1> %1, <2 x i32> <i32 40, i32 40>, <2 x i32> <i32 42, i32 42>
   ret <2 x i32> %2
 }
 
 ;; Code sequence for (X & 16) ? 16 : 0
 define i32 @test15a(i32 %X) {
 ; CHECK-LABEL: @test15a(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 16
 ; CHECK-NEXT:    ret i32 [[T1]]
 ;
   %t1 = and i32 %X, 16
   %t2 = icmp eq i32 %t1, 0
   %t3 = select i1 %t2, i32 0, i32 16
   ret i32 %t3
 }
 
 ;; Code sequence for (X & 32) ? 0 : 24
 define i32 @test15b(i32 %X) {
 ; CHECK-LABEL: @test15b(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 32
-; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[T1]], 32
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 32, i32 0
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 32
   %t2 = icmp eq i32 %t1, 0
   %t3 = select i1 %t2, i32 32, i32 0
   ret i32 %t3
 }
 
 ;; Alternate code sequence for (X & 16) ? 16 : 0
;
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 256, i32 0
   ret i32 %t3
 }
 
 ;; (a & 128) ? 0 : 256
 define i32 @test15f(i32 %X) {
 ; CHECK-LABEL: @test15f(
-; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[T1]], 256
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], 256
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 128
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 256, i32 0
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 128
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 0, i32 256
   ret i32 %t3
 }
 
 ;; (a & 8) ? -1 : -9
 define i32 @test15g(i32 %X) {
 ; CHECK-LABEL: @test15g(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -9
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 -9, i32 -1
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 8
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 -1, i32 -9
   ret i32 %t3
 }
 
 ;; (a & 8) ? -9 : -1
 define i32 @test15h(i32 %X) {
 ; CHECK-LABEL: @test15h(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -9
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], 8
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 -1, i32 -9
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 8
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 -9, i32 -1
   ret i32 %t3
 }
 
 ;; (a & 2) ? 577 : 1089
 define i32 @test15i(i32 %X) {
 ; CHECK-LABEL: @test15i(
-; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[T1]], 512
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], 512
-; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 577
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 1089, i32 577
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 2
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 577, i32 1089
   ret i32 %t3
 }
 
 ;; (a & 2) ? 1089 : 577
 define i32 @test15j(i32 %X) {
 ; CHECK-LABEL: @test15j(
-; CHECK-NEXT:    [[T1:%.*]] = shl i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[T1]], 512
-; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 577
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 577, i32 1089
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %X, 2
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 1089, i32 577
   ret i32 %t3
 }
 
 declare void @use1(i1)
 
 ; (X & 8) == 0 ? -3 : -11 --> (X & 8) ^ -3
 ; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
 
 define i32 @clear_to_set(i32 %x) {
 ; CHECK-LABEL: @clear_to_set(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 -3, i32 -11
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %x, 8
   %t2 = icmp eq i32 %t1, 0
   %t3 = select i1 %t2, i32 -3, i32 -11
   call void @use1(i1 %t2)
   ret i32 %t3
 }
 
 ; (X & 8) == 0 ? -11 : -3 --> (X & 8) | -11
 ; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
 
 define i32 @clear_to_clear(i32 %x) {
 ; CHECK-LABEL: @clear_to_clear(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T1]], -11
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i32 -11, i32 -3
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
   %t1 = and i32 %x, 8
   %t2 = icmp eq i32 %t1, 0
   %t3 = select i1 %t2, i32 -11, i32 -3
   call void @use1(i1 %t2)
   ret i32 %t3
 }
 

 
 ; (X & 8) != 0 ? -3 : -11 --> (X & 8) ^ -3
 ; Extra cmp use ensures that cmp predicate canonicalization is thwarted.
 
 define i32 @set_to_clear(i32 %x) {
 ; CHECK-LABEL: @set_to_clear(
 ; CHECK-NEXT:    [[T1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[T1]], -11
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %t1 = and i32 %x, 8
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 -11, i32 -3
   call void @use1(i1 %t2)
   ret i32 %t3
 }
 
 ; (X & 128) == 0 ? 131 : 3 --> (X & 128) ^ 131
 
 define i8 @clear_to_set_decomposebittest(i8 %x) {
 ; CHECK-LABEL: @clear_to_set_decomposebittest(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], -125
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp sgt i8 %x, -1
   %t3 = select i1 %t2, i8 131, i8 3
   ret i8 %t3
 }
 
 ; (X & 128) == 0 ? 3 : 131 --> (X & 128) | 3
 
 define i8 @clear_to_clear_decomposebittest(i8 %x) {
 ; CHECK-LABEL: @clear_to_clear_decomposebittest(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 3
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp sgt i8 %x, -1
   %t3 = select i1 %t2, i8 3, i8 131
   ret i8 %t3
 }
 
 ; (X & 128) != 0 ? 131 : 3 --> (X & 128) | 3
 
 define i8 @set_to_set_decomposebittest(i8 %x) {
 ; CHECK-LABEL: @set_to_set_decomposebittest(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 3
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp slt i8 %x, 0
   %t3 = select i1 %t2, i8 131, i8 3
   ret i8 %t3
 }
 
 ; (X & 128) != 0 ? 3 : 131 --> (X & 128) ^ 131
 
 define i8 @set_to_clear_decomposebittest(i8 %x) {
 ; CHECK-LABEL: @set_to_clear_decomposebittest(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], -125
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp slt i8 %x, 0
   %t3 = select i1 %t2, i8 3, i8 131
   ret i8 %t3
 }
 
 ; (X & 128) == 0 ? 131 : 3 --> (X & 128) ^ 131
 ; Extra cmp use to verify that we are not creating extra instructions.
 
 define i8 @clear_to_set_decomposebittest_extra_use(i8 %x) {
 ; CHECK-LABEL: @clear_to_set_decomposebittest_extra_use(
 ; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], -125
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp sgt i8 %x, -1
   %t3 = select i1 %t2, i8 131, i8 3
   call void @use1(i1 %t2)
   ret i8 %t3
 }
 
 ; (X & 128) == 0 ? 3 : 131 --> (X & 128) | 3
 ; Extra cmp use to verify that we are not creating extra instructions.
 
 define i8 @clear_to_clear_decomposebittest_extra_use(i8 %x) {
 ; CHECK-LABEL: @clear_to_clear_decomposebittest_extra_use(
 ; CHECK-NEXT:    [[T2:%.*]] = icmp sgt i8 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp sgt i8 %x, -1
   %t3 = select i1 %t2, i8 3, i8 131
   call void @use1(i1 %t2)
   ret i8 %t3
 }
 
 ; (X & 128) != 0 ? 131 : 3 --> (X & 128) | 3
 ; Extra cmp use to verify that we are not creating extra instructions.
 
 define i8 @set_to_set_decomposebittest_extra_use(i8 %x) {
 ; CHECK-LABEL: @set_to_set_decomposebittest_extra_use(
 ; CHECK-NEXT:    [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 -125, i8 3
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp slt i8 %x, 0
   %t3 = select i1 %t2, i8 131, i8 3
   call void @use1(i1 %t2)
   ret i8 %t3
 }
 
 ; (X & 128) != 0 ? 3 : 131 --> (X & 128) ^ 131
 ; Extra cmp use to verify that we are not creating extra instructions.
 
 define i8 @set_to_clear_decomposebittest_extra_use(i8 %x) {
 ; CHECK-LABEL: @set_to_clear_decomposebittest_extra_use(
 ; CHECK-NEXT:    [[T2:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X]], -128
-; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], -125
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T2]], i8 3, i8 -125
 ; CHECK-NEXT:    call void @use1(i1 [[T2]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t2 = icmp slt i8 %x, 0
   %t3 = select i1 %t2, i8 3, i8 131
   call void @use1(i1 %t2)
   ret i8 %t3
 }
 

test/Transforms/InstCombine/unrecognized_three-way-comparison.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; Various patterns of three-ways comparison that are not currently recognized.
 
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
 declare void @foo(i32 %x)
 
 define i32 @compare_against_arbitrary_value(i32 %x, i32 %c) {
 ; TODO: We can prove that if %x s> %c then %x != c, so there should be no actual
 ;       calculations in callfoo block. @foo can be invoked with 1. We only do it
 ;       for constants that are not 0 currently while it could be generalized.
 ; CHECK-LABEL: @compare_against_arbitrary_value(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[X:%.*]], [[C:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[X]], [[C]]
 ; CHECK-NEXT:    [[SELECT2:%.*]] = zext i1 [[CMP1]] to i32
 ; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])

 
 exit:
   ret i32 42
 }
 
 define i32 @compare_against_zero(i32 %x) {
 ; CHECK-LABEL: @compare_against_zero(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr i32 [[X]], 31
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[TMP0]], 1
-; CHECK-NEXT:    [[SELECT2:%.*]] = select i1 [[CMP1]], i32 0, i32 [[TMP1]]
-; CHECK-NEXT:    [[COND:%.*]] = icmp sgt i32 [[SELECT2]], 0
-; CHECK-NEXT:    br i1 [[COND]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
-; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])
+; CHECK-NEXT:    call void @foo(i32 1)
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 42
 ;
 
 entry:
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp slt i32 %x, 0

 
 exit:
   ret i32 42
 }
 
 define i32 @compare_against_zero_non_idiomatic_add(i32 %x) {
 ; CHECK-LABEL: @compare_against_zero_non_idiomatic_add(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr i32 [[X]], 31
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], -431
-; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], 425
-; CHECK-NEXT:    [[SELECT2:%.*]] = select i1 [[CMP1]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[COND:%.*]] = icmp sgt i32 [[SELECT2]], 0
-; CHECK-NEXT:    br i1 [[COND]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
-; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])
+; CHECK-NEXT:    call void @foo(i32 425)
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 42
 ;
 
 entry:
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp slt i32 %x, 0

 
 exit:
   ret i32 42
 }
 
 define i32 @compare_against_zero_non_idiomatic_or(i32 %x) {
 ; CHECK-LABEL: @compare_against_zero_non_idiomatic_or(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = ashr i32 [[X]], 31
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], -430
-; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], 425
-; CHECK-NEXT:    [[SELECT2:%.*]] = select i1 [[CMP1]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[COND:%.*]] = icmp sgt i32 [[SELECT2]], 0
-; CHECK-NEXT:    br i1 [[COND]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
-; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])
+; CHECK-NEXT:    call void @foo(i32 425)
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 42
 ;
 
 entry:
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp slt i32 %x, 0

 
 exit:
   ret i32 42
 }
 
 define i32 @compare_against_zero_type_mismatch_idiomatic(i64 %x) {
 ; CHECK-LABEL: @compare_against_zero_type_mismatch_idiomatic(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = lshr i64 [[X]], 62
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = add nsw i32 [[TMP3]], -1
-; CHECK-NEXT:    [[SELECT2:%.*]] = select i1 [[CMP1]], i32 0, i32 [[TMP4]]
-; CHECK-NEXT:    [[COND:%.*]] = icmp sgt i32 [[SELECT2]], 0
-; CHECK-NEXT:    br i1 [[COND]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i64 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
-; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])
+; CHECK-NEXT:    call void @foo(i32 1)
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 42
 ;
 
 entry:
   %cmp1 = icmp eq i64 %x, 0
   %cmp2 = icmp slt i64 %x, 0
   %select1 = select i1 %cmp2, i32 -1, i32 1
   %select2 = select i1 %cmp1, i32 0, i32 %select1
   %cond = icmp sgt i32 %select2, 0
   br i1 %cond, label %callfoo, label %exit
 
 callfoo:
   call void @foo(i32 %select2)
   br label %exit
 
 exit:
   ret i32 42
 }
 
 define i32 @compare_against_zero_type_mismatch_non_idiomatic_1(i64 %x) {
 ; CHECK-LABEL: @compare_against_zero_type_mismatch_non_idiomatic_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP0:%.*]] = lshr i64 [[X]], 60
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 8
-; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 8
-; CHECK-NEXT:    [[TMP4:%.*]] = add nsw i32 [[TMP3]], -7
-; CHECK-NEXT:    [[SELECT2:%.*]] = select i1 [[CMP1]], i32 0, i32 [[TMP4]]
-; CHECK-NEXT:    [[COND:%.*]] = icmp sgt i32 [[SELECT2]], 0
-; CHECK-NEXT:    br i1 [[COND]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i64 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[TMP0]], label [[CALLFOO:%.*]], label [[EXIT:%.*]]
 ; CHECK:       callfoo:
-; CHECK-NEXT:    call void @foo(i32 [[SELECT2]])
+; CHECK-NEXT:    call void @foo(i32 1)
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret i32 42
 ;
 
 entry:
   %cmp1 = icmp eq i64 %x, 0
   %cmp2 = icmp slt i64 %x, 0