This is an archive of the discontinued LLVM Phabricator instance.

Paths

Table of Contentst

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llvm/trunk/
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trunk/
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include/llvm/CodeGen/
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llvm/
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CodeGen/
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MachineBasicBlock.h
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MachineInstrBuilder.h
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SlotIndexes.h
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lib/
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CodeGen/
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AggressiveAntiDepBreaker.cpp
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AsmPrinter/
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AsmPrinter.cpp
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CodeViewDebug.cpp
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DbgValueHistoryCalculator.cpp
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BranchFolding.cpp
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BreakFalseDeps.cpp
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CalcSpillWeights.cpp
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CriticalAntiDepBreaker.cpp
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EarlyIfConversion.cpp
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ExecutionDomainFix.cpp
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IfConversion.cpp
2/2
InlineSpiller.cpp
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LiveIntervals.cpp
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LiveRangeShrink.cpp
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LiveVariables.cpp
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LocalStackSlotAllocation.cpp
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MachineBasicBlock.cpp
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MachineCSE.cpp
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MachineInstr.cpp
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MachineScheduler.cpp
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MachineSink.cpp
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MachineTraceMetrics.cpp
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MachineVerifier.cpp
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PHIElimination.cpp
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PeepholeOptimizer.cpp
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ReachingDefAnalysis.cpp
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RegAllocFast.cpp
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RegisterCoalescer.cpp
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RegisterPressure.cpp
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RegisterScavenging.cpp
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ScheduleDAGInstrs.cpp
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SlotIndexes.cpp
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SplitKit.cpp
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StackColoring.cpp
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StackSlotColoring.cpp
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TwoAddressInstructionPass.cpp
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Target/
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AArch64/
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AArch64ConditionalCompares.cpp
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AArch64FrameLowering.cpp
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AArch64InstrInfo.cpp
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AMDGPU/
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AMDGPUAsmPrinter.cpp
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GCNHazardRecognizer.cpp
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GCNIterativeScheduler.cpp
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GCNRegPressure.cpp
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GCNSchedStrategy.cpp
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SIDebuggerInsertNops.cpp
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SIInsertWaitcnts.cpp
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SIMachineScheduler.cpp
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SIOptimizeExecMaskingPreRA.cpp
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ARC/
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ARCInstrInfo.cpp
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ARM/
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ARMBaseInstrInfo.cpp
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ARMConstantIslandPass.cpp
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ARMHazardRecognizer.cpp
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ARMLoadStoreOptimizer.cpp
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Thumb2ITBlockPass.cpp
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Thumb2InstrInfo.cpp
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Thumb2SizeReduction.cpp
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ThumbRegisterInfo.cpp
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AVR/
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AVRInstrInfo.cpp
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BPF/
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BPFInstrInfo.cpp
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Hexagon/
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BitTracker.cpp
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HexagonAsmPrinter.cpp
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HexagonBlockRanges.cpp
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HexagonConstPropagation.cpp
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HexagonCopyToCombine.cpp
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HexagonEarlyIfConv.cpp
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HexagonGenMux.cpp
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HexagonInstrInfo.cpp
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HexagonNewValueJump.cpp
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HexagonSplitDouble.cpp
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HexagonVLIWPacketizer.cpp
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RDFGraph.cpp
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RDFLiveness.cpp
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Lanai/
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LanaiDelaySlotFiller.cpp
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LanaiInstrInfo.cpp
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LanaiMemAluCombiner.cpp
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MSP430/
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MSP430InstrInfo.cpp
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Mips/
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MipsAsmPrinter.cpp
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MipsConstantIslandPass.cpp
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MipsDelaySlotFiller.cpp
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MipsInstrInfo.cpp
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MipsLongBranch.cpp
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PowerPC/
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PPCEarlyReturn.cpp
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PPCHazardRecognizers.cpp
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PPCMIPeephole.cpp
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PPCVSXSwapRemoval.cpp
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Sparc/
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DelaySlotFiller.cpp
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SparcInstrInfo.cpp
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SystemZ/
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SystemZInstrInfo.cpp
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SystemZLongBranch.cpp
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SystemZMachineScheduler.cpp
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WebAssembly/
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WebAssemblyCFGStackify.cpp
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WebAssemblyExplicitLocals.cpp
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WebAssemblyInstrInfo.cpp
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WebAssemblyRegStackify.cpp
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X86/
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X86CallFrameOptimization.cpp
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X86CmovConversion.cpp
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X86FloatingPoint.cpp
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X86FrameLowering.cpp
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X86ISelLowering.cpp
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X86InstrInfo.cpp
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X86PadShortFunction.cpp
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XCore/
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XCoreFrameLowering.cpp
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XCoreInstrInfo.cpp

Differential D45342

[DebugInfo] Examine all uses of isDebugValue() for debug instructions.
ClosedPublic

Authored by HsiangKai on Apr 5 2018, 5:13 PM.

Download Raw Diff

Details

Reviewers

rnk
chenwj
aprantl
probinson
javed.absar

Commits

rG801bf7ebbed3: [DebugInfo] Examine all uses of isDebugValue() for debug instructions.
rL331844: [DebugInfo] Examine all uses of isDebugValue() for debug instructions.

Summary

Because we create a new kind of debug instruction, DBG_LABEL, we need to
check all passes which use isDebugValue() to check MachineInstr is debug
instruction or not. When expelling debug instructions, we should expel
both DBG_VALUE and DBG_LABEL. So, I create a new function,
isDebugInstr(), in MachineInstr to check whether the MachineInstr is
debug instruction or not.

This patch has no new test case. I have run regression test and there is
no difference in regression test.

Diff Detail

Repository: rL LLVM

Event Timeline

HsiangKai created this revision.Apr 5 2018, 5:13 PM

Herald added subscribers: jrtc27, JDevlieghere, javed.absar and 16 others. · View Herald TranscriptApr 5 2018, 5:13 PM

HsiangKai added a parent revision: D45341: [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr..Apr 5 2018, 5:15 PM

aprantl added inline comments.Apr 6 2018, 3:35 PM

include/llvm/CodeGen/MachineBasicBlock.h
893 ↗	(On Diff #141243)	It might be interesting so look at the uses and see if this shouldn't instead test for isMetaInstruction.
lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
239 ↗	(On Diff #141243)	indentation
lib/CodeGen/ScheduleDAGInstrs.cpp
768 ↗	(On Diff #141243)	LLVM usually doesn't use braces around a single statement.

Update according to review comments.

You could land a simplified implementation of isDebugInstr that only checks for DBG_VALUE first and get this in before the other dependencies.

This revision is now accepted and ready to land.Apr 11 2018, 10:04 AM

Ka-Ka added a subscriber: Ka-Ka.Apr 11 2018, 11:08 PM

Closed by commit rL331844: [DebugInfo] Examine all uses of isDebugValue() for debug instructions. (authored by shiva). · Explain WhyMay 8 2018, 7:47 PM

This revision was automatically updated to reflect the committed changes.

Herald added a reviewer: javed.absar. · View Herald TranscriptMay 8 2018, 7:47 PM

bjope added a subscriber: bjope.May 9 2018, 1:12 PM

bjope added inline comments.

llvm/trunk/lib/CodeGen/InlineSpiller.cpp
935	Isn't this is a little bit confusing? Calling buildDbgValueForSpill is probably only correct for a DBG_VALUE. So the old check for MI->isDebugValue() is probably more correct (and more future proof). And then perhaps there should be an assertion like this on line 943 instead: assert(!MI->isDebugInstr() && "Did not expect to find a use in debug instruction that isn't a DBG_VALUE")

HsiangKai marked an inline comment as done.May 9 2018, 8:08 PM

HsiangKai added inline comments.

llvm/trunk/lib/CodeGen/InlineSpiller.cpp
935	I replaced isDebugValue() by isDebugInstr() conservatively. The instructions using Reg should not be DBG_LABEL. I think your opinion is right. I will create a patch to correct it.

Create a new revision to review it.
https://reviews.llvm.org/D46739

Revision Contents

Path

Size

llvm/

trunk/

include/

llvm/

CodeGen/

MachineBasicBlock.h

6 lines

MachineInstrBuilder.h

3 lines

SlotIndexes.h

4 lines

lib/

CodeGen/

AggressiveAntiDepBreaker.cpp

2 lines

AsmPrinter/

AsmPrinter.cpp

2 lines

CodeViewDebug.cpp

6 lines

DbgValueHistoryCalculator.cpp

6 lines

BranchFolding.cpp

6 lines

BreakFalseDeps.cpp

4 lines

CalcSpillWeights.cpp

2 lines

CriticalAntiDepBreaker.cpp

4 lines

EarlyIfConversion.cpp

2 lines

ExecutionDomainFix.cpp

4 lines

18 lines

4 lines

6 lines

4 lines

4 lines

LocalStackSlotAllocation.cpp

2 lines

MachineBasicBlock.cpp

10 lines

4 lines

7 lines

8 lines

2 lines

MachineTraceMetrics.cpp

2 lines

MachineVerifier.cpp

2 lines

PHIElimination.cpp

4 lines

PeepholeOptimizer.cpp

4 lines

ReachingDefAnalysis.cpp

4 lines

RegAllocFast.cpp

3 lines

RegisterCoalescer.cpp

2 lines

RegisterPressure.cpp

6 lines

RegisterScavenging.cpp

8 lines

ScheduleDAGInstrs.cpp

9 lines

SlotIndexes.cpp

4 lines

SplitKit.cpp

2 lines

StackColoring.cpp

6 lines

StackSlotColoring.cpp

2 lines

TwoAddressInstructionPass.cpp

20 lines

Target/

AArch64/

AArch64ConditionalCompares.cpp

2 lines

AArch64FrameLowering.cpp

2 lines

AArch64InstrInfo.cpp

2 lines

AMDGPU/

AMDGPUAsmPrinter.cpp

4 lines

GCNHazardRecognizer.cpp

2 lines

GCNIterativeScheduler.cpp

8 lines

GCNRegPressure.cpp

2 lines

GCNSchedStrategy.cpp

6 lines

SIDebuggerInsertNops.cpp

4 lines

SIInsertWaitcnts.cpp

2 lines

SIMachineScheduler.cpp

2 lines

SIOptimizeExecMaskingPreRA.cpp

2 lines

ARC/

ARCInstrInfo.cpp

2 lines

ARM/

ARMBaseInstrInfo.cpp

8 lines

ARMConstantIslandPass.cpp

2 lines

ARMHazardRecognizer.cpp

4 lines

ARMLoadStoreOptimizer.cpp

16 lines

Thumb2ITBlockPass.cpp

4 lines

Thumb2InstrInfo.cpp

4 lines

Thumb2SizeReduction.cpp

2 lines

ThumbRegisterInfo.cpp

2 lines

AVR/

AVRInstrInfo.cpp

4 lines

BPF/

BPFInstrInfo.cpp

4 lines

Hexagon/

BitTracker.cpp

2 lines

HexagonAsmPrinter.cpp

2 lines

HexagonBlockRanges.cpp

4 lines

HexagonConstPropagation.cpp

8 lines

HexagonCopyToCombine.cpp

12 lines

HexagonEarlyIfConv.cpp

2 lines

HexagonGenMux.cpp

2 lines

HexagonInstrInfo.cpp

12 lines

HexagonNewValueJump.cpp

4 lines

HexagonSplitDouble.cpp

2 lines

HexagonVLIWPacketizer.cpp

2 lines

RDFGraph.cpp

2 lines

RDFLiveness.cpp

2 lines

Lanai/

LanaiDelaySlotFiller.cpp

2 lines

LanaiInstrInfo.cpp

6 lines

LanaiMemAluCombiner.cpp

2 lines

MSP430/

MSP430InstrInfo.cpp

4 lines

Mips/

MipsAsmPrinter.cpp

2 lines

MipsConstantIslandPass.cpp

2 lines

MipsDelaySlotFiller.cpp

2 lines

MipsInstrInfo.cpp

6 lines

MipsLongBranch.cpp

2 lines

PowerPC/

PPCEarlyReturn.cpp

2 lines

PPCHazardRecognizers.cpp

4 lines

PPCMIPeephole.cpp

4 lines

PPCVSXSwapRemoval.cpp

2 lines

Sparc/

DelaySlotFiller.cpp

4 lines

SparcInstrInfo.cpp

2 lines

SystemZ/

SystemZInstrInfo.cpp

4 lines

SystemZLongBranch.cpp

2 lines

SystemZMachineScheduler.cpp

2 lines

WebAssembly/

WebAssemblyCFGStackify.cpp

2 lines

WebAssemblyExplicitLocals.cpp

4 lines

WebAssemblyInstrInfo.cpp

2 lines

WebAssemblyRegStackify.cpp

4 lines

X86/

X86CallFrameOptimization.cpp

2 lines

X86CmovConversion.cpp

6 lines

2 lines

2 lines

2 lines

16 lines

X86PadShortFunction.cpp

2 lines

XCore/

XCoreFrameLowering.cpp

2 lines

XCoreInstrInfo.cpp

6 lines

Diff 145850

llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h

Show First 20 Lines • Show All 694 Lines • ▼ Show 20 Lines	#endif
/// DestA and DestB, retain other edges leading to LandingPads (currently		/// DestA and DestB, retain other edges leading to LandingPads (currently
/// there can be only one; we don't check or require that here). Note it is		/// there can be only one; we don't check or require that here). Note it is
/// possible that DestA and/or DestB are LandingPads.		/// possible that DestA and/or DestB are LandingPads.
bool CorrectExtraCFGEdges(MachineBasicBlock *DestA,		bool CorrectExtraCFGEdges(MachineBasicBlock *DestA,
MachineBasicBlock *DestB,		MachineBasicBlock *DestB,
bool IsCond);		bool IsCond);

/// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE		/// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
/// instructions. Return UnknownLoc if there is none.		/// and DBG_LABEL instructions. Return UnknownLoc if there is none.
DebugLoc findDebugLoc(instr_iterator MBBI);		DebugLoc findDebugLoc(instr_iterator MBBI);
DebugLoc findDebugLoc(iterator MBBI) {		DebugLoc findDebugLoc(iterator MBBI) {
return findDebugLoc(MBBI.getInstrIterator());		return findDebugLoc(MBBI.getInstrIterator());
}		}

/// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE		/// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE
/// instructions. Return UnknownLoc if there is none.		/// instructions. Return UnknownLoc if there is none.
DebugLoc findPrevDebugLoc(instr_iterator MBBI);		DebugLoc findPrevDebugLoc(instr_iterator MBBI);
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
};		};

/// Increment \p It until it points to a non-debug instruction or to \p End		/// Increment \p It until it points to a non-debug instruction or to \p End
/// and return the resulting iterator. This function should only be used		/// and return the resulting iterator. This function should only be used
/// MachineBasicBlock::{iterator, const_iterator, instr_iterator,		/// MachineBasicBlock::{iterator, const_iterator, instr_iterator,
/// const_instr_iterator} and the respective reverse iterators.		/// const_instr_iterator} and the respective reverse iterators.
template<typename IterT>		template<typename IterT>
inline IterT skipDebugInstructionsForward(IterT It, IterT End) {		inline IterT skipDebugInstructionsForward(IterT It, IterT End) {
while (It != End && It->isDebugValue())		while (It != End && It->isDebugInstr())
It++;		It++;
return It;		return It;
}		}

/// Decrement \p It until it points to a non-debug instruction or to \p Begin		/// Decrement \p It until it points to a non-debug instruction or to \p Begin
/// and return the resulting iterator. This function should only be used		/// and return the resulting iterator. This function should only be used
/// MachineBasicBlock::{iterator, const_iterator, instr_iterator,		/// MachineBasicBlock::{iterator, const_iterator, instr_iterator,
/// const_instr_iterator} and the respective reverse iterators.		/// const_instr_iterator} and the respective reverse iterators.
template<class IterT>		template<class IterT>
inline IterT skipDebugInstructionsBackward(IterT It, IterT Begin) {		inline IterT skipDebugInstructionsBackward(IterT It, IterT Begin) {
while (It != Begin && It->isDebugValue())		while (It != Begin && It->isDebugInstr())
It--;		It--;
return It;		return It;
}		}

} // end namespace llvm		} // end namespace llvm

#endif // LLVM_CODEGEN_MACHINEBASICBLOCK_H		#endif // LLVM_CODEGEN_MACHINEBASICBLOCK_H

llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h

Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Lines	const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
return *this;		return *this;
}		}

const MachineInstrBuilder &addMetadata(const MDNode *MD) const {		const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));		MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())		assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
: true) &&		: true) &&
"first MDNode argument of a DBG_VALUE not a variable");		"first MDNode argument of a DBG_VALUE not a variable");
		assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
		: true) &&
		"first MDNode argument of a DBG_LABEL not a label");
return *this;		return *this;
}		}

const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {		const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));		MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
return *this;		return *this;
}		}

▲ Show 20 Lines • Show All 330 Lines • Show Last 20 Lines

llvm/trunk/include/llvm/CodeGen/SlotIndexes.h

Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines	public:
/// assigned index.		/// assigned index.
/// If Late is set and there are null indexes between mi's neighboring		/// If Late is set and there are null indexes between mi's neighboring
/// instructions, create the new index after the null indexes instead of		/// instructions, create the new index after the null indexes instead of
/// before them.		/// before them.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {		SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
assert(!MI.isInsideBundle() &&		assert(!MI.isInsideBundle() &&
"Instructions inside bundles should use bundle start's slot.");		"Instructions inside bundles should use bundle start's slot.");
assert(mi2iMap.find(&MI) == mi2iMap.end() && "Instr already indexed.");		assert(mi2iMap.find(&MI) == mi2iMap.end() && "Instr already indexed.");
// Numbering DBG_VALUE instructions could cause code generation to be		// Numbering debug instructions could cause code generation to be
// affected by debug information.		// affected by debug information.
assert(!MI.isDebugValue() && "Cannot number DBG_VALUE instructions.");		assert(!MI.isDebugInstr() && "Cannot number debug instructions.");

assert(MI.getParent() != nullptr && "Instr must be added to function.");		assert(MI.getParent() != nullptr && "Instr must be added to function.");

// Get the entries where MI should be inserted.		// Get the entries where MI should be inserted.
IndexList::iterator prevItr, nextItr;		IndexList::iterator prevItr, nextItr;
if (Late) {		if (Late) {
// Insert MI's index immediately before the following instruction.		// Insert MI's index immediately before the following instruction.
nextItr = getIndexAfter(MI).listEntry()->getIterator();		nextItr = getIndexAfter(MI).listEntry()->getIterator();
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Show First 20 Lines • Show All 802 Lines • ▼ Show 20 Lines	#endif
// from the bottom up, tracking information about liveness as we go		// from the bottom up, tracking information about liveness as we go
// to help determine which registers are available.		// to help determine which registers are available.
unsigned Broken = 0;		unsigned Broken = 0;
unsigned Count = InsertPosIndex - 1;		unsigned Count = InsertPosIndex - 1;
for (MachineBasicBlock::iterator I = End, E = Begin;		for (MachineBasicBlock::iterator I = End, E = Begin;
I != E; --Count) {		I != E; --Count) {
MachineInstr &MI = *--I;		MachineInstr &MI = *--I;

if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

DEBUG(dbgs() << "Anti: ");		DEBUG(dbgs() << "Anti: ");
DEBUG(MI.dump());		DEBUG(MI.dump());

std::set<unsigned> PassthruRegs;		std::set<unsigned> PassthruRegs;
GetPassthruRegs(MI, PassthruRegs);		GetPassthruRegs(MI, PassthruRegs);

▲ Show 20 Lines • Show All 187 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Show First 20 Lines • Show All 1,053 Lines • ▼ Show 20 Lines	void AsmPrinter::EmitFunctionBody() {
bool HasAnyRealCode = false;		bool HasAnyRealCode = false;
int NumInstsInFunction = 0;		int NumInstsInFunction = 0;
for (auto &MBB : *MF) {		for (auto &MBB : *MF) {
// Print a label for the basic block.		// Print a label for the basic block.
EmitBasicBlockStart(MBB);		EmitBasicBlockStart(MBB);
for (auto &MI : MBB) {		for (auto &MI : MBB) {
// Print the assembly for the instruction.		// Print the assembly for the instruction.
if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() &&		if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() &&
!MI.isDebugValue()) {		!MI.isDebugInstr()) {
HasAnyRealCode = true;		HasAnyRealCode = true;
++NumInstsInFunction;		++NumInstsInFunction;
}		}

if (ShouldPrintDebugScopes) {		if (ShouldPrintDebugScopes) {
for (const HandlerInfo &HI : Handlers) {		for (const HandlerInfo &HI : Handlers) {
NamedRegionTimer T(HI.TimerName, HI.TimerDescription,		NamedRegionTimer T(HI.TimerName, HI.TimerDescription,
HI.TimerGroupName, HI.TimerGroupDescription,		HI.TimerGroupName, HI.TimerGroupDescription,
▲ Show 20 Lines • Show All 1,950 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

Show First 20 Lines • Show All 2,583 Lines • ▼ Show 20 Lines	void CodeViewDebug::endFunctionImpl(const MachineFunction *MF) {
CurFn->End = Asm->getFunctionEnd();		CurFn->End = Asm->getFunctionEnd();

CurFn = nullptr;		CurFn = nullptr;
}		}

void CodeViewDebug::beginInstruction(const MachineInstr *MI) {		void CodeViewDebug::beginInstruction(const MachineInstr *MI) {
DebugHandlerBase::beginInstruction(MI);		DebugHandlerBase::beginInstruction(MI);

// Ignore DBG_VALUE locations and function prologue.		// Ignore DBG_VALUE and DBG_LABEL locations and function prologue.
if (!Asm \|\| !CurFn \|\| MI->isDebugValue() \|\|		if (!Asm \|\| !CurFn \|\| MI->isDebugInstr() \|\|
MI->getFlag(MachineInstr::FrameSetup))		MI->getFlag(MachineInstr::FrameSetup))
return;		return;

// If the first instruction of a new MBB has no location, find the first		// If the first instruction of a new MBB has no location, find the first
// instruction with a location and use that.		// instruction with a location and use that.
DebugLoc DL = MI->getDebugLoc();		DebugLoc DL = MI->getDebugLoc();
if (!DL && MI->getParent() != PrevInstBB) {		if (!DL && MI->getParent() != PrevInstBB) {
for (const auto &NextMI : *MI->getParent()) {		for (const auto &NextMI : *MI->getParent()) {
if (NextMI.isDebugValue())		if (NextMI.isDebugInstr())
continue;		continue;
DL = NextMI.getDebugLoc();		DL = NextMI.getDebugLoc();
if (DL)		if (DL)
break;		break;
}		}
}		}
PrevInstBB = MI->getParent();		PrevInstBB = MI->getParent();

▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines	void llvm::calculateDbgValueHistory(const MachineFunction *MF,
BitVector ChangingRegs(TRI->getNumRegs());		BitVector ChangingRegs(TRI->getNumRegs());
collectChangingRegs(MF, TRI, ChangingRegs);		collectChangingRegs(MF, TRI, ChangingRegs);

const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();		const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();		unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
RegDescribedVarsMap RegVars;		RegDescribedVarsMap RegVars;
for (const auto &MBB : *MF) {		for (const auto &MBB : *MF) {
for (const auto &MI : MBB) {		for (const auto &MI : MBB) {
if (!MI.isDebugValue()) {		if (!MI.isDebugInstr()) {
// Not a DBG_VALUE instruction. It may clobber registers which describe		// Not a DBG_VALUE instruction. It may clobber registers which describe
// some variables.		// some variables.
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg() && MO.isDef() && MO.getReg()) {		if (MO.isReg() && MO.isDef() && MO.getReg()) {
// Ignore call instructions that claim to clobber SP. The AArch64		// Ignore call instructions that claim to clobber SP. The AArch64
// backend does this for aggregate function arguments.		// backend does this for aggregate function arguments.
if (MI.isCall() && MO.getReg() == SP)		if (MI.isCall() && MO.getReg() == SP)
continue;		continue;
Show All 19 Lines	for (const auto &MI : MBB) {
clobberRegisterUses(RegVars, I, Result, MI);		clobberRegisterUses(RegVars, I, Result, MI);
}		}
}		}
}		}
}		}
continue;		continue;
}		}

		// Skip DBG_LABEL instructions.
		if (MI.isDebugLabel())
		continue;

assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");		assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
// Use the base variable (without any DW_OP_piece expressions)		// Use the base variable (without any DW_OP_piece expressions)
// as index into History. The full variables including the		// as index into History. The full variables including the
// piece expressions are attached to the MI.		// piece expressions are attached to the MI.
const DILocalVariable *RawVar = MI.getDebugVariable();		const DILocalVariable *RawVar = MI.getDebugVariable();
assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) &&		assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
"Expected inlined-at fields to agree");		"Expected inlined-at fields to agree");
InlinedVariable Var(RawVar, MI.getDebugLoc()->getInlinedAt());		InlinedVariable Var(RawVar, MI.getDebugLoc()->getInlinedAt());
Show All 23 Lines

llvm/trunk/lib/CodeGen/BranchFolding.cpp

Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Lines	while (I1 != MBB1->begin() && I2 != MBB2->begin()) {
++TailLen;		++TailLen;
}		}
// Back past possible debugging pseudos at beginning of block. This matters		// Back past possible debugging pseudos at beginning of block. This matters
// when one block differs from the other only by whether debugging pseudos		// when one block differs from the other only by whether debugging pseudos
// are present at the beginning. (This way, the various checks later for		// are present at the beginning. (This way, the various checks later for
// I1==MBB1->begin() work as expected.)		// I1==MBB1->begin() work as expected.)
if (I1 == MBB1->begin() && I2 != MBB2->begin()) {		if (I1 == MBB1->begin() && I2 != MBB2->begin()) {
--I2;		--I2;
while (I2->isDebugValue()) {		while (I2->isDebugInstr()) {
if (I2 == MBB2->begin())		if (I2 == MBB2->begin())
return TailLen;		return TailLen;
--I2;		--I2;
}		}
++I2;		++I2;
}		}
if (I2 == MBB2->begin() && I1 != MBB1->begin()) {		if (I2 == MBB2->begin() && I1 != MBB1->begin()) {
--I1;		--I1;
while (I1->isDebugValue()) {		while (I1->isDebugInstr()) {
if (I1 == MBB1->begin())		if (I1 == MBB1->begin())
return TailLen;		return TailLen;
--I1;		--I1;
}		}
++I1;		++I1;
}		}

SkipTopCFIAndReturn:		SkipTopCFIAndReturn:
▲ Show 20 Lines • Show All 1,115 Lines • ▼ Show 20 Lines	if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 &&
// Remove redundant DBG_VALUEs first.		// Remove redundant DBG_VALUEs first.
if (PrevBB.begin() != PrevBB.end()) {		if (PrevBB.begin() != PrevBB.end()) {
MachineBasicBlock::iterator PrevBBIter = PrevBB.end();		MachineBasicBlock::iterator PrevBBIter = PrevBB.end();
--PrevBBIter;		--PrevBBIter;
MachineBasicBlock::iterator MBBIter = MBB->begin();		MachineBasicBlock::iterator MBBIter = MBB->begin();
// Check if DBG_VALUE at the end of PrevBB is identical to the		// Check if DBG_VALUE at the end of PrevBB is identical to the
// DBG_VALUE at the beginning of MBB.		// DBG_VALUE at the beginning of MBB.
while (PrevBBIter != PrevBB.begin() && MBBIter != MBB->end()		while (PrevBBIter != PrevBB.begin() && MBBIter != MBB->end()
&& PrevBBIter->isDebugValue() && MBBIter->isDebugValue()) {		&& PrevBBIter->isDebugInstr() && MBBIter->isDebugInstr()) {
if (!MBBIter->isIdenticalTo(*PrevBBIter))		if (!MBBIter->isIdenticalTo(*PrevBBIter))
break;		break;
MachineInstr &DuplicateDbg = *MBBIter;		MachineInstr &DuplicateDbg = *MBBIter;
++MBBIter; -- PrevBBIter;		++MBBIter; -- PrevBBIter;
DuplicateDbg.eraseFromParent();		DuplicateDbg.eraseFromParent();
}		}
}		}
PrevBB.splice(PrevBB.end(), MBB, MBB->begin(), MBB->end());		PrevBB.splice(PrevBB.end(), MBB, MBB->begin(), MBB->end());
▲ Show 20 Lines • Show All 633 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/BreakFalseDeps.cpp

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines	if (Pref > Clearance) {
DEBUG(dbgs() << ": Break dependency.\n");		DEBUG(dbgs() << ": Break dependency.\n");
return true;		return true;
}		}
DEBUG(dbgs() << ": OK .\n");		DEBUG(dbgs() << ": OK .\n");
return false;		return false;
}		}

void BreakFalseDeps::processDefs(MachineInstr *MI) {		void BreakFalseDeps::processDefs(MachineInstr *MI) {
assert(!MI->isDebugValue() && "Won't process debug values");		assert(!MI->isDebugInstr() && "Won't process debug values");

// Break dependence on undef uses. Do this before updating LiveRegs below.		// Break dependence on undef uses. Do this before updating LiveRegs below.
unsigned OpNum;		unsigned OpNum;
unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);		unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
if (Pref) {		if (Pref) {
bool HadTrueDependency = pickBestRegisterForUndef(MI, OpNum, Pref);		bool HadTrueDependency = pickBestRegisterForUndef(MI, OpNum, Pref);
// We don't need to bother trying to break a dependency if this		// We don't need to bother trying to break a dependency if this
// instruction has a true dependency on that register through another		// instruction has a true dependency on that register through another
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines

void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB) {		void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB) {
UndefReads.clear();		UndefReads.clear();
// If this block is not done, it makes little sense to make any decisions		// If this block is not done, it makes little sense to make any decisions
// based on clearance information. We need to make a second pass anyway,		// based on clearance information. We need to make a second pass anyway,
// and by then we'll have better information, so we can avoid doing the work		// and by then we'll have better information, so we can avoid doing the work
// to try and break dependencies now.		// to try and break dependencies now.
for (MachineInstr &MI : *MBB) {		for (MachineInstr &MI : *MBB) {
if (!MI.isDebugValue())		if (!MI.isDebugInstr())
processDefs(&MI);		processDefs(&MI);
}		}
processUndefReads(MBB);		processUndefReads(MBB);
}		}

bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {		bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(mf.getFunction()))		if (skipFunction(mf.getFunction()))
return false;		return false;
Show All 16 Lines

llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines	for (MachineRegisterInfo::reg_instr_iterator

// For local split artifacts, we are interested only in instructions between		// For local split artifacts, we are interested only in instructions between
// the expected start and end of the range.		// the expected start and end of the range.
SlotIndex si = LIS.getInstructionIndex(*mi);		SlotIndex si = LIS.getInstructionIndex(*mi);
if (localSplitArtifact && ((si < start) \|\| (si > end)))		if (localSplitArtifact && ((si < start) \|\| (si > end)))
continue;		continue;

numInstr++;		numInstr++;
if (mi->isIdentityCopy() \|\| mi->isImplicitDef() \|\| mi->isDebugValue())		if (mi->isIdentityCopy() \|\| mi->isImplicitDef() \|\| mi->isDebugInstr())
continue;		continue;
if (!visited.insert(mi).second)		if (!visited.insert(mi).second)
continue;		continue;

float weight = 1.0f;		float weight = 1.0f;
if (Spillable) {		if (Spillable) {
// Get loop info for mi.		// Get loop info for mi.
if (mi->getParent() != mbb) {		if (mi->getParent() != mbb) {
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llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines	void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
unsigned InsertPosIndex) {		unsigned InsertPosIndex) {
// Kill instructions can define registers but are really nops, and there might		// Kill instructions can define registers but are really nops, and there might
// be a real definition earlier that needs to be paired with uses dominated by		// be a real definition earlier that needs to be paired with uses dominated by
// this kill.		// this kill.

// FIXME: It may be possible to remove the isKill() restriction once PR18663		// FIXME: It may be possible to remove the isKill() restriction once PR18663
// has been properly fixed. There can be value in processing kills as seen in		// has been properly fixed. There can be value in processing kills as seen in
// the AggressiveAntiDepBreaker class.		// the AggressiveAntiDepBreaker class.
if (MI.isDebugValue() \|\| MI.isKill())		if (MI.isDebugInstr() \|\| MI.isKill())
return;		return;
assert(Count < InsertPosIndex && "Instruction index out of expected range!");		assert(Count < InsertPosIndex && "Instruction index out of expected range!");

for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {		for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
if (KillIndices[Reg] != ~0u) {		if (KillIndices[Reg] != ~0u) {
// If Reg is currently live, then mark that it can't be renamed as		// If Reg is currently live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it		// we don't know the extent of its live-range anymore (now that it
// has been scheduled).		// has been scheduled).
▲ Show 20 Lines • Show All 404 Lines • ▼ Show 20 Lines	for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
MachineInstr &MI = *--I;		MachineInstr &MI = *--I;
// Kill instructions can define registers but are really nops, and there		// Kill instructions can define registers but are really nops, and there
// might be a real definition earlier that needs to be paired with uses		// might be a real definition earlier that needs to be paired with uses
// dominated by this kill.		// dominated by this kill.

// FIXME: It may be possible to remove the isKill() restriction once PR18663		// FIXME: It may be possible to remove the isKill() restriction once PR18663
// has been properly fixed. There can be value in processing kills as seen		// has been properly fixed. There can be value in processing kills as seen
// in the AggressiveAntiDepBreaker class.		// in the AggressiveAntiDepBreaker class.
if (MI.isDebugValue() \|\| MI.isKill())		if (MI.isDebugInstr() \|\| MI.isKill())
continue;		continue;

// Check if this instruction has a dependence on the critical path that		// Check if this instruction has a dependence on the critical path that
// is an anti-dependence that we may be able to break. If it is, set		// is an anti-dependence that we may be able to break. If it is, set
// AntiDepReg to the non-zero register associated with the anti-dependence.		// AntiDepReg to the non-zero register associated with the anti-dependence.
//		//
// We limit our attention to the critical path as a heuristic to avoid		// We limit our attention to the critical path as a heuristic to avoid
// breaking anti-dependence edges that aren't going to significantly		// breaking anti-dependence edges that aren't going to significantly
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines	bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
}		}

unsigned InstrCount = 0;		unsigned InstrCount = 0;

// Check all instructions, except the terminators. It is assumed that		// Check all instructions, except the terminators. It is assumed that
// terminators never have side effects or define any used register values.		// terminators never have side effects or define any used register values.
for (MachineBasicBlock::iterator I = MBB->begin(),		for (MachineBasicBlock::iterator I = MBB->begin(),
E = MBB->getFirstTerminator(); I != E; ++I) {		E = MBB->getFirstTerminator(); I != E; ++I) {
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

if (++InstrCount > BlockInstrLimit && !Stress) {		if (++InstrCount > BlockInstrLimit && !Stress) {
DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "		DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");		<< BlockInstrLimit << " instructions.\n");
return false;		return false;
}		}

▲ Show 20 Lines • Show All 611 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/ExecutionDomainFix.cpp

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines	if (DomP.first) {
else		else
visitHardInstr(MI, DomP.first);		visitHardInstr(MI, DomP.first);
}		}

return !DomP.first;		return !DomP.first;
}		}

void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {		void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
assert(!MI->isDebugValue() && "Won't process debug values");		assert(!MI->isDebugInstr() && "Won't process debug values");
const MCInstrDesc &MCID = MI->getDesc();		const MCInstrDesc &MCID = MI->getDesc();
for (unsigned i = 0,		for (unsigned i = 0,
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();		e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
i != e; ++i) {		i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);		MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg())		if (!MO.isReg())
continue;		continue;
if (MO.isUse())		if (MO.isUse())
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
void ExecutionDomainFix::processBasicBlock(		void ExecutionDomainFix::processBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {		const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
enterBasicBlock(TraversedMBB);		enterBasicBlock(TraversedMBB);
// If this block is not done, it makes little sense to make any decisions		// If this block is not done, it makes little sense to make any decisions
// based on clearance information. We need to make a second pass anyway,		// based on clearance information. We need to make a second pass anyway,
// and by then we'll have better information, so we can avoid doing the work		// and by then we'll have better information, so we can avoid doing the work
// to try and break dependencies now.		// to try and break dependencies now.
for (MachineInstr &MI : *TraversedMBB.MBB) {		for (MachineInstr &MI : *TraversedMBB.MBB) {
if (!MI.isDebugValue()) {		if (!MI.isDebugInstr()) {
bool Kill = false;		bool Kill = false;
if (TraversedMBB.PrimaryPass)		if (TraversedMBB.PrimaryPass)
Kill = visitInstr(&MI);		Kill = visitInstr(&MI);
processDefs(&MI, Kill);		processDefs(&MI, Kill);
}		}
}		}
leaveBasicBlock(TraversedMBB);		leaveBasicBlock(TraversedMBB);
}		}
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llvm/trunk/lib/CodeGen/IfConversion.cpp

Show First 20 Lines • Show All 942 Lines • ▼ Show 20 Lines	void IfConverter::ScanInstructions(BBInfo &BBI,

bool AlreadyPredicated = !BBI.Predicate.empty();		bool AlreadyPredicated = !BBI.Predicate.empty();

BBI.NonPredSize = 0;		BBI.NonPredSize = 0;
BBI.ExtraCost = 0;		BBI.ExtraCost = 0;
BBI.ExtraCost2 = 0;		BBI.ExtraCost2 = 0;
BBI.ClobbersPred = false;		BBI.ClobbersPred = false;
for (MachineInstr &MI : make_range(Begin, End)) {		for (MachineInstr &MI : make_range(Begin, End)) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

// It's unsafe to duplicate convergent instructions in this context, so set		// It's unsafe to duplicate convergent instructions in this context, so set
// BBI.CannotBeCopied to true if MI is convergent. To see why, consider the		// BBI.CannotBeCopied to true if MI is convergent. To see why, consider the
// following CFG, which is subject to our "simple" transformation.		// following CFG, which is subject to our "simple" transformation.
//		//
// BB0 // if (c1) goto BB1; else goto BB2;		// BB0 // if (c1) goto BB1; else goto BB2;
// / \		// / \
▲ Show 20 Lines • Show All 761 Lines • ▼ Show 20 Lines	bool IfConverter::IfConvertDiamondCommon(
BBI2->NonPredSize -= NumDups1;		BBI2->NonPredSize -= NumDups1;

// Skip past the dups on each side separately since there may be		// Skip past the dups on each side separately since there may be
// differing dbg_value entries. NumDups1 can include a "return"		// differing dbg_value entries. NumDups1 can include a "return"
// instruction, if it's not marked as "branch".		// instruction, if it's not marked as "branch".
for (unsigned i = 0; i < NumDups1; ++DI1) {		for (unsigned i = 0; i < NumDups1; ++DI1) {
if (DI1 == MBB1.end())		if (DI1 == MBB1.end())
break;		break;
if (!DI1->isDebugValue())		if (!DI1->isDebugInstr())
++i;		++i;
}		}
while (NumDups1 != 0) {		while (NumDups1 != 0) {
++DI2;		++DI2;
if (DI2 == MBB2.end())		if (DI2 == MBB2.end())
break;		break;
if (!DI2->isDebugValue())		if (!DI2->isDebugInstr())
--NumDups1;		--NumDups1;
}		}

if (MRI->tracksLiveness()) {		if (MRI->tracksLiveness()) {
for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {		for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Dummy;		SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Dummy;
Redefs.stepForward(MI, Dummy);		Redefs.stepForward(MI, Dummy);
}		}
Show All 17 Lines	#endif
// Remove duplicated instructions.		// Remove duplicated instructions.
DI1 = MBB1.end();		DI1 = MBB1.end();
for (unsigned i = 0; i != NumDups2; ) {		for (unsigned i = 0; i != NumDups2; ) {
// NumDups2 only counted non-dbg_value instructions, so this won't		// NumDups2 only counted non-dbg_value instructions, so this won't
// run off the head of the list.		// run off the head of the list.
assert(DI1 != MBB1.begin());		assert(DI1 != MBB1.begin());
--DI1;		--DI1;
// skip dbg_value instructions		// skip dbg_value instructions
if (!DI1->isDebugValue())		if (!DI1->isDebugInstr())
++i;		++i;
}		}
MBB1.erase(DI1, MBB1.end());		MBB1.erase(DI1, MBB1.end());

DI2 = BBI2->BB->end();		DI2 = BBI2->BB->end();
// The branches have been checked to match. Skip over the branch in the false		// The branches have been checked to match. Skip over the branch in the false
// block so that we don't try to predicate it.		// block so that we don't try to predicate it.
if (RemoveBranch)		if (RemoveBranch)
BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB);		BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB);
else {		else {
// Make DI2 point to the end of the range where the common "tail"		// Make DI2 point to the end of the range where the common "tail"
// instructions could be found.		// instructions could be found.
while (DI2 != MBB2.begin()) {		while (DI2 != MBB2.begin()) {
MachineBasicBlock::iterator Prev = std::prev(DI2);		MachineBasicBlock::iterator Prev = std::prev(DI2);
if (!Prev->isBranch() && !Prev->isDebugValue())		if (!Prev->isBranch() && !Prev->isDebugInstr())
break;		break;
DI2 = Prev;		DI2 = Prev;
}		}
}		}
while (NumDups2 != 0) {		while (NumDups2 != 0) {
// NumDups2 only counted non-dbg_value instructions, so this won't		// NumDups2 only counted non-dbg_value instructions, so this won't
// run off the head of the list.		// run off the head of the list.
assert(DI2 != MBB2.begin());		assert(DI2 != MBB2.begin());
--DI2;		--DI2;
// skip dbg_value instructions		// skip dbg_value instructions
if (!DI2->isDebugValue())		if (!DI2->isDebugInstr())
--NumDups2;		--NumDups2;
}		}

// Remember which registers would later be defined by the false block.		// Remember which registers would later be defined by the false block.
// This allows us not to predicate instructions in the true block that would		// This allows us not to predicate instructions in the true block that would
// later be re-defined. That is, rather than		// later be re-defined. That is, rather than
// subeq r0, r1, #1		// subeq r0, r1, #1
// addne r0, r1, #1		// addne r0, r1, #1
// generate:		// generate:
// sub r0, r1, #1		// sub r0, r1, #1
// addne r0, r1, #1		// addne r0, r1, #1
SmallSet<unsigned, 4> RedefsByFalse;		SmallSet<unsigned, 4> RedefsByFalse;
SmallSet<unsigned, 4> ExtUses;		SmallSet<unsigned, 4> ExtUses;
if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {		if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {		for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
if (FI.isDebugValue())		if (FI.isDebugInstr())
continue;		continue;
SmallVector<unsigned, 4> Defs;		SmallVector<unsigned, 4> Defs;
for (const MachineOperand &MO : FI.operands()) {		for (const MachineOperand &MO : FI.operands()) {
if (!MO.isReg())		if (!MO.isReg())
continue;		continue;
unsigned Reg = MO.getReg();		unsigned Reg = MO.getReg();
if (!Reg)		if (!Reg)
continue;		continue;
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines
/// the specified condition.		/// the specified condition.
void IfConverter::PredicateBlock(BBInfo &BBI,		void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E,		MachineBasicBlock::iterator E,
SmallVectorImpl<MachineOperand> &Cond,		SmallVectorImpl<MachineOperand> &Cond,
SmallSet<unsigned, 4> *LaterRedefs) {		SmallSet<unsigned, 4> *LaterRedefs) {
bool AnyUnpred = false;		bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;		bool MaySpec = LaterRedefs != nullptr;
for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {		for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {
if (I.isDebugValue() \|\| TII->isPredicated(I))		if (I.isDebugInstr() \|\| TII->isPredicated(I))
continue;		continue;
// It may be possible not to predicate an instruction if it's the 'true'		// It may be possible not to predicate an instruction if it's the 'true'
// side of a diamond and the 'false' side may re-define the instruction's		// side of a diamond and the 'false' side may re-define the instruction's
// defs.		// defs.
if (MaySpec && MaySpeculate(I, *LaterRedefs)) {		if (MaySpec && MaySpeculate(I, *LaterRedefs)) {
AnyUnpred = true;		AnyUnpred = true;
continue;		continue;
}		}
Show All 39 Lines	for (MachineInstr &I : FromMBB) {
ToBBI.BB->insert(ToBBI.BB->end(), MI);		ToBBI.BB->insert(ToBBI.BB->end(), MI);
ToBBI.NonPredSize++;		ToBBI.NonPredSize++;
unsigned ExtraPredCost = TII->getPredicationCost(I);		unsigned ExtraPredCost = TII->getPredicationCost(I);
unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);		unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
if (NumCycles > 1)		if (NumCycles > 1)
ToBBI.ExtraCost += NumCycles-1;		ToBBI.ExtraCost += NumCycles-1;
ToBBI.ExtraCost2 += ExtraPredCost;		ToBBI.ExtraCost2 += ExtraPredCost;

if (!TII->isPredicated(I) && !MI->isDebugValue()) {		if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
if (!TII->PredicateInstruction(*MI, Cond)) {		if (!TII->PredicateInstruction(*MI, Cond)) {
#ifndef NDEBUG		#ifndef NDEBUG
dbgs() << "Unable to predicate " << I << "!\n";		dbgs() << "Unable to predicate " << I << "!\n";
#endif		#endif
llvm_unreachable(nullptr);		llvm_unreachable(nullptr);
}		}
}		}

▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Show First 20 Lines • Show All 611 Lines • ▼ Show 20 Lines	void InlineSpiller::reMaterializeAll() {
for (unsigned Reg : RegsToSpill) {		for (unsigned Reg : RegsToSpill) {
LiveInterval &LI = LIS.getInterval(Reg);		LiveInterval &LI = LIS.getInterval(Reg);
for (MachineRegisterInfo::reg_bundle_iterator		for (MachineRegisterInfo::reg_bundle_iterator
RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();		RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
RegI != E; ) {		RegI != E; ) {
MachineInstr &MI = *RegI++;		MachineInstr &MI = *RegI++;

// Debug values are not allowed to affect codegen.		// Debug values are not allowed to affect codegen.
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

anyRemat \|= reMaterializeFor(LI, MI);		anyRemat \|= reMaterializeFor(LI, MI);
}		}
}		}
if (!anyRemat)		if (!anyRemat)
return;		return;

▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Lines	void InlineSpiller::spillAroundUses(unsigned Reg) {

// Iterate over instructions using Reg.		// Iterate over instructions using Reg.
for (MachineRegisterInfo::reg_bundle_iterator		for (MachineRegisterInfo::reg_bundle_iterator
RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();		RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
RegI != E; ) {		RegI != E; ) {
MachineInstr MI = &(RegI++);		MachineInstr MI = &(RegI++);

// Debug values are not allowed to affect codegen.		// Debug values are not allowed to affect codegen.
if (MI->isDebugValue()) {		if (MI->isDebugInstr()) {
		bjopeUnsubmitted Done Reply Inline Actions Isn't this is a little bit confusing? Calling buildDbgValueForSpill is probably only correct for a DBG_VALUE. So the old check for MI->isDebugValue() is probably more correct (and more future proof). And then perhaps there should be an assertion like this on line 943 instead: assert(!MI->isDebugInstr() && "Did not expect to find a use in debug instruction that isn't a DBG_VALUE") bjope: Isn't this is a little bit confusing? Calling buildDbgValueForSpill is probably only correct…
		HsiangKaiAuthorUnsubmitted Done Reply Inline Actions I replaced isDebugValue() by isDebugInstr() conservatively. The instructions using Reg should not be DBG_LABEL. I think your opinion is right. I will create a patch to correct it. HsiangKai: I replaced isDebugValue() by isDebugInstr() conservatively. The instructions using Reg should…
// Modify DBG_VALUE now that the value is in a spill slot.		// Modify DBG_VALUE now that the value is in a spill slot.
MachineBasicBlock *MBB = MI->getParent();		MachineBasicBlock *MBB = MI->getParent();
DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);		DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
buildDbgValueForSpill(MBB, MI, MI, StackSlot);		buildDbgValueForSpill(MBB, MI, MI, StackSlot);
MBB->erase(MI);		MBB->erase(MI);
continue;		continue;
}		}

▲ Show 20 Lines • Show All 556 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveIntervals.cpp

Show First 20 Lines • Show All 1,385 Lines • ▼ Show 20 Lines	SlotIndex findLastUseBefore(SlotIndex Before, unsigned Reg,
MachineBasicBlock::iterator MII = MBB->end();		MachineBasicBlock::iterator MII = MBB->end();
if (MachineInstr *MI = Indexes->getInstructionFromIndex(		if (MachineInstr *MI = Indexes->getInstructionFromIndex(
Indexes->getNextNonNullIndex(OldIdx)))		Indexes->getNextNonNullIndex(OldIdx)))
if (MI->getParent() == MBB)		if (MI->getParent() == MBB)
MII = MI;		MII = MI;

MachineBasicBlock::iterator Begin = MBB->begin();		MachineBasicBlock::iterator Begin = MBB->begin();
while (MII != Begin) {		while (MII != Begin) {
if ((--MII)->isDebugValue())		if ((--MII)->isDebugInstr())
continue;		continue;
SlotIndex Idx = Indexes->getInstructionIndex(*MII);		SlotIndex Idx = Indexes->getInstructionIndex(*MII);

// Stop searching when Before is reached.		// Stop searching when Before is reached.
if (!SlotIndex::isEarlierInstr(Before, Idx))		if (!SlotIndex::isEarlierInstr(Before, Idx))
return Before;		return Before;

// Check if MII uses Reg.		// Check if MII uses Reg.
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines	void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
if (LII != LR.end() && LII->start < endIdx)		if (LII != LR.end() && LII->start < endIdx)
lastUseIdx = LII->end;		lastUseIdx = LII->end;
else		else
--LII;		--LII;

for (MachineBasicBlock::iterator I = End; I != Begin;) {		for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;		--I;
MachineInstr &MI = *I;		MachineInstr &MI = *I;
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

SlotIndex instrIdx = getInstructionIndex(MI);		SlotIndex instrIdx = getInstructionIndex(MI);
bool isStartValid = getInstructionFromIndex(LII->start);		bool isStartValid = getInstructionFromIndex(LII->start);
bool isEndValid = getInstructionFromIndex(LII->end);		bool isEndValid = getInstructionFromIndex(LII->end);

// FIXME: This doesn't currently handle early-clobber or multiple removed		// FIXME: This doesn't currently handle early-clobber or multiple removed
// defs inside of the region to repair.		// defs inside of the region to repair.
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines	LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
else		else
endIdx = getInstructionIndex(*End);		endIdx = getInstructionIndex(*End);

Indexes->repairIndexesInRange(MBB, Begin, End);		Indexes->repairIndexesInRange(MBB, Begin, End);

for (MachineBasicBlock::iterator I = End; I != Begin;) {		for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;		--I;
MachineInstr &MI = *I;		MachineInstr &MI = *I;
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),		for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
MOE = MI.operands_end();		MOE = MI.operands_end();
MOI != MOE; ++MOI) {		MOI != MOE; ++MOI) {
if (MOI->isReg() &&		if (MOI->isReg() &&
TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&		TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
!hasInterval(MOI->getReg())) {		!hasInterval(MOI->getReg())) {
createAndComputeVirtRegInterval(MOI->getReg());		createAndComputeVirtRegInterval(MOI->getReg());
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines	if (MBB.empty())
continue;		continue;
bool SawStore = false;		bool SawStore = false;
BuildInstOrderMap(MBB.begin(), IOM);		BuildInstOrderMap(MBB.begin(), IOM);
UseMap.clear();		UseMap.clear();

for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {		for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
MachineInstr &MI = *Next;		MachineInstr &MI = *Next;
++Next;		++Next;
if (MI.isPHI() \|\| MI.isDebugValue())		if (MI.isPHI() \|\| MI.isDebugInstr())
continue;		continue;
if (MI.mayStore())		if (MI.mayStore())
SawStore = true;		SawStore = true;

unsigned CurrentOrder = IOM[&MI];		unsigned CurrentOrder = IOM[&MI];
unsigned Barrier = 0;		unsigned Barrier = 0;
MachineInstr *BarrierMI = nullptr;		MachineInstr *BarrierMI = nullptr;
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines	for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
if (I == BarrierMI) {		if (I == BarrierMI) {
Insert = nullptr;		Insert = nullptr;
break;		break;
}		}
// Move the instruction when # of shrunk live range > 1.		// Move the instruction when # of shrunk live range > 1.
if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {		if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
MachineBasicBlock::iterator I = std::next(Insert->getIterator());		MachineBasicBlock::iterator I = std::next(Insert->getIterator());
// Skip all the PHI and debug instructions.		// Skip all the PHI and debug instructions.
while (I != MBB.end() && (I->isPHI() \|\| I->isDebugValue()))		while (I != MBB.end() && (I->isPHI() \|\| I->isDebugInstr()))
I = std::next(I);		I = std::next(I);
if (I == MI.getIterator())		if (I == MI.getIterator())
continue;		continue;

// Update the dominator order to be the same as the insertion point.		// Update the dominator order to be the same as the insertion point.
// We do this to maintain a non-decreasing order without need to update		// We do this to maintain a non-decreasing order without need to update
// all instruction orders after the insertion point.		// all instruction orders after the insertion point.
unsigned NewOrder = IOM[&*I];		unsigned NewOrder = IOM[&*I];
Show All 17 Lines

llvm/trunk/lib/CodeGen/LiveVariables.cpp

Show First 20 Lines • Show All 493 Lines • ▼ Show 20 Lines	for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);
PhysRegDef[SubReg] = &MI;		PhysRegDef[SubReg] = &MI;
PhysRegUse[SubReg] = nullptr;		PhysRegUse[SubReg] = nullptr;
}		}
}		}
}		}

void LiveVariables::runOnInstr(MachineInstr &MI,		void LiveVariables::runOnInstr(MachineInstr &MI,
SmallVectorImpl<unsigned> &Defs) {		SmallVectorImpl<unsigned> &Defs) {
assert(!MI.isDebugValue());		assert(!MI.isDebugInstr());
// Process all of the operands of the instruction...		// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI.getNumOperands();		unsigned NumOperandsToProcess = MI.getNumOperands();

// Unless it is a PHI node. In this case, ONLY process the DEF, not any		// Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks.		// of the uses. They will be handled in other basic blocks.
if (MI.isPHI())		if (MI.isPHI())
NumOperandsToProcess = 1;		NumOperandsToProcess = 1;

▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	assert(TargetRegisterInfo::isPhysicalRegister(LI.PhysReg) &&
"Cannot have a live-in virtual register!");		"Cannot have a live-in virtual register!");
HandlePhysRegDef(LI.PhysReg, nullptr, Defs);		HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
}		}

// Loop over all of the instructions, processing them.		// Loop over all of the instructions, processing them.
DistanceMap.clear();		DistanceMap.clear();
unsigned Dist = 0;		unsigned Dist = 0;
for (MachineInstr &MI : *MBB) {		for (MachineInstr &MI : *MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
DistanceMap.insert(std::make_pair(&MI, Dist++));		DistanceMap.insert(std::make_pair(&MI, Dist++));

runOnInstr(MI, Defs);		runOnInstr(MI, Defs);
}		}

// Handle any virtual assignments from PHI nodes which might be at the		// Handle any virtual assignments from PHI nodes which might be at the
// bottom of this basic block. We check all of our successor blocks to see		// bottom of this basic block. We check all of our successor blocks to see
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp

Show First 20 Lines • Show All 298 Lines • ▼ Show 20 Lines	bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
SmallVector<FrameRef, 64> FrameReferenceInsns;		SmallVector<FrameRef, 64> FrameReferenceInsns;

unsigned Order = 0;		unsigned Order = 0;

for (MachineBasicBlock &BB : Fn) {		for (MachineBasicBlock &BB : Fn) {
for (MachineInstr &MI : BB) {		for (MachineInstr &MI : BB) {
// Debug value, stackmap and patchpoint instructions can't be out of		// Debug value, stackmap and patchpoint instructions can't be out of
// range, so they don't need any updates.		// range, so they don't need any updates.
if (MI.isDebugValue() \|\| MI.getOpcode() == TargetOpcode::STATEPOINT \|\|		if (MI.isDebugInstr() \|\| MI.getOpcode() == TargetOpcode::STATEPOINT \|\|
MI.getOpcode() == TargetOpcode::STACKMAP \|\|		MI.getOpcode() == TargetOpcode::STACKMAP \|\|
MI.getOpcode() == TargetOpcode::PATCHPOINT)		MI.getOpcode() == TargetOpcode::PATCHPOINT)
continue;		continue;

// For now, allocate the base register(s) within the basic block		// For now, allocate the base register(s) within the basic block
// where they're used, and don't try to keep them around outside		// where they're used, and don't try to keep them around outside
// of that. It may be beneficial to try sharing them more broadly		// of that. It may be beneficial to try sharing them more broadly
// than that, but the increased register pressure makes that a		// than that, but the increased register pressure makes that a
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines	MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
return I;		return I;
}		}

MachineBasicBlock::iterator		MachineBasicBlock::iterator
MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) {		MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) {
const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();		const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();

iterator E = end();		iterator E = end();
while (I != E && (I->isPHI() \|\| I->isPosition() \|\| I->isDebugValue() \|\|		while (I != E && (I->isPHI() \|\| I->isPosition() \|\| I->isDebugInstr() \|\|
TII->isBasicBlockPrologue(*I)))		TII->isBasicBlockPrologue(*I)))
++I;		++I;
// FIXME: This needs to change if we wish to bundle labels / dbg_values		// FIXME: This needs to change if we wish to bundle labels / dbg_values
// inside the bundle.		// inside the bundle.
assert((I == E \|\| !I->isInsideBundle()) &&		assert((I == E \|\| !I->isInsideBundle()) &&
"First non-phi / non-label / non-debug "		"First non-phi / non-label / non-debug "
"instruction is inside a bundle!");		"instruction is inside a bundle!");
return I;		return I;
}		}

MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {		MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
iterator B = begin(), E = end(), I = E;		iterator B = begin(), E = end(), I = E;
while (I != B && ((--I)->isTerminator() \|\| I->isDebugValue()))		while (I != B && ((--I)->isTerminator() \|\| I->isDebugInstr()))
; /noop /		; /noop /
while (I != E && !I->isTerminator())		while (I != E && !I->isTerminator())
++I;		++I;
return I;		return I;
}		}

MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {		MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
instr_iterator B = instr_begin(), E = instr_end(), I = E;		instr_iterator B = instr_begin(), E = instr_end(), I = E;
while (I != B && ((--I)->isTerminator() \|\| I->isDebugValue()))		while (I != B && ((--I)->isTerminator() \|\| I->isDebugInstr()))
; /noop /		; /noop /
while (I != E && !I->isTerminator())		while (I != E && !I->isTerminator())
++I;		++I;
return I;		return I;
}		}

MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {		MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
// Skip over begin-of-block dbg_value instructions.		// Skip over begin-of-block dbg_value instructions.
return skipDebugInstructionsForward(begin(), end());		return skipDebugInstructionsForward(begin(), end());
}		}

MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {		MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
// Skip over end-of-block dbg_value instructions.		// Skip over end-of-block dbg_value instructions.
instr_iterator B = instr_begin(), I = instr_end();		instr_iterator B = instr_begin(), I = instr_end();
while (I != B) {		while (I != B) {
--I;		--I;
// Return instruction that starts a bundle.		// Return instruction that starts a bundle.
if (I->isDebugValue() \|\| I->isInsideBundle())		if (I->isDebugInstr() \|\| I->isInsideBundle())
continue;		continue;
return I;		return I;
}		}
// The block is all debug values.		// The block is all debug values.
return end();		return end();
}		}

bool MachineBasicBlock::hasEHPadSuccessor() const {		bool MachineBasicBlock::hasEHPadSuccessor() const {
▲ Show 20 Lines • Show All 1,040 Lines • ▼ Show 20 Lines
}		}

/// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE		/// Find the previous valid DebugLoc preceding MBBI, skipping and DBG_VALUE
/// instructions. Return UnknownLoc if there is none.		/// instructions. Return UnknownLoc if there is none.
DebugLoc MachineBasicBlock::findPrevDebugLoc(instr_iterator MBBI) {		DebugLoc MachineBasicBlock::findPrevDebugLoc(instr_iterator MBBI) {
if (MBBI == instr_begin()) return {};		if (MBBI == instr_begin()) return {};
// Skip debug declarations, we don't want a DebugLoc from them.		// Skip debug declarations, we don't want a DebugLoc from them.
MBBI = skipDebugInstructionsBackward(std::prev(MBBI), instr_begin());		MBBI = skipDebugInstructionsBackward(std::prev(MBBI), instr_begin());
if (!MBBI->isDebugValue()) return MBBI->getDebugLoc();		if (!MBBI->isDebugInstr()) return MBBI->getDebugLoc();
return {};		return {};
}		}

/// Find and return the merged DebugLoc of the branch instructions of the block.		/// Find and return the merged DebugLoc of the branch instructions of the block.
/// Return UnknownLoc if there is none.		/// Return UnknownLoc if there is none.
DebugLoc		DebugLoc
MachineBasicBlock::findBranchDebugLoc() {		MachineBasicBlock::findBranchDebugLoc() {
DebugLoc DL;		DebugLoc DL;
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineCSE.cpp

Show First 20 Lines • Show All 308 Lines • ▼ Show 20 Lines	if (CSMBB != MBB) {
CrossMBB = true;		CrossMBB = true;
}		}
MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);		MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
MachineBasicBlock::const_iterator E = MI;		MachineBasicBlock::const_iterator E = MI;
MachineBasicBlock::const_iterator EE = CSMBB->end();		MachineBasicBlock::const_iterator EE = CSMBB->end();
unsigned LookAheadLeft = LookAheadLimit;		unsigned LookAheadLeft = LookAheadLimit;
while (LookAheadLeft) {		while (LookAheadLeft) {
// Skip over dbg_value's.		// Skip over dbg_value's.
while (I != E && I != EE && I->isDebugValue())		while (I != E && I != EE && I->isDebugInstr())
++I;		++I;

if (I == EE) {		if (I == EE) {
assert(CrossMBB && "Reaching end-of-MBB without finding MI?");		assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
(void)CrossMBB;		(void)CrossMBB;
CrossMBB = false;		CrossMBB = false;
NonLocal = true;		NonLocal = true;
I = MBB->begin();		I = MBB->begin();
Show All 22 Lines	while (LookAheadLeft) {
++I;		++I;
}		}

return false;		return false;
}		}

bool MachineCSE::isCSECandidate(MachineInstr *MI) {		bool MachineCSE::isCSECandidate(MachineInstr *MI) {
if (MI->isPosition() \|\| MI->isPHI() \|\| MI->isImplicitDef() \|\| MI->isKill() \|\|		if (MI->isPosition() \|\| MI->isPHI() \|\| MI->isImplicitDef() \|\| MI->isKill() \|\|
MI->isInlineAsm() \|\| MI->isDebugValue())		MI->isInlineAsm() \|\| MI->isDebugInstr())
return false;		return false;

// Ignore copies.		// Ignore copies.
if (MI->isCopyLike())		if (MI->isCopyLike())
return false;		return false;

// Ignore stuff that we obviously can't move.		// Ignore stuff that we obviously can't move.
if (MI->mayStore() \|\| MI->isCall() \|\| MI->isTerminator() \|\|		if (MI->mayStore() \|\| MI->isCall() \|\| MI->isTerminator() \|\|
▲ Show 20 Lines • Show All 373 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineInstr.cpp

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Lines	if (MO.isDef()) {
}		}
} else {		} else {
if (!MO.isIdenticalTo(OMO))		if (!MO.isIdenticalTo(OMO))
return false;		return false;
if (Check == CheckKillDead && MO.isKill() != OMO.isKill())		if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
return false;		return false;
}		}
}		}
// If DebugLoc does not match then two dbg.values are not identical.		// If DebugLoc does not match then two debug instructions are not identical.
if (isDebugValue())		if (isDebugInstr())
if (getDebugLoc() && Other.getDebugLoc() &&		if (getDebugLoc() && Other.getDebugLoc() &&
getDebugLoc() != Other.getDebugLoc())		getDebugLoc() != Other.getDebugLoc())
return false;		return false;
return true;		return true;
}		}

const MachineFunction *MachineInstr::getMF() const {		const MachineFunction *MachineInstr::getMF() const {
return getParent()->getParent();		return getParent()->getParent();
▲ Show 20 Lines • Show All 490 Lines • ▼ Show 20 Lines	bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
// volatiles, but it is required for atomic loads. It is not allowed to move		// volatiles, but it is required for atomic loads. It is not allowed to move
// a load across an atomic load with Ordering > Monotonic.		// a load across an atomic load with Ordering > Monotonic.
if (mayStore() \|\| isCall() \|\| isPHI() \|\|		if (mayStore() \|\| isCall() \|\| isPHI() \|\|
(mayLoad() && hasOrderedMemoryRef())) {		(mayLoad() && hasOrderedMemoryRef())) {
SawStore = true;		SawStore = true;
return false;		return false;
}		}

if (isPosition() \|\| isDebugValue() \|\| isTerminator() \|\|		if (isPosition() \|\| isDebugInstr() \|\| isTerminator() \|\|
hasUnmodeledSideEffects())		hasUnmodeledSideEffects())
return false;		return false;

// See if this instruction does a load. If so, we have to guarantee that the		// See if this instruction does a load. If so, we have to guarantee that the
// loaded value doesn't change between the load and the its intended		// loaded value doesn't change between the load and the its intended
// destination. The check for isInvariantLoad gives the targe the chance to		// destination. The check for isInvariantLoad gives the targe the chance to
// classify the load as always returning a constant, e.g. a constant pool		// classify the load as always returning a constant, e.g. a constant pool
// load.		// load.
▲ Show 20 Lines • Show All 542 Lines • ▼ Show 20 Lines	if (auto *InlinedAt = debugLoc->getInlinedAt()) {
OS << " inlined @[ ";		OS << " inlined @[ ";
InlinedAtDL.print(OS);		InlinedAtDL.print(OS);
OS << " ]";		OS << " ]";
}		}
}		}
if (isIndirectDebugValue())		if (isIndirectDebugValue())
OS << " indirect";		OS << " indirect";
}		}
		// TODO: DBG_LABEL

if (AddNewLine)		if (AddNewLine)
OS << '\n';		OS << '\n';
}		}

bool MachineInstr::addRegisterKilled(unsigned IncomingReg,		bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo,		const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {		bool AddIfNotFound) {
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines	static cl::opt<bool> EnablePostRAMachineSched(
cl::init(true), cl::Hidden);		cl::init(true), cl::Hidden);

/// Decrement this iterator until reaching the top or a non-debug instr.		/// Decrement this iterator until reaching the top or a non-debug instr.
static MachineBasicBlock::const_iterator		static MachineBasicBlock::const_iterator
priorNonDebug(MachineBasicBlock::const_iterator I,		priorNonDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator Beg) {		MachineBasicBlock::const_iterator Beg) {
assert(I != Beg && "reached the top of the region, cannot decrement");		assert(I != Beg && "reached the top of the region, cannot decrement");
while (--I != Beg) {		while (--I != Beg) {
if (!I->isDebugValue())		if (!I->isDebugInstr())
break;		break;
}		}
return I;		return I;
}		}

/// Non-const version.		/// Non-const version.
static MachineBasicBlock::iterator		static MachineBasicBlock::iterator
priorNonDebug(MachineBasicBlock::iterator I,		priorNonDebug(MachineBasicBlock::iterator I,
MachineBasicBlock::const_iterator Beg) {		MachineBasicBlock::const_iterator Beg) {
return priorNonDebug(MachineBasicBlock::const_iterator(I), Beg)		return priorNonDebug(MachineBasicBlock::const_iterator(I), Beg)
.getNonConstIterator();		.getNonConstIterator();
}		}

/// If this iterator is a debug value, increment until reaching the End or a		/// If this iterator is a debug value, increment until reaching the End or a
/// non-debug instruction.		/// non-debug instruction.
static MachineBasicBlock::const_iterator		static MachineBasicBlock::const_iterator
nextIfDebug(MachineBasicBlock::const_iterator I,		nextIfDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator End) {		MachineBasicBlock::const_iterator End) {
for(; I != End; ++I) {		for(; I != End; ++I) {
if (!I->isDebugValue())		if (!I->isDebugInstr())
break;		break;
}		}
return I;		return I;
}		}

/// Non-const version.		/// Non-const version.
static MachineBasicBlock::iterator		static MachineBasicBlock::iterator
nextIfDebug(MachineBasicBlock::iterator I,		nextIfDebug(MachineBasicBlock::iterator I,
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines	for(MachineBasicBlock::iterator RegionEnd = MBB->end();
// The next region starts above the previous region. Look backward in the		// The next region starts above the previous region. Look backward in the
// instruction stream until we find the nearest boundary.		// instruction stream until we find the nearest boundary.
unsigned NumRegionInstrs = 0;		unsigned NumRegionInstrs = 0;
I = RegionEnd;		I = RegionEnd;
for (;I != MBB->begin(); --I) {		for (;I != MBB->begin(); --I) {
MachineInstr &MI = *std::prev(I);		MachineInstr &MI = *std::prev(I);
if (isSchedBoundary(&MI, &*MBB, MF, TII))		if (isSchedBoundary(&MI, &*MBB, MF, TII))
break;		break;
if (!MI.isDebugValue())		if (!MI.isDebugInstr())
// MBB::size() uses instr_iterator to count. Here we need a bundle to		// MBB::size() uses instr_iterator to count. Here we need a bundle to
// count as a single instruction.		// count as a single instruction.
++NumRegionInstrs;		++NumRegionInstrs;
}		}

Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));		Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
}		}

▲ Show 20 Lines • Show All 556 Lines • ▼ Show 20 Lines	void ScheduleDAGMILive::initRegPressure() {
DEBUG(		DEBUG(
dbgs() << "Top Pressure:\n";		dbgs() << "Top Pressure:\n";
dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);		dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
dbgs() << "Bottom Pressure:\n";		dbgs() << "Bottom Pressure:\n";
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);		dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);
);		);

assert((BotRPTracker.getPos() == RegionEnd \|\|		assert((BotRPTracker.getPos() == RegionEnd \|\|
(RegionEnd->isDebugValue() &&		(RegionEnd->isDebugInstr() &&
BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&		BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
"Can't find the region bottom");		"Can't find the region bottom");

// Cache the list of excess pressure sets in this region. This will also track		// Cache the list of excess pressure sets in this region. This will also track
// the max pressure in the scheduled code for these sets.		// the max pressure in the scheduled code for these sets.
RegionCriticalPSets.clear();		RegionCriticalPSets.clear();
const std::vector<unsigned> &RegionPressure =		const std::vector<unsigned> &RegionPressure =
RPTracker.getPressure().MaxSetPressure;		RPTracker.getPressure().MaxSetPressure;
▲ Show 20 Lines • Show All 2,589 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineSink.cpp

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Lines	do {
MachineInstr &MI = *I; // The instruction to sink.		MachineInstr &MI = *I; // The instruction to sink.

// Predecrement I (if it's not begin) so that it isn't invalidated by		// Predecrement I (if it's not begin) so that it isn't invalidated by
// sinking.		// sinking.
ProcessedBegin = I == MBB.begin();		ProcessedBegin = I == MBB.begin();
if (!ProcessedBegin)		if (!ProcessedBegin)
--I;		--I;

if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);		bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
if (Joined) {		if (Joined) {
MadeChange = true;		MadeChange = true;
continue;		continue;
}		}

▲ Show 20 Lines • Show All 798 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp

	Show First 20 Lines • Show All 647 Lines • ▼ Show 20 Lines
	} // end anonymous namespace			} // end anonymous namespace

	// Get the input data dependencies that must be ready before UseMI can issue.			// Get the input data dependencies that must be ready before UseMI can issue.
	// Return true if UseMI has any physreg operands.			// Return true if UseMI has any physreg operands.
	static bool getDataDeps(const MachineInstr &UseMI,			static bool getDataDeps(const MachineInstr &UseMI,
	SmallVectorImpl<DataDep> &Deps,			SmallVectorImpl<DataDep> &Deps,
	const MachineRegisterInfo *MRI) {			const MachineRegisterInfo *MRI) {
	// Debug values should not be included in any calculations.			// Debug values should not be included in any calculations.
	if (UseMI.isDebugValue())			if (UseMI.isDebugInstr())
	return false;			return false;

	bool HasPhysRegs = false;			bool HasPhysRegs = false;
	for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),			for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
	E = UseMI.operands_end(); I != E; ++I) {			E = UseMI.operands_end(); I != E; ++I) {
	const MachineOperand &MO = *I;			const MachineOperand &MO = *I;
	if (!MO.isReg())			if (!MO.isReg())
	continue;			continue;
	▲ Show 20 Lines • Show All 689 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 896 Lines • ▼ Show 20 Lines	for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
if ((*I)->isStore() && !MI->mayStore())		if ((*I)->isStore() && !MI->mayStore())
report("Missing mayStore flag", MI);		report("Missing mayStore flag", MI);
}		}

// Debug values must not have a slot index.		// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.		// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {		if (LiveInts) {
bool mapped = !LiveInts->isNotInMIMap(*MI);		bool mapped = !LiveInts->isNotInMIMap(*MI);
if (MI->isDebugValue()) {		if (MI->isDebugInstr()) {
if (mapped)		if (mapped)
report("Debug instruction has a slot index", MI);		report("Debug instruction has a slot index", MI);
} else if (MI->isInsideBundle()) {		} else if (MI->isInsideBundle()) {
if (mapped)		if (mapped)
report("Instruction inside bundle has a slot index", MI);		report("Instruction inside bundle has a slot index", MI);
} else {		} else {
if (!mapped)		if (!mapped)
report("Missing slot index", MI);		report("Missing slot index", MI);
▲ Show 20 Lines • Show All 1,426 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PHIElimination.cpp

Show First 20 Lines • Show All 446 Lines • ▼ Show 20 Lines	if (LV && !SrcUndef &&
if (KillInst == opBlock.end()) {		if (KillInst == opBlock.end()) {
// No terminator uses the register.		// No terminator uses the register.

if (reusedIncoming \|\| !IncomingReg) {		if (reusedIncoming \|\| !IncomingReg) {
// We may have to rewind a bit if we didn't insert a copy this time.		// We may have to rewind a bit if we didn't insert a copy this time.
KillInst = FirstTerm;		KillInst = FirstTerm;
while (KillInst != opBlock.begin()) {		while (KillInst != opBlock.begin()) {
--KillInst;		--KillInst;
if (KillInst->isDebugValue())		if (KillInst->isDebugInstr())
continue;		continue;
if (KillInst->readsRegister(SrcReg))		if (KillInst->readsRegister(SrcReg))
break;		break;
}		}
} else {		} else {
// We just inserted this copy.		// We just inserted this copy.
KillInst = std::prev(InsertPos);		KillInst = std::prev(InsertPos);
}		}
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines	if (LIS) {
if (KillInst == opBlock.end()) {		if (KillInst == opBlock.end()) {
// No terminator uses the register.		// No terminator uses the register.

if (reusedIncoming \|\| !IncomingReg) {		if (reusedIncoming \|\| !IncomingReg) {
// We may have to rewind a bit if we didn't just insert a copy.		// We may have to rewind a bit if we didn't just insert a copy.
KillInst = FirstTerm;		KillInst = FirstTerm;
while (KillInst != opBlock.begin()) {		while (KillInst != opBlock.begin()) {
--KillInst;		--KillInst;
if (KillInst->isDebugValue())		if (KillInst->isDebugInstr())
continue;		continue;
if (KillInst->readsRegister(SrcReg))		if (KillInst->readsRegister(SrcReg))
break;		break;
}		}
} else {		} else {
// We just inserted this copy.		// We just inserted this copy.
KillInst = std::prev(InsertPos);		KillInst = std::prev(InsertPos);
}		}
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp

Show First 20 Lines • Show All 1,637 Lines • ▼ Show 20 Lines	for (MachineBasicBlock &MBB : MF) {

for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();		for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
MII != MIE; ) {		MII != MIE; ) {
MachineInstr MI = &MII;		MachineInstr MI = &MII;
// We may be erasing MI below, increment MII now.		// We may be erasing MI below, increment MII now.
++MII;		++MII;
LocalMIs.insert(MI);		LocalMIs.insert(MI);

// Skip debug values. They should not affect this peephole optimization.		// Skip debug instructions. They should not affect this peephole optimization.
if (MI->isDebugValue())		if (MI->isDebugInstr())
continue;		continue;

if (MI->isPosition())		if (MI->isPosition())
continue;		continue;

if (IsLoopHeader && MI->isPHI()) {		if (IsLoopHeader && MI->isPHI()) {
if (optimizeRecurrence(*MI)) {		if (optimizeRecurrence(*MI)) {
Changed = true;		Changed = true;
▲ Show 20 Lines • Show All 451 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/ReachingDefAnalysis.cpp

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines	void ReachingDefAnalysis::leaveBasicBlock(
// only cares about the clearance from the end of the block, so adjust		// only cares about the clearance from the end of the block, so adjust
// everything to be relative to the end of the basic block.		// everything to be relative to the end of the basic block.
for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber])		for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber])
OutLiveReg -= CurInstr;		OutLiveReg -= CurInstr;
LiveRegs.clear();		LiveRegs.clear();
}		}

void ReachingDefAnalysis::processDefs(MachineInstr *MI) {		void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
assert(!MI->isDebugValue() && "Won't process debug values");		assert(!MI->isDebugInstr() && "Won't process debug instructions");

unsigned MBBNumber = MI->getParent()->getNumber();		unsigned MBBNumber = MI->getParent()->getNumber();
assert(MBBNumber < MBBReachingDefs.size() &&		assert(MBBNumber < MBBReachingDefs.size() &&
"Unexpected basic block number.");		"Unexpected basic block number.");
const MCInstrDesc &MCID = MI->getDesc();		const MCInstrDesc &MCID = MI->getDesc();
for (unsigned i = 0,		for (unsigned i = 0,
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();		e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
i != e; ++i) {		i != e; ++i) {
Show All 15 Lines	void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
InstIds[MI] = CurInstr;		InstIds[MI] = CurInstr;
++CurInstr;		++CurInstr;
}		}

void ReachingDefAnalysis::processBasicBlock(		void ReachingDefAnalysis::processBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {		const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
enterBasicBlock(TraversedMBB);		enterBasicBlock(TraversedMBB);
for (MachineInstr &MI : *TraversedMBB.MBB) {		for (MachineInstr &MI : *TraversedMBB.MBB) {
if (!MI.isDebugValue())		if (!MI.isDebugInstr())
processDefs(&MI);		processDefs(&MI);
}		}
leaveBasicBlock(TraversedMBB);		leaveBasicBlock(TraversedMBB);
}		}

bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {		bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(mf.getFunction()))		if (skipFunction(mf.getFunction()))
return false;		return false;
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Show First 20 Lines • Show All 904 Lines • ▼ Show 20 Lines	if (MI.isDebugValue()) {
}		}

// If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so		// If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so
// that future spills of Reg will have DBG_VALUEs.		// that future spills of Reg will have DBG_VALUEs.
LiveDbgValueMap[Reg].push_back(DebugMI);		LiveDbgValueMap[Reg].push_back(DebugMI);
continue;		continue;
}		}

		if (MI.isDebugLabel())
		continue;

// If this is a copy, we may be able to coalesce.		// If this is a copy, we may be able to coalesce.
unsigned CopySrcReg = 0;		unsigned CopySrcReg = 0;
unsigned CopyDstReg = 0;		unsigned CopyDstReg = 0;
unsigned CopySrcSub = 0;		unsigned CopySrcSub = 0;
unsigned CopyDstSub = 0;		unsigned CopyDstSub = 0;
if (MI.isCopy()) {		if (MI.isCopy()) {
CopyDstReg = MI.getOperand(0).getReg();		CopyDstReg = MI.getOperand(0).getReg();
CopySrcReg = MI.getOperand(1).getReg();		CopySrcReg = MI.getOperand(1).getReg();
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Show First 20 Lines • Show All 2,572 Lines • ▼ Show 20 Lines	do {
if (!OV.RedefVNI)		if (!OV.RedefVNI)
break;		break;
} while (TaintedLanes.any());		} while (TaintedLanes.any());
return true;		return true;
}		}

bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,		bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
LaneBitmask Lanes) const {		LaneBitmask Lanes) const {
if (MI.isDebugValue())		if (MI.isDebugInstr())
return false;		return false;
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() \|\| MO.isDef() \|\| MO.getReg() != Reg)		if (!MO.isReg() \|\| MO.isDef() \|\| MO.getReg() != Reg)
continue;		continue;
if (!MO.readsReg())		if (!MO.readsReg())
continue;		continue;
unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());		unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())		if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
▲ Show 20 Lines • Show All 831 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterPressure.cpp

	Show First 20 Lines • Show All 742 Lines • ▼ Show 20 Lines

	/// Recede across the previous instruction. If LiveUses is provided, record any			/// Recede across the previous instruction. If LiveUses is provided, record any
	/// RegUnits that are made live by the current instruction's uses. This includes			/// RegUnits that are made live by the current instruction's uses. This includes
	/// registers that are both defined and used by the instruction. If a pressure			/// registers that are both defined and used by the instruction. If a pressure
	/// difference pointer is provided record the changes is pressure caused by this			/// difference pointer is provided record the changes is pressure caused by this
	/// instruction independent of liveness.			/// instruction independent of liveness.
	void RegPressureTracker::recede(const RegisterOperands &RegOpers,			void RegPressureTracker::recede(const RegisterOperands &RegOpers,
	SmallVectorImpl<RegisterMaskPair> *LiveUses) {			SmallVectorImpl<RegisterMaskPair> *LiveUses) {
	assert(!CurrPos->isDebugValue());			assert(!CurrPos->isDebugInstr());

	// Boost pressure for all dead defs together.			// Boost pressure for all dead defs together.
	bumpDeadDefs(RegOpers.DeadDefs);			bumpDeadDefs(RegOpers.DeadDefs);

	// Kill liveness at live defs.			// Kill liveness at live defs.
	// TODO: consider earlyclobbers?			// TODO: consider earlyclobbers?
	for (const RegisterMaskPair &Def : RegOpers.Defs) {			for (const RegisterMaskPair &Def : RegOpers.Defs) {
	unsigned Reg = Def.RegUnit;			unsigned Reg = Def.RegUnit;
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines

	/// Record the upward impact of a single instruction on current register			/// Record the upward impact of a single instruction on current register
	/// pressure. Unlike the advance/recede pressure tracking interface, this does			/// pressure. Unlike the advance/recede pressure tracking interface, this does
	/// not discover live in/outs.			/// not discover live in/outs.
	///			///
	/// This is intended for speculative queries. It leaves pressure inconsistent			/// This is intended for speculative queries. It leaves pressure inconsistent
	/// with the current position, so must be restored by the caller.			/// with the current position, so must be restored by the caller.
	void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {			void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
	assert(!MI->isDebugValue() && "Expect a nondebug instruction.");			assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");

	SlotIndex SlotIdx;			SlotIndex SlotIdx;
	if (RequireIntervals)			if (RequireIntervals)
	SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();			SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();

	// Account for register pressure similar to RegPressureTracker::recede().			// Account for register pressure similar to RegPressureTracker::recede().
	RegisterOperands RegOpers;			RegisterOperands RegOpers;
	RegOpers.collect(MI, TRI, MRI, TrackLaneMasks, /IgnoreDead=*/true);			RegOpers.collect(MI, TRI, MRI, TrackLaneMasks, /IgnoreDead=*/true);
	▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines

	/// Record the downward impact of a single instruction on current register			/// Record the downward impact of a single instruction on current register
	/// pressure. Unlike the advance/recede pressure tracking interface, this does			/// pressure. Unlike the advance/recede pressure tracking interface, this does
	/// not discover live in/outs.			/// not discover live in/outs.
	///			///
	/// This is intended for speculative queries. It leaves pressure inconsistent			/// This is intended for speculative queries. It leaves pressure inconsistent
	/// with the current position, so must be restored by the caller.			/// with the current position, so must be restored by the caller.
	void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {			void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
	assert(!MI->isDebugValue() && "Expect a nondebug instruction.");			assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");

	SlotIndex SlotIdx;			SlotIndex SlotIdx;
	if (RequireIntervals)			if (RequireIntervals)
	SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();			SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();

	// Account for register pressure similar to RegPressureTracker::recede().			// Account for register pressure similar to RegPressureTracker::recede().
	RegisterOperands RegOpers;			RegisterOperands RegOpers;
	RegOpers.collect(MI, TRI, *MRI, TrackLaneMasks, false);			RegOpers.collect(MI, TRI, *MRI, TrackLaneMasks, false);
	▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines	void RegScavenger::removeRegUnits(BitVector &BV, unsigned Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)		for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.reset(*RUI);		BV.reset(*RUI);
}		}

void RegScavenger::determineKillsAndDefs() {		void RegScavenger::determineKillsAndDefs() {
assert(Tracking && "Must be tracking to determine kills and defs");		assert(Tracking && "Must be tracking to determine kills and defs");

MachineInstr &MI = *MBBI;		MachineInstr &MI = *MBBI;
assert(!MI.isDebugValue() && "Debug values have no kills or defs");		assert(!MI.isDebugInstr() && "Debug values have no kills or defs");

// Find out which registers are early clobbered, killed, defined, and marked		// Find out which registers are early clobbered, killed, defined, and marked
// def-dead in this instruction.		// def-dead in this instruction.
KillRegUnits.reset();		KillRegUnits.reset();
DefRegUnits.reset();		DefRegUnits.reset();
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
if (MO.isRegMask()) {		if (MO.isRegMask()) {
TmpRegUnits.clear();		TmpRegUnits.clear();
Show All 30 Lines	for (const MachineOperand &MO : MI.operands()) {
}		}
}		}
}		}

void RegScavenger::unprocess() {		void RegScavenger::unprocess() {
assert(Tracking && "Cannot unprocess because we're not tracking");		assert(Tracking && "Cannot unprocess because we're not tracking");

MachineInstr &MI = *MBBI;		MachineInstr &MI = *MBBI;
if (!MI.isDebugValue()) {		if (!MI.isDebugInstr()) {
determineKillsAndDefs();		determineKillsAndDefs();

// Commit the changes.		// Commit the changes.
setUsed(KillRegUnits);		setUsed(KillRegUnits);
setUnused(DefRegUnits);		setUnused(DefRegUnits);
}		}

if (MBBI == MBB->begin()) {		if (MBBI == MBB->begin()) {
Show All 20 Lines	for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
IE = Scavenged.end(); I != IE; ++I) {		IE = Scavenged.end(); I != IE; ++I) {
if (I->Restore != &MI)		if (I->Restore != &MI)
continue;		continue;

I->Reg = 0;		I->Reg = 0;
I->Restore = nullptr;		I->Restore = nullptr;
}		}

if (MI.isDebugValue())		if (MI.isDebugInstr())
return;		return;

determineKillsAndDefs();		determineKillsAndDefs();

// Verify uses and defs.		// Verify uses and defs.
#ifndef NDEBUG		#ifndef NDEBUG
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())		if (!MO.isReg())
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines	unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,

MachineBasicBlock::iterator ME = MBB->getFirstTerminator();		MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
assert(StartMI != ME && "MI already at terminator");		assert(StartMI != ME && "MI already at terminator");
MachineBasicBlock::iterator RestorePointMI = StartMI;		MachineBasicBlock::iterator RestorePointMI = StartMI;
MachineBasicBlock::iterator MI = StartMI;		MachineBasicBlock::iterator MI = StartMI;

bool inVirtLiveRange = false;		bool inVirtLiveRange = false;
for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {		for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
if (MI->isDebugValue()) {		if (MI->isDebugInstr()) {
++InstrLimit; // Don't count debug instructions		++InstrLimit; // Don't count debug instructions
continue;		continue;
}		}
bool isVirtKillInsn = false;		bool isVirtKillInsn = false;
bool isVirtDefInsn = false;		bool isVirtDefInsn = false;
// Remove any candidates touched by instruction.		// Remove any candidates touched by instruction.
for (const MachineOperand &MO : MI->operands()) {		for (const MachineOperand &MO : MI->operands()) {
if (MO.isRegMask())		if (MO.isRegMask())
▲ Show 20 Lines • Show All 478 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Show First 20 Lines • Show All 527 Lines • ▼ Show 20 Lines
/// MachineScheduler relies on initSUnits numbering the nodes by their order in		/// MachineScheduler relies on initSUnits numbering the nodes by their order in
/// the original instruction list.		/// the original instruction list.
void ScheduleDAGInstrs::initSUnits() {		void ScheduleDAGInstrs::initSUnits() {
// We'll be allocating one SUnit for each real instruction in the region,		// We'll be allocating one SUnit for each real instruction in the region,
// which is contained within a basic block.		// which is contained within a basic block.
SUnits.reserve(NumRegionInstrs);		SUnits.reserve(NumRegionInstrs);

for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {		for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

SUnit *SU = newSUnit(&MI);		SUnit *SU = newSUnit(&MI);
MISUnitMap[&MI] = SU;		MISUnitMap[&MI] = SU;

SU->isCall = MI.isCall();		SU->isCall = MI.isCall();
SU->isCommutable = MI.isCommutable();		SU->isCommutable = MI.isCommutable();

▲ Show 20 Lines • Show All 214 Lines • ▼ Show 20 Lines	if (DbgMI) {
DbgValues.push_back(std::make_pair(DbgMI, &MI));		DbgValues.push_back(std::make_pair(DbgMI, &MI));
DbgMI = nullptr;		DbgMI = nullptr;
}		}

if (MI.isDebugValue()) {		if (MI.isDebugValue()) {
DbgMI = &MI;		DbgMI = &MI;
continue;		continue;
}		}
		if (MI.isDebugLabel())
		continue;

SUnit *SU = MISUnitMap[&MI];		SUnit *SU = MISUnitMap[&MI];
assert(SU && "No SUnit mapped to this MI");		assert(SU && "No SUnit mapped to this MI");

if (RPTracker) {		if (RPTracker) {
RegisterOperands RegOpers;		RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);		RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {		if (TrackLaneMasks) {
SlotIndex SlotIdx = LIS->getInstructionIndex(MI);		SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines
void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {		void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');		DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');

LiveRegs.init(*TRI);		LiveRegs.init(*TRI);
LiveRegs.addLiveOuts(MBB);		LiveRegs.addLiveOuts(MBB);

// Examine block from end to start...		// Examine block from end to start...
for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {		for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

// Update liveness. Registers that are defed but not used in this		// Update liveness. Registers that are defed but not used in this
// instruction are now dead. Mark register and all subregs as they		// instruction are now dead. Mark register and all subregs as they
// are completely defined.		// are completely defined.
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {		for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
const MachineOperand &MO = *O;		const MachineOperand &MO = *O;
if (MO.isReg()) {		if (MO.isReg()) {
Show All 19 Lines	if (!MI.isBundled()) {
}		}
// Some targets make the (questionable) assumtion that the instructions		// Some targets make the (questionable) assumtion that the instructions
// inside the bundle are ordered and consequently only the last use of		// inside the bundle are ordered and consequently only the last use of
// a register inside the bundle can kill it.		// a register inside the bundle can kill it.
MachineBasicBlock::instr_iterator I = std::next(First);		MachineBasicBlock::instr_iterator I = std::next(First);
while (I->isBundledWithSucc())		while (I->isBundledWithSucc())
++I;		++I;
do {		do {
if (!I->isDebugValue())		if (!I->isDebugInstr())
toggleKills(MRI, LiveRegs, *I, true);		toggleKills(MRI, LiveRegs, *I, true);
--I;		--I;
} while(I != First);		} while(I != First);
}		}
}		}
}		}

void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {		void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/SlotIndexes.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines	bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
indexList.push_back(createEntry(nullptr, index));		indexList.push_back(createEntry(nullptr, index));

// Iterate over the function.		// Iterate over the function.
for (MachineBasicBlock &MBB : *mf) {		for (MachineBasicBlock &MBB : *mf) {
// Insert an index for the MBB start.		// Insert an index for the MBB start.
SlotIndex blockStartIndex(&indexList.back(), SlotIndex::Slot_Block);		SlotIndex blockStartIndex(&indexList.back(), SlotIndex::Slot_Block);

for (MachineInstr &MI : MBB) {		for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

// Insert a store index for the instr.		// Insert a store index for the instr.
indexList.push_back(createEntry(&MI, index += SlotIndex::InstrDist));		indexList.push_back(createEntry(&MI, index += SlotIndex::InstrDist));

// Save this base index in the maps.		// Save this base index in the maps.
mi2iMap.insert(std::make_pair(		mi2iMap.insert(std::make_pair(
&MI, SlotIndex(&indexList.back(), SlotIndex::Slot_Block)));		&MI, SlotIndex(&indexList.back(), SlotIndex::Slot_Block)));
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	while (ListI != ListB \|\| MBBI != Begin \|\| (includeStart && !pastStart)) {
}		}
}		}

// In theory this could be combined with the previous loop, but it is tricky		// In theory this could be combined with the previous loop, but it is tricky
// to update the IndexList while we are iterating it.		// to update the IndexList while we are iterating it.
for (MachineBasicBlock::iterator I = End; I != Begin;) {		for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;		--I;
MachineInstr &MI = *I;		MachineInstr &MI = *I;
if (!MI.isDebugValue() && mi2iMap.find(&MI) == mi2iMap.end())		if (!MI.isDebugInstr() && mi2iMap.find(&MI) == mi2iMap.end())
insertMachineInstrInMaps(MI);		insertMachineInstrInMaps(MI);
}		}
}		}

#if !defined(NDEBUG) \|\| defined(LLVM_ENABLE_DUMP)		#if !defined(NDEBUG) \|\| defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void SlotIndexes::dump() const {		LLVM_DUMP_METHOD void SlotIndexes::dump() const {
for (IndexList::const_iterator itr = indexList.begin();		for (IndexList::const_iterator itr = indexList.begin();
itr != indexList.end(); ++itr) {		itr != indexList.end(); ++itr) {
Show All 31 Lines

llvm/trunk/lib/CodeGen/SplitKit.cpp

Show First 20 Lines • Show All 854 Lines • ▼ Show 20 Lines	for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
SlotIndex Def = Copies[i]->def;		SlotIndex Def = Copies[i]->def;
MachineInstr *MI = LIS.getInstructionFromIndex(Def);		MachineInstr *MI = LIS.getInstructionFromIndex(Def);
assert(MI && "No instruction for back-copy");		assert(MI && "No instruction for back-copy");

MachineBasicBlock *MBB = MI->getParent();		MachineBasicBlock *MBB = MI->getParent();
MachineBasicBlock::iterator MBBI(MI);		MachineBasicBlock::iterator MBBI(MI);
bool AtBegin;		bool AtBegin;
do AtBegin = MBBI == MBB->begin();		do AtBegin = MBBI == MBB->begin();
while (!AtBegin && (--MBBI)->isDebugValue());		while (!AtBegin && (--MBBI)->isDebugInstr());

DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);		DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
LIS.removeVRegDefAt(*LI, Def);		LIS.removeVRegDefAt(*LI, Def);
LIS.RemoveMachineInstrFromMaps(*MI);		LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();		MI->eraseFromParent();

// Adjust RegAssign if a register assignment is killed at Def. We want to		// Adjust RegAssign if a register assignment is killed at Def. We want to
// avoid calculating the live range of the source register if possible.		// avoid calculating the live range of the source register if possible.
▲ Show 20 Lines • Show All 979 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/StackColoring.cpp

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lines	if (MI.getOpcode() == TargetOpcode::LIFETIME_END) {
isStart = false;		isStart = false;
return true;		return true;
}		}
if (!applyFirstUse(Slot)) {		if (!applyFirstUse(Slot)) {
isStart = true;		isStart = true;
return true;		return true;
}		}
} else if (LifetimeStartOnFirstUse && !ProtectFromEscapedAllocas) {		} else if (LifetimeStartOnFirstUse && !ProtectFromEscapedAllocas) {
if (!MI.isDebugValue()) {		if (!MI.isDebugInstr()) {
bool found = false;		bool found = false;
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
if (!MO.isFI())		if (!MO.isFI())
continue;		continue;
int Slot = MO.getIndex();		int Slot = MO.getIndex();
if (Slot<0)		if (Slot<0)
continue;		continue;
if (InterestingSlots.test(Slot) && applyFirstUse(Slot)) {		if (InterestingSlots.test(Slot) && applyFirstUse(Slot)) {
▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Lines	for (MachineInstr &I : BB) {
// outside of the lifetime markers, or that the user has a bug.		// outside of the lifetime markers, or that the user has a bug.
// NOTE: Alloca address calculations which happen outside the lifetime		// NOTE: Alloca address calculations which happen outside the lifetime
// zone are okay, despite the fact that we don't have a good way		// zone are okay, despite the fact that we don't have a good way
// for validating all of the usages of the calculation.		// for validating all of the usages of the calculation.
#ifndef NDEBUG		#ifndef NDEBUG
bool TouchesMemory = I.mayLoad() \|\| I.mayStore();		bool TouchesMemory = I.mayLoad() \|\| I.mayStore();
// If we don't protect the user from escaped allocas, don't bother		// If we don't protect the user from escaped allocas, don't bother
// validating the instructions.		// validating the instructions.
if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) {		if (!I.isDebugInstr() && TouchesMemory && ProtectFromEscapedAllocas) {
SlotIndex Index = Indexes->getInstructionIndex(I);		SlotIndex Index = Indexes->getInstructionIndex(I);
const LiveInterval Interval = &Intervals[FromSlot];		const LiveInterval Interval = &Intervals[FromSlot];
assert(Interval->find(Index) != Interval->end() &&		assert(Interval->find(Index) != Interval->end() &&
"Found instruction usage outside of live range.");		"Found instruction usage outside of live range.");
}		}
#endif		#endif

// Fix the machine instructions.		// Fix the machine instructions.
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	#endif
DEBUG(dbgs()<<"Fixed "<<FixedDbg<<" debug locations.\n");		DEBUG(dbgs()<<"Fixed "<<FixedDbg<<" debug locations.\n");
DEBUG(dbgs()<<"Fixed "<<FixedInstr<<" machine instructions.\n");		DEBUG(dbgs()<<"Fixed "<<FixedInstr<<" machine instructions.\n");
}		}

void StackColoring::removeInvalidSlotRanges() {		void StackColoring::removeInvalidSlotRanges() {
for (MachineBasicBlock &BB : *MF)		for (MachineBasicBlock &BB : *MF)
for (MachineInstr &I : BB) {		for (MachineInstr &I : BB) {
if (I.getOpcode() == TargetOpcode::LIFETIME_START \|\|		if (I.getOpcode() == TargetOpcode::LIFETIME_START \|\|
I.getOpcode() == TargetOpcode::LIFETIME_END \|\| I.isDebugValue())		I.getOpcode() == TargetOpcode::LIFETIME_END \|\| I.isDebugInstr())
continue;		continue;

// Some intervals are suspicious! In some cases we find address		// Some intervals are suspicious! In some cases we find address
// calculations outside of the lifetime zone, but not actual memory		// calculations outside of the lifetime zone, but not actual memory
// read or write. Memory accesses outside of the lifetime zone are a clear		// read or write. Memory accesses outside of the lifetime zone are a clear
// violation, but address calculations are okay. This can happen when		// violation, but address calculations are okay. This can happen when
// GEPs are hoisted outside of the lifetime zone.		// GEPs are hoisted outside of the lifetime zone.
// So, in here we only check instructions which can read or write memory.		// So, in here we only check instructions which can read or write memory.
▲ Show 20 Lines • Show All 208 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/StackSlotColoring.cpp

Show First 20 Lines • Show All 417 Lines • ▼ Show 20 Lines	for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();

unsigned LoadReg = 0;		unsigned LoadReg = 0;
unsigned StoreReg = 0;		unsigned StoreReg = 0;
unsigned LoadSize = 0;		unsigned LoadSize = 0;
unsigned StoreSize = 0;		unsigned StoreSize = 0;
if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))		if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))
continue;		continue;
// Skip the ...pseudo debugging... instructions between a load and store.		// Skip the ...pseudo debugging... instructions between a load and store.
while ((NextMI != E) && NextMI->isDebugValue()) {		while ((NextMI != E) && NextMI->isDebugInstr()) {
++NextMI;		++NextMI;
++I;		++I;
}		}
if (NextMI == E) continue;		if (NextMI == E) continue;
if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS, StoreSize)))		if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS, StoreSize)))
continue;		continue;
if (FirstSS != SecondSS \|\| LoadReg != StoreReg \|\| FirstSS == -1 \|\|		if (FirstSS != SecondSS \|\| LoadReg != StoreReg \|\| FirstSS == -1 \|\|
LoadSize != StoreSize)		LoadSize != StoreSize)
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Show First 20 Lines • Show All 284 Lines • ▼ Show 20 Lines	sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
// instruction is before or after another instruction. Then we can use		// instruction is before or after another instruction. Then we can use
// MachineRegisterInfo def / use instead.		// MachineRegisterInfo def / use instead.
MachineOperand *KillMO = nullptr;		MachineOperand *KillMO = nullptr;
MachineBasicBlock::iterator KillPos = KillMI;		MachineBasicBlock::iterator KillPos = KillMI;
++KillPos;		++KillPos;

unsigned NumVisited = 0;		unsigned NumVisited = 0;
for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {		for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
// DBG_VALUE cannot be counted against the limit.		// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugValue())		if (OtherMI.isDebugInstr())
continue;		continue;
if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.		if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
return false;		return false;
++NumVisited;		++NumVisited;
for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = OtherMI.getOperand(i);		MachineOperand &MO = OtherMI.getOperand(i);
if (!MO.isReg())		if (!MO.isReg())
continue;		continue;
▲ Show 20 Lines • Show All 632 Lines • ▼ Show 20 Lines	while (End->isCopy() &&
++End;		++End;
}		}

// Check if the reschedule will not break dependencies.		// Check if the reschedule will not break dependencies.
unsigned NumVisited = 0;		unsigned NumVisited = 0;
MachineBasicBlock::iterator KillPos = KillMI;		MachineBasicBlock::iterator KillPos = KillMI;
++KillPos;		++KillPos;
for (MachineInstr &OtherMI : make_range(End, KillPos)) {		for (MachineInstr &OtherMI : make_range(End, KillPos)) {
// DBG_VALUE cannot be counted against the limit.		// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugValue())		if (OtherMI.isDebugInstr())
continue;		continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.		if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false;		return false;
++NumVisited;		++NumVisited;
if (OtherMI.hasUnmodeledSideEffects() \|\| OtherMI.isCall() \|\|		if (OtherMI.hasUnmodeledSideEffects() \|\| OtherMI.isCall() \|\|
OtherMI.isBranch() \|\| OtherMI.isTerminator())		OtherMI.isBranch() \|\| OtherMI.isTerminator())
// Don't move pass calls, etc.		// Don't move pass calls, etc.
return false;		return false;
Show All 27 Lines	for (const MachineOperand &MO : OtherMI.operands()) {
// Ensure that if this is register in question, its the kill we expect.		// Ensure that if this is register in question, its the kill we expect.
assert((MOReg != Reg \|\| &OtherMI == KillMI) &&		assert((MOReg != Reg \|\| &OtherMI == KillMI) &&
"Found multiple kills of a register in a basic block");		"Found multiple kills of a register in a basic block");
}		}
}		}
}		}

// Move debug info as well.		// Move debug info as well.
while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())		while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())
--Begin;		--Begin;

nmi = End;		nmi = End;
MachineBasicBlock::iterator InsertPos = KillPos;		MachineBasicBlock::iterator InsertPos = KillPos;
if (LIS) {		if (LIS) {
// We have to move the copies first so that the MBB is still well-formed		// We have to move the copies first so that the MBB is still well-formed
// when calling handleMove().		// when calling handleMove().
for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {		for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines	if (MO.isUse()) {
LiveDefs.insert(MOReg);		LiveDefs.insert(MOReg);
}		}
}		}

// Check if the reschedule will not break depedencies.		// Check if the reschedule will not break depedencies.
unsigned NumVisited = 0;		unsigned NumVisited = 0;
for (MachineInstr &OtherMI :		for (MachineInstr &OtherMI :
make_range(mi, MachineBasicBlock::iterator(KillMI))) {		make_range(mi, MachineBasicBlock::iterator(KillMI))) {
// DBG_VALUE cannot be counted against the limit.		// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugValue())		if (OtherMI.isDebugInstr())
continue;		continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.		if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false;		return false;
++NumVisited;		++NumVisited;
if (OtherMI.hasUnmodeledSideEffects() \|\| OtherMI.isCall() \|\|		if (OtherMI.hasUnmodeledSideEffects() \|\| OtherMI.isCall() \|\|
OtherMI.isBranch() \|\| OtherMI.isTerminator())		OtherMI.isBranch() \|\| OtherMI.isTerminator())
// Don't move pass calls, etc.		// Don't move pass calls, etc.
return false;		return false;
Show All 30 Lines	for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
return false;		return false;
// Physical register def is seen.		// Physical register def is seen.
Defs.erase(MOReg);		Defs.erase(MOReg);
}		}
}		}

// Move the old kill above MI, don't forget to move debug info as well.		// Move the old kill above MI, don't forget to move debug info as well.
MachineBasicBlock::iterator InsertPos = mi;		MachineBasicBlock::iterator InsertPos = mi;
while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())		while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())
--InsertPos;		--InsertPos;
MachineBasicBlock::iterator From = KillMI;		MachineBasicBlock::iterator From = KillMI;
MachineBasicBlock::iterator To = std::next(From);		MachineBasicBlock::iterator To = std::next(From);
while (std::prev(From)->isDebugValue())		while (std::prev(From)->isDebugInstr())
--From;		--From;
MBB->splice(InsertPos, MBB, From, To);		MBB->splice(InsertPos, MBB, From, To);

nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.		nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
DistanceMap.erase(DI);		DistanceMap.erase(DI);

// Update live variables		// Update live variables
if (LIS) {		if (LIS) {
▲ Show 20 Lines • Show All 516 Lines • ▼ Show 20 Lines	for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
DstRegMap.clear();		DstRegMap.clear();
Processed.clear();		Processed.clear();
SunkInstrs.clear();		SunkInstrs.clear();
for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();		for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
mi != me; ) {		mi != me; ) {
MachineBasicBlock::iterator nmi = std::next(mi);		MachineBasicBlock::iterator nmi = std::next(mi);
// Don't revisit an instruction previously converted by target. It may		// Don't revisit an instruction previously converted by target. It may
// contain undef register operands (%noreg), which are not handled.		// contain undef register operands (%noreg), which are not handled.
if (mi->isDebugValue() \|\| SunkInstrs.count(&*mi)) {		if (mi->isDebugInstr() \|\| SunkInstrs.count(&*mi)) {
mi = nmi;		mi = nmi;
continue;		continue;
}		}

// Expand REG_SEQUENCE instructions. This will position mi at the first		// Expand REG_SEQUENCE instructions. This will position mi at the first
// expanded instruction.		// expanded instruction.
if (mi->isRegSequence())		if (mi->isRegSequence())
eliminateRegSequence(mi);		eliminateRegSequence(mi);
▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp

Show First 20 Lines • Show All 386 Lines • ▼ Show 20 Lines	if (!MBB->livein_empty()) {
return false;		return false;
}		}

unsigned InstrCount = 0;		unsigned InstrCount = 0;

// Check all instructions, except the terminators. It is assumed that		// Check all instructions, except the terminators. It is assumed that
// terminators never have side effects or define any used register values.		// terminators never have side effects or define any used register values.
for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {		for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
if (I.isDebugValue())		if (I.isDebugInstr())
continue;		continue;

if (++InstrCount > BlockInstrLimit && !Stress) {		if (++InstrCount > BlockInstrLimit && !Stress) {
DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "		DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");		<< BlockInstrLimit << " instructions.\n");
return false;		return false;
}		}

▲ Show 20 Lines • Show All 551 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

	Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
	/// size limit beyond which some of these instructions will require a scratch			/// size limit beyond which some of these instructions will require a scratch
	/// register during their expansion later.			/// register during their expansion later.
	static unsigned estimateRSStackSizeLimit(MachineFunction &MF) {			static unsigned estimateRSStackSizeLimit(MachineFunction &MF) {
	// FIXME: For now, just conservatively guestimate based on unscaled indexing			// FIXME: For now, just conservatively guestimate based on unscaled indexing
	// range. We'll end up allocating an unnecessary spill slot a lot, but			// range. We'll end up allocating an unnecessary spill slot a lot, but
	// realistically that's not a big deal at this stage of the game.			// realistically that's not a big deal at this stage of the game.
	for (MachineBasicBlock &MBB : MF) {			for (MachineBasicBlock &MBB : MF) {
	for (MachineInstr &MI : MBB) {			for (MachineInstr &MI : MBB) {
	if (MI.isDebugValue() \|\| MI.isPseudo() \|\|			if (MI.isDebugInstr() \|\| MI.isPseudo() \|\|
	MI.getOpcode() == AArch64::ADDXri \|\|			MI.getOpcode() == AArch64::ADDXri \|\|
	MI.getOpcode() == AArch64::ADDSXri)			MI.getOpcode() == AArch64::ADDSXri)
	continue;			continue;

	for (const MachineOperand &MO : MI.operands()) {			for (const MachineOperand &MO : MI.operands()) {
	if (!MO.isFI())			if (!MO.isFI())
	continue;			continue;

	▲ Show 20 Lines • Show All 1,356 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

Show First 20 Lines • Show All 5,038 Lines • ▼ Show 20 Lines	AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
MachineFunction *MF = MBB->getParent();		MachineFunction *MF = MBB->getParent();
AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();		AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();

// Don't outline LOHs.		// Don't outline LOHs.
if (FuncInfo->getLOHRelated().count(&MI))		if (FuncInfo->getLOHRelated().count(&MI))
return MachineOutlinerInstrType::Illegal;		return MachineOutlinerInstrType::Illegal;

// Don't allow debug values to impact outlining type.		// Don't allow debug values to impact outlining type.
if (MI.isDebugValue() \|\| MI.isIndirectDebugValue())		if (MI.isDebugInstr() \|\| MI.isIndirectDebugValue())
return MachineOutlinerInstrType::Invisible;		return MachineOutlinerInstrType::Invisible;

// At this point, KILL instructions don't really tell us much so we can go		// At this point, KILL instructions don't really tell us much so we can go
// ahead and skip over them.		// ahead and skip over them.
if (MI.isKill())		if (MI.isKill())
return MachineOutlinerInstrType::Invisible;		return MachineOutlinerInstrType::Invisible;

// Is this a terminator for a basic block?		// Is this a terminator for a basic block?
▲ Show 20 Lines • Show All 326 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Show First 20 Lines • Show All 505 Lines • ▼ Show 20 Lines	uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {

uint64_t CodeSize = 0;		uint64_t CodeSize = 0;

for (const MachineBasicBlock &MBB : MF) {		for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {		for (const MachineInstr &MI : MBB) {
// TODO: CodeSize should account for multiple functions.		// TODO: CodeSize should account for multiple functions.

// TODO: Should we count size of debug info?		// TODO: Should we count size of debug info?
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

CodeSize += TII->getInstSizeInBytes(MI);		CodeSize += TII->getInstSizeInBytes(MI);
}		}
}		}

return CodeSize;		return CodeSize;
}		}
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines	for (const MachineInstr &MI : MBB) {
case AMDGPU::M0:		case AMDGPU::M0:
case AMDGPU::SRC_SHARED_BASE:		case AMDGPU::SRC_SHARED_BASE:
case AMDGPU::SRC_SHARED_LIMIT:		case AMDGPU::SRC_SHARED_LIMIT:
case AMDGPU::SRC_PRIVATE_BASE:		case AMDGPU::SRC_PRIVATE_BASE:
case AMDGPU::SRC_PRIVATE_LIMIT:		case AMDGPU::SRC_PRIVATE_LIMIT:
continue;		continue;

case AMDGPU::NoRegister:		case AMDGPU::NoRegister:
assert(MI.isDebugValue());		assert(MI.isDebugInstr());
continue;		continue;

case AMDGPU::VCC:		case AMDGPU::VCC:
case AMDGPU::VCC_LO:		case AMDGPU::VCC_LO:
case AMDGPU::VCC_HI:		case AMDGPU::VCC_HI:
Info.UsesVCC = true;		Info.UsesVCC = true;
continue;		continue;

▲ Show 20 Lines • Show All 631 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Show First 20 Lines • Show All 628 Lines • ▼ Show 20 Lines	int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) {
auto IsHazardFn = [TII] (MachineInstr *MI) {		auto IsHazardFn = [TII] (MachineInstr *MI) {
return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;		return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;
};		};
int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);		int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
return RFEWaitStates - WaitStatesNeeded;		return RFEWaitStates - WaitStatesNeeded;
}		}

int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {		int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
if (MI->isDebugValue())		if (MI->isDebugInstr())
return 0;		return 0;

const SIRegisterInfo *TRI = ST.getRegisterInfo();		const SIRegisterInfo *TRI = ST.getRegisterInfo();
if (!ST.hasSMovFedHazard())		if (!ST.hasSMovFedHazard())
return 0;		return 0;

// Check for any instruction reading an SGPR after a write from		// Check for any instruction reading an SGPR after a write from
// s_mov_fed_b32.		// s_mov_fed_b32.
Show All 25 Lines

llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines	static void printRegion(raw_ostream &OS,
unsigned MaxInstNum =		unsigned MaxInstNum =
std::numeric_limits<unsigned>::max()) {		std::numeric_limits<unsigned>::max()) {
auto BB = Begin->getParent();		auto BB = Begin->getParent();
OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' '		OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' '
<< BB->getName() << ":\n";		<< BB->getName() << ":\n";
auto I = Begin;		auto I = Begin;
MaxInstNum = std::max(MaxInstNum, 1u);		MaxInstNum = std::max(MaxInstNum, 1u);
for (; I != End && MaxInstNum; ++I, --MaxInstNum) {		for (; I != End && MaxInstNum; ++I, --MaxInstNum) {
if (!I->isDebugValue() && LIS)		if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);		OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;		OS << '\t' << *I;
}		}
if (I != End) {		if (I != End) {
OS << "\t...\n";		OS << "\t...\n";
I = std::prev(End);		I = std::prev(End);
if (!I->isDebugValue() && LIS)		if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);		OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;		OS << '\t' << *I;
}		}
if (End != BB->end()) { // print boundary inst if present		if (End != BB->end()) { // print boundary inst if present
OS << "----\n";		OS << "----\n";
if (LIS) OS << LIS->getInstructionIndex(*End) << '\t';		if (LIS) OS << LIS->getInstructionIndex(*End) << '\t';
OS << *End;		OS << *End;
}		}
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#endif		#endif
auto BB = R.Begin->getParent();		auto BB = R.Begin->getParent();
auto Top = R.Begin;		auto Top = R.Begin;
for (const auto &I : Schedule) {		for (const auto &I : Schedule) {
auto MI = getMachineInstr(I);		auto MI = getMachineInstr(I);
if (MI != &*Top) {		if (MI != &*Top) {
BB->remove(MI);		BB->remove(MI);
BB->insert(Top, MI);		BB->insert(Top, MI);
if (!MI->isDebugValue())		if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);		LIS->handleMove(*MI, true);
}		}
if (!MI->isDebugValue()) {		if (!MI->isDebugInstr()) {
// Reset read - undef flags and update them later.		// Reset read - undef flags and update them later.
for (auto &Op : MI->operands())		for (auto &Op : MI->operands())
if (Op.isReg() && Op.isDef())		if (Op.isReg() && Op.isDef())
Op.setIsUndef(false);		Op.setIsUndef(false);

RegisterOperands RegOpers;		RegisterOperands RegOpers;
RegOpers.collect(MI, TRI, MRI, /ShouldTrackLaneMasks/true,		RegOpers.collect(MI, TRI, MRI, /ShouldTrackLaneMasks/true,
/IgnoreDead/false);		/IgnoreDead/false);
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llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines	void GCNUpwardRPTracker::reset(const MachineInstr &MI,
MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);		MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
}		}

void GCNUpwardRPTracker::recede(const MachineInstr &MI) {		void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
assert(MRI && "call reset first");		assert(MRI && "call reset first");

LastTrackedMI = &MI;		LastTrackedMI = &MI;

if (MI.isDebugValue())		if (MI.isDebugInstr())
return;		return;

auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);		auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);

// calc pressure at the MI (defs + uses)		// calc pressure at the MI (defs + uses)
auto AtMIPressure = CurPressure;		auto AtMIPressure = CurPressure;
for (const auto &U : RegUses) {		for (const auto &U : RegUses) {
auto LiveMask = LiveRegs[U.RegUnit];		auto LiveMask = LiveRegs[U.RegUnit];
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llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Show First 20 Lines • Show All 382 Lines • ▼ Show 20 Lines	void GCNScheduleDAGMILive::schedule() {
if (WavesAfter >= WavesBefore) {		if (WavesAfter >= WavesBefore) {
Pressure[RegionIdx] = PressureAfter;		Pressure[RegionIdx] = PressureAfter;
return;		return;
}		}

DEBUG(dbgs() << "Attempting to revert scheduling.\n");		DEBUG(dbgs() << "Attempting to revert scheduling.\n");
RegionEnd = RegionBegin;		RegionEnd = RegionBegin;
for (MachineInstr *MI : Unsched) {		for (MachineInstr *MI : Unsched) {
if (MI->isDebugValue())		if (MI->isDebugInstr())
continue;		continue;

if (MI->getIterator() != RegionEnd) {		if (MI->getIterator() != RegionEnd) {
BB->remove(MI);		BB->remove(MI);
BB->insert(RegionEnd, MI);		BB->insert(RegionEnd, MI);
if (!MI->isDebugValue())		if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);		LIS->handleMove(*MI, true);
}		}
// Reset read-undef flags and update them later.		// Reset read-undef flags and update them later.
for (auto &Op : MI->operands())		for (auto &Op : MI->operands())
if (Op.isReg() && Op.isDef())		if (Op.isReg() && Op.isDef())
Op.setIsUndef(false);		Op.setIsUndef(false);
RegisterOperands RegOpers;		RegisterOperands RegOpers;
RegOpers.collect(MI, TRI, MRI, ShouldTrackLaneMasks, false);		RegOpers.collect(MI, TRI, MRI, ShouldTrackLaneMasks, false);
if (!MI->isDebugValue()) {		if (!MI->isDebugInstr()) {
if (ShouldTrackLaneMasks) {		if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.		// Adjust liveness and add missing dead+read-undef flags.
SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();		SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);		RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else {		} else {
// Adjust for missing dead-def flags.		// Adjust for missing dead-def flags.
RegOpers.detectDeadDefs(MI, LIS);		RegOpers.detectDeadDefs(MI, LIS);
}		}
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llvm/trunk/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	bool SIDebuggerInsertNops::runOnMachineFunction(MachineFunction &MF) {
// Target instruction info.		// Target instruction info.
const SIInstrInfo *TII = ST.getInstrInfo();		const SIInstrInfo *TII = ST.getInstrInfo();

// Set containing line numbers that have nop inserted.		// Set containing line numbers that have nop inserted.
DenseSet<unsigned> NopInserted;		DenseSet<unsigned> NopInserted;

for (auto &MBB : MF) {		for (auto &MBB : MF) {
for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {		for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Skip DBG_VALUE instructions and instructions without location.		// Skip debug instructions and instructions without location.
if (MI->isDebugValue() \|\| !MI->getDebugLoc())		if (MI->isDebugInstr() \|\| !MI->getDebugLoc())
continue;		continue;

// Insert nop instruction if line number does not have nop inserted.		// Insert nop instruction if line number does not have nop inserted.
auto DL = MI->getDebugLoc();		auto DL = MI->getDebugLoc();
if (NopInserted.find(DL.getLine()) == NopInserted.end()) {		if (NopInserted.find(DL.getLine()) == NopInserted.end()) {
BuildMI(MBB, *MI, DL, TII->get(AMDGPU::S_NOP))		BuildMI(MBB, *MI, DL, TII->get(AMDGPU::S_NOP))
.addImm(0);		.addImm(0);
NopInserted.insert(DL.getLine());		NopInserted.insert(DL.getLine());
}		}
}		}
}		}

return true;		return true;
}		}

llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Show First 20 Lines • Show All 891 Lines • ▼ Show 20 Lines	void SIInsertWaitcnts::generateWaitcntInstBefore(
bool NeedLineMapping = false; // TODO: Check on this.		bool NeedLineMapping = false; // TODO: Check on this.

// ForceEmitZeroWaitcnt: force a single s_waitcnt 0 due to hw bug		// ForceEmitZeroWaitcnt: force a single s_waitcnt 0 due to hw bug
bool ForceEmitZeroWaitcnt = false;		bool ForceEmitZeroWaitcnt = false;

setForceEmitWaitcnt();		setForceEmitWaitcnt();
bool IsForceEmitWaitcnt = isForceEmitWaitcnt();		bool IsForceEmitWaitcnt = isForceEmitWaitcnt();

if (MI.isDebugValue() &&		if (MI.isDebugInstr() &&
// TODO: any other opcode?		// TODO: any other opcode?
!NeedLineMapping) {		!NeedLineMapping) {
return;		return;
}		}

// See if an s_waitcnt is forced at block entry, or is needed at		// See if an s_waitcnt is forced at block entry, or is needed at
// program end.		// program end.
if (ScoreBrackets->getWaitAtBeginning()) {		if (ScoreBrackets->getWaitAtBeginning()) {
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llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp

	Show First 20 Lines • Show All 1,274 Lines • ▼ Show 20 Lines

	// Two functions taken from Codegen/MachineScheduler.cpp			// Two functions taken from Codegen/MachineScheduler.cpp

	/// Non-const version.			/// Non-const version.
	static MachineBasicBlock::iterator			static MachineBasicBlock::iterator
	nextIfDebug(MachineBasicBlock::iterator I,			nextIfDebug(MachineBasicBlock::iterator I,
	MachineBasicBlock::const_iterator End) {			MachineBasicBlock::const_iterator End) {
	for (; I != End; ++I) {			for (; I != End; ++I) {
	if (!I->isDebugValue())			if (!I->isDebugInstr())
	break;			break;
	}			}
	return I;			return I;
	}			}

	void SIScheduleBlockCreator::topologicalSort() {			void SIScheduleBlockCreator::topologicalSort() {
	unsigned DAGSize = CurrentBlocks.size();			unsigned DAGSize = CurrentBlocks.size();
	std::vector<int> WorkList;			std::vector<int> WorkList;
	▲ Show 20 Lines • Show All 773 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines	if (MBB.succ_empty()) {
if (I != E) {		if (I != E) {
if (I->isUnconditionalBranch() \|\| I->getOpcode() == AMDGPU::S_ENDPGM)		if (I->isUnconditionalBranch() \|\| I->getOpcode() == AMDGPU::S_ENDPGM)
++I;		++I;
else if (I->isBranch())		else if (I->isBranch())
continue;		continue;
}		}

while (I != E) {		while (I != E) {
if (I->isDebugValue()) {		if (I->isDebugInstr()) {
I = std::next(I);		I = std::next(I);
continue;		continue;
}		}

if (I->mayStore() \|\| I->isBarrier() \|\| I->isCall() \|\|		if (I->mayStore() \|\| I->isBarrier() \|\| I->isCall() \|\|
I->hasUnmodeledSideEffects() \|\| I->hasOrderedMemoryRef())		I->hasUnmodeledSideEffects() \|\| I->hasOrderedMemoryRef())
break;		break;

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llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines	bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,

while (isPredicated(*I) \|\| I->isTerminator() \|\| I->isDebugValue()) {		while (isPredicated(*I) \|\| I->isTerminator() \|\| I->isDebugValue()) {
// Flag to be raised on unanalyzeable instructions. This is useful in cases		// Flag to be raised on unanalyzeable instructions. This is useful in cases
// where we want to clean up on the end of the basic block before we bail		// where we want to clean up on the end of the basic block before we bail
// out.		// out.
bool CantAnalyze = false;		bool CantAnalyze = false;

// Skip over DEBUG values and predicated nonterminators.		// Skip over DEBUG values and predicated nonterminators.
while (I->isDebugValue() \|\| !I->isTerminator()) {		while (I->isDebugInstr() \|\| !I->isTerminator()) {
if (I == MBB.begin())		if (I == MBB.begin())
return false;		return false;
--I;		--I;
}		}

if (isJumpOpcode(I->getOpcode())) {		if (isJumpOpcode(I->getOpcode())) {
// Indirect branches and jump tables can't be analyzed, but we still want		// Indirect branches and jump tables can't be analyzed, but we still want
// to clean up any instructions at the tail of the basic block.		// to clean up any instructions at the tail of the basic block.
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llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines	bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
// analyzed or we give up.		// analyzed or we give up.
while (isPredicated(*I) \|\| I->isTerminator() \|\| I->isDebugValue()) {		while (isPredicated(*I) \|\| I->isTerminator() \|\| I->isDebugValue()) {
// Flag to be raised on unanalyzeable instructions. This is useful in cases		// Flag to be raised on unanalyzeable instructions. This is useful in cases
// where we want to clean up on the end of the basic block before we bail		// where we want to clean up on the end of the basic block before we bail
// out.		// out.
bool CantAnalyze = false;		bool CantAnalyze = false;

// Skip over DEBUG values and predicated nonterminators.		// Skip over DEBUG values and predicated nonterminators.
while (I->isDebugValue() \|\| !I->isTerminator()) {		while (I->isDebugInstr() \|\| !I->isTerminator()) {
if (I == MBB.begin())		if (I == MBB.begin())
return false;		return false;
--I;		--I;
}		}

if (isIndirectBranchOpcode(I->getOpcode()) \|\|		if (isIndirectBranchOpcode(I->getOpcode()) \|\|
isJumpTableBranchOpcode(I->getOpcode())) {		isJumpTableBranchOpcode(I->getOpcode())) {
// Indirect branches and jump tables can't be analyzed, but we still want		// Indirect branches and jump tables can't be analyzed, but we still want
▲ Show 20 Lines • Show All 1,467 Lines • ▼ Show 20 Lines	bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,		const MachineBasicBlock *MBB,
const MachineFunction &MF) const {		const MachineFunction &MF) const {
// Debug info is never a scheduling boundary. It's necessary to be explicit		// Debug info is never a scheduling boundary. It's necessary to be explicit
// due to the special treatment of IT instructions below, otherwise a		// due to the special treatment of IT instructions below, otherwise a
// dbg_value followed by an IT will result in the IT instruction being		// dbg_value followed by an IT will result in the IT instruction being
// considered a scheduling hazard, which is wrong. It should be the actual		// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is		// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.		// when debug info is not present.
if (MI.isDebugValue())		if (MI.isDebugInstr())
return false;		return false;

// Terminators and labels can't be scheduled around.		// Terminators and labels can't be scheduled around.
if (MI.isTerminator() \|\| MI.isPosition())		if (MI.isTerminator() \|\| MI.isPosition())
return true;		return true;

// Treat the start of the IT block as a scheduling boundary, but schedule		// Treat the start of the IT block as a scheduling boundary, but schedule
// t2IT along with all instructions following it.		// t2IT along with all instructions following it.
// FIXME: This is a big hammer. But the alternative is to add all potential		// FIXME: This is a big hammer. But the alternative is to add all potential
// true and anti dependencies to IT block instructions as implicit operands		// true and anti dependencies to IT block instructions as implicit operands
// to the t2IT instruction. The added compile time and complexity does not		// to the t2IT instruction. The added compile time and complexity does not
// seem worth it.		// seem worth it.
MachineBasicBlock::const_iterator I = MI;		MachineBasicBlock::const_iterator I = MI;
// Make sure to skip any dbg_value instructions		// Make sure to skip any debug instructions
while (++I != MBB->end() && I->isDebugValue())		while (++I != MBB->end() && I->isDebugInstr())
;		;
if (I != MBB->end() && I->getOpcode() == ARM::t2IT)		if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
return true;		return true;

// Don't attempt to schedule around any instruction that defines		// Don't attempt to schedule around any instruction that defines
// a stack-oriented pointer, as it's unlikely to be profitable. This		// a stack-oriented pointer, as it's unlikely to be profitable. This
// saves compile time, because it doesn't require every single		// saves compile time, because it doesn't require every single
// stack slot reference to depend on the instruction that does the		// stack slot reference to depend on the instruction that does the
▲ Show 20 Lines • Show All 3,157 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Show First 20 Lines • Show All 695 Lines • ▼ Show 20 Lines	initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
// Now go back through the instructions and build up our data structures.		// Now go back through the instructions and build up our data structures.
for (MachineBasicBlock &MBB : *MF) {		for (MachineBasicBlock &MBB : *MF) {
// If this block doesn't fall through into the next MBB, then this is		// If this block doesn't fall through into the next MBB, then this is
// 'water' that a constant pool island could be placed.		// 'water' that a constant pool island could be placed.
if (!BBHasFallthrough(&MBB))		if (!BBHasFallthrough(&MBB))
WaterList.push_back(&MBB);		WaterList.push_back(&MBB);

for (MachineInstr &I : MBB) {		for (MachineInstr &I : MBB) {
if (I.isDebugValue())		if (I.isDebugInstr())
continue;		continue;

unsigned Opc = I.getOpcode();		unsigned Opc = I.getOpcode();
if (I.isBranch()) {		if (I.isBranch()) {
bool isCond = false;		bool isCond = false;
unsigned Bits = 0;		unsigned Bits = 0;
unsigned Scale = 1;		unsigned Scale = 1;
int UOpc = Opc;		int UOpc = Opc;
▲ Show 20 Lines • Show All 1,671 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp

	Show All 31 Lines
	}			}

	ScheduleHazardRecognizer::HazardType			ScheduleHazardRecognizer::HazardType
	ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {			ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
	assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");			assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");

	MachineInstr *MI = SU->getInstr();			MachineInstr *MI = SU->getInstr();

	if (!MI->isDebugValue()) {			if (!MI->isDebugInstr()) {
	// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following			// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
	// a VMLA / VMLS will cause 4 cycle stall.			// a VMLA / VMLS will cause 4 cycle stall.
	const MCInstrDesc &MCID = MI->getDesc();			const MCInstrDesc &MCID = MI->getDesc();
	if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {			if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
	MachineInstr *DefMI = LastMI;			MachineInstr *DefMI = LastMI;
	const MCInstrDesc &LastMCID = LastMI->getDesc();			const MCInstrDesc &LastMCID = LastMI->getDesc();
	const MachineFunction *MF = MI->getParent()->getParent();			const MachineFunction *MF = MI->getParent()->getParent();
	const ARMBaseInstrInfo &TII = static_cast<const ARMBaseInstrInfo >(			const ARMBaseInstrInfo &TII = static_cast<const ARMBaseInstrInfo >(
	Show All 27 Lines
	void ARMHazardRecognizer::Reset() {			void ARMHazardRecognizer::Reset() {
	LastMI = nullptr;			LastMI = nullptr;
	FpMLxStalls = 0;			FpMLxStalls = 0;
	ScoreboardHazardRecognizer::Reset();			ScoreboardHazardRecognizer::Reset();
	}			}

	void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {			void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
	MachineInstr *MI = SU->getInstr();			MachineInstr *MI = SU->getInstr();
	if (!MI->isDebugValue()) {			if (!MI->isDebugInstr()) {
	LastMI = MI;			LastMI = MI;
	FpMLxStalls = 0;			FpMLxStalls = 0;
	}			}

	ScoreboardHazardRecognizer::EmitInstruction(SU);			ScoreboardHazardRecognizer::EmitInstruction(SU);
	}			}

	void ARMHazardRecognizer::AdvanceCycle() {			void ARMHazardRecognizer::AdvanceCycle() {
	Show All 9 Lines

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Show First 20 Lines • Show All 1,192 Lines • ▼ Show 20 Lines	findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg,
MachineBasicBlock &MBB = *MBBI->getParent();		MachineBasicBlock &MBB = *MBBI->getParent();
MachineBasicBlock::iterator BeginMBBI = MBB.begin();		MachineBasicBlock::iterator BeginMBBI = MBB.begin();
MachineBasicBlock::iterator EndMBBI = MBB.end();		MachineBasicBlock::iterator EndMBBI = MBB.end();
if (MBBI == BeginMBBI)		if (MBBI == BeginMBBI)
return EndMBBI;		return EndMBBI;

// Skip debug values.		// Skip debug values.
MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);		MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
while (PrevMBBI->isDebugValue() && PrevMBBI != BeginMBBI)		while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
--PrevMBBI;		--PrevMBBI;

Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);		Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
return Offset == 0 ? EndMBBI : PrevMBBI;		return Offset == 0 ? EndMBBI : PrevMBBI;
}		}

/// Searches for a increment or decrement of \p Reg after \p MBBI.		/// Searches for a increment or decrement of \p Reg after \p MBBI.
static MachineBasicBlock::iterator		static MachineBasicBlock::iterator
findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg,		findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg,
ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {		ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {
Offset = 0;		Offset = 0;
MachineBasicBlock &MBB = *MBBI->getParent();		MachineBasicBlock &MBB = *MBBI->getParent();
MachineBasicBlock::iterator EndMBBI = MBB.end();		MachineBasicBlock::iterator EndMBBI = MBB.end();
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);		MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
// Skip debug values.		// Skip debug values.
while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())		while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
++NextMBBI;		++NextMBBI;
if (NextMBBI == EndMBBI)		if (NextMBBI == EndMBBI)
return EndMBBI;		return EndMBBI;

Offset = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);		Offset = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
return Offset == 0 ? EndMBBI : NextMBBI;		return Offset == 0 ? EndMBBI : NextMBBI;
}		}

▲ Show 20 Lines • Show All 576 Lines • ▼ Show 20 Lines	if (isMemoryOp(*MBBI)) {
}		}
}		}
}		}

// Don't advance the iterator; The op will start a new chain next.		// Don't advance the iterator; The op will start a new chain next.
MBBI = I;		MBBI = I;
--Position;		--Position;
// Fallthrough to look into existing chain.		// Fallthrough to look into existing chain.
} else if (MBBI->isDebugValue()) {		} else if (MBBI->isDebugInstr()) {
continue;		continue;
} else if (MBBI->getOpcode() == ARM::t2LDRDi8 \|\|		} else if (MBBI->getOpcode() == ARM::t2LDRDi8 \|\|
MBBI->getOpcode() == ARM::t2STRDi8) {		MBBI->getOpcode() == ARM::t2STRDi8) {
// ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions		// ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions
// remember them because we may still be able to merge add/sub into them.		// remember them because we may still be able to merge add/sub into them.
MergeBaseCandidates.push_back(&*MBBI);		MergeBaseCandidates.push_back(&*MBBI);
}		}

▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines	bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
if (MBB.empty()) return false;		if (MBB.empty()) return false;

MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();		MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
if (MBBI != MBB.begin() && MBBI != MBB.end() &&		if (MBBI != MBB.begin() && MBBI != MBB.end() &&
(MBBI->getOpcode() == ARM::BX_RET \|\|		(MBBI->getOpcode() == ARM::BX_RET \|\|
MBBI->getOpcode() == ARM::tBX_RET \|\|		MBBI->getOpcode() == ARM::tBX_RET \|\|
MBBI->getOpcode() == ARM::MOVPCLR)) {		MBBI->getOpcode() == ARM::MOVPCLR)) {
MachineBasicBlock::iterator PrevI = std::prev(MBBI);		MachineBasicBlock::iterator PrevI = std::prev(MBBI);
// Ignore any DBG_VALUE instructions.		// Ignore any debug instructions.
while (PrevI->isDebugValue() && PrevI != MBB.begin())		while (PrevI->isDebugInstr() && PrevI != MBB.begin())
--PrevI;		--PrevI;
MachineInstr &PrevMI = *PrevI;		MachineInstr &PrevMI = *PrevI;
unsigned Opcode = PrevMI.getOpcode();		unsigned Opcode = PrevMI.getOpcode();
if (Opcode == ARM::LDMIA_UPD \|\| Opcode == ARM::LDMDA_UPD \|\|		if (Opcode == ARM::LDMIA_UPD \|\| Opcode == ARM::LDMDA_UPD \|\|
Opcode == ARM::LDMDB_UPD \|\| Opcode == ARM::LDMIB_UPD \|\|		Opcode == ARM::LDMDB_UPD \|\| Opcode == ARM::LDMIB_UPD \|\|
Opcode == ARM::t2LDMIA_UPD \|\| Opcode == ARM::t2LDMDB_UPD) {		Opcode == ARM::t2LDMIA_UPD \|\| Opcode == ARM::t2LDMDB_UPD) {
MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);		MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
if (MO.getReg() != ARM::LR)		if (MO.getReg() != ARM::LR)
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
MachineBasicBlock::iterator E,		MachineBasicBlock::iterator E,
SmallPtrSetImpl<MachineInstr*> &MemOps,		SmallPtrSetImpl<MachineInstr*> &MemOps,
SmallSet<unsigned, 4> &MemRegs,		SmallSet<unsigned, 4> &MemRegs,
const TargetRegisterInfo *TRI,		const TargetRegisterInfo *TRI,
AliasAnalysis *AA) {		AliasAnalysis *AA) {
// Are there stores / loads / calls between them?		// Are there stores / loads / calls between them?
SmallSet<unsigned, 4> AddedRegPressure;		SmallSet<unsigned, 4> AddedRegPressure;
while (++I != E) {		while (++I != E) {
if (I->isDebugValue() \|\| MemOps.count(&*I))		if (I->isDebugInstr() \|\| MemOps.count(&*I))
continue;		continue;
if (I->isCall() \|\| I->isTerminator() \|\| I->hasUnmodeledSideEffects())		if (I->isCall() \|\| I->isTerminator() \|\| I->hasUnmodeledSideEffects())
return false;		return false;
if (I->mayStore() \|\| (!isLd && I->mayLoad()))		if (I->mayStore() \|\| (!isLd && I->mayLoad()))
for (MachineInstr *MemOp : MemOps)		for (MachineInstr *MemOp : MemOps)
if (I->mayAlias(AA, MemOp, /UseTBAA*/ false))		if (I->mayAlias(AA, MemOp, /UseTBAA*/ false))
return false;		return false;
for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {		for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines	else {
MemOps, MemRegs, TRI, AA);		MemOps, MemRegs, TRI, AA);
if (!DoMove) {		if (!DoMove) {
for (unsigned i = 0; i != NumMove; ++i)		for (unsigned i = 0; i != NumMove; ++i)
Ops.pop_back();		Ops.pop_back();
} else {		} else {
// This is the new location for the loads / stores.		// This is the new location for the loads / stores.
MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;		MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
while (InsertPos != MBB->end() &&		while (InsertPos != MBB->end() &&
(MemOps.count(&*InsertPos) \|\| InsertPos->isDebugValue()))		(MemOps.count(&*InsertPos) \|\| InsertPos->isDebugInstr()))
++InsertPos;		++InsertPos;

// If we are moving a pair of loads / stores, see if it makes sense		// If we are moving a pair of loads / stores, see if it makes sense
// to try to allocate a pair of registers that can form register pairs.		// to try to allocate a pair of registers that can form register pairs.
MachineInstr *Op0 = Ops.back();		MachineInstr *Op0 = Ops.back();
MachineInstr *Op1 = Ops[Ops.size()-2];		MachineInstr *Op1 = Ops[Ops.size()-2];
unsigned FirstReg = 0, SecondReg = 0;		unsigned FirstReg = 0, SecondReg = 0;
unsigned BaseReg = 0, PredReg = 0;		unsigned BaseReg = 0, PredReg = 0;
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines	while (MBBI != E) {
for (; MBBI != E; ++MBBI) {		for (; MBBI != E; ++MBBI) {
MachineInstr &MI = *MBBI;		MachineInstr &MI = *MBBI;
if (MI.isCall() \|\| MI.isTerminator()) {		if (MI.isCall() \|\| MI.isTerminator()) {
// Stop at barriers.		// Stop at barriers.
++MBBI;		++MBBI;
break;		break;
}		}

if (!MI.isDebugValue())		if (!MI.isDebugInstr())
MI2LocMap[&MI] = ++Loc;		MI2LocMap[&MI] = ++Loc;

if (!isMemoryOp(MI))		if (!isMemoryOp(MI))
continue;		continue;
unsigned PredReg = 0;		unsigned PredReg = 0;
if (getInstrPredicate(MI, PredReg) != ARMCC::AL)		if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
continue;		continue;

▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines	Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
if (MI->hasOptionalDef() &&		if (MI->hasOptionalDef() &&
MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)		MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
return false;		return false;

// Then peek at the next instruction to see if it's predicated on CC or OCC.		// Then peek at the next instruction to see if it's predicated on CC or OCC.
// If not, then there is nothing to be gained by moving the copy.		// If not, then there is nothing to be gained by moving the copy.
MachineBasicBlock::iterator I = MI; ++I;		MachineBasicBlock::iterator I = MI; ++I;
MachineBasicBlock::iterator E = MI->getParent()->end();		MachineBasicBlock::iterator E = MI->getParent()->end();
while (I != E && I->isDebugValue())		while (I != E && I->isDebugInstr())
++I;		++I;
if (I != E) {		if (I != E) {
unsigned NPredReg = 0;		unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);		ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
if (NCC == CC \|\| NCC == OCC)		if (NCC == CC \|\| NCC == OCC)
return true;		return true;
}		}
return false;		return false;
Show All 37 Lines	while (MBBI != E) {

// v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it		// v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
// is set: skip the loop		// is set: skip the loop
if (!restrictIT) {		if (!restrictIT) {
// Branches, including tricky ones like LDM_RET, need to end an IT		// Branches, including tricky ones like LDM_RET, need to end an IT
// block so check the instruction we just put in the block.		// block so check the instruction we just put in the block.
for (; MBBI != E && Pos &&		for (; MBBI != E && Pos &&
(!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {		(!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
if (MBBI->isDebugValue())		if (MBBI->isDebugInstr())
continue;		continue;

MachineInstr NMI = &MBBI;		MachineInstr NMI = &MBBI;
MI = NMI;		MI = NMI;

unsigned NPredReg = 0;		unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);		ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
if (NCC == CC \|\| NCC == OCC) {		if (NCC == CC \|\| NCC == OCC) {
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines	Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
// Actually replace the tail.		// Actually replace the tail.
TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);		TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);

// Fix up IT.		// Fix up IT.
if (CC != ARMCC::AL) {		if (CC != ARMCC::AL) {
MachineBasicBlock::iterator E = MBB->begin();		MachineBasicBlock::iterator E = MBB->begin();
unsigned Count = 4; // At most 4 instructions in an IT block.		unsigned Count = 4; // At most 4 instructions in an IT block.
while (Count && MBBI != E) {		while (Count && MBBI != E) {
if (MBBI->isDebugValue()) {		if (MBBI->isDebugInstr()) {
--MBBI;		--MBBI;
continue;		continue;
}		}
if (MBBI->getOpcode() == ARM::t2IT) {		if (MBBI->getOpcode() == ARM::t2IT) {
unsigned Mask = MBBI->getOperand(1).getImm();		unsigned Mask = MBBI->getOperand(1).getImm();
if (Count == 4)		if (Count == 4)
MBBI->eraseFromParent();		MBBI->eraseFromParent();
else {		else {
Show All 10 Lines	if (CC != ARMCC::AL) {
// Ctrl flow can reach here if branch folding is run before IT block		// Ctrl flow can reach here if branch folding is run before IT block
// formation pass.		// formation pass.
}		}
}		}

bool		bool
Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,		Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const {		MachineBasicBlock::iterator MBBI) const {
while (MBBI->isDebugValue()) {		while (MBBI->isDebugInstr()) {
++MBBI;		++MBBI;
if (MBBI == MBB.end())		if (MBBI == MBB.end())
return false;		return false;
}		}

unsigned PredReg = 0;		unsigned PredReg = 0;
return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;		return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
}		}
▲ Show 20 Lines • Show All 559 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Show First 20 Lines • Show All 1,027 Lines • ▼ Show 20 Lines	bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
for (; MII != E; MII = NextMII) {		for (; MII != E; MII = NextMII) {
NextMII = std::next(MII);		NextMII = std::next(MII);

MachineInstr MI = &MII;		MachineInstr MI = &MII;
if (MI->isBundle()) {		if (MI->isBundle()) {
BundleMI = MI;		BundleMI = MI;
continue;		continue;
}		}
if (MI->isDebugValue())		if (MI->isDebugInstr())
continue;		continue;

LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);		LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);

// Does NextMII belong to the same bundle as MI?		// Does NextMII belong to the same bundle as MI?
bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();		bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();

if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {		if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp

Show First 20 Lines • Show All 469 Lines • ▼ Show 20 Lines	BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
.addReg(Reg, RegState::Kill)		.addReg(Reg, RegState::Kill)
.add(predOps(ARMCC::AL));		.add(predOps(ARMCC::AL));

// The UseMI is where we would like to restore the register. If there's		// The UseMI is where we would like to restore the register. If there's
// interference with R12 before then, however, we'll need to restore it		// interference with R12 before then, however, we'll need to restore it
// before that instead and adjust the UseMI.		// before that instead and adjust the UseMI.
bool done = false;		bool done = false;
for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {		for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
if (II->isDebugValue())		if (II->isDebugInstr())
continue;		continue;
// If this instruction affects R12, adjust our restore point.		// If this instruction affects R12, adjust our restore point.
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = II->getOperand(i);		const MachineOperand &MO = II->getOperand(i);
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {		if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
UseMI = II;		UseMI = II;
done = true;		done = true;
break;		break;
▲ Show 20 Lines • Show All 135 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines	bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
bool AllowModify) const {		bool AllowModify) const {
// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
MachineBasicBlock::iterator UnCondBrIter = MBB.end();		MachineBasicBlock::iterator UnCondBrIter = MBB.end();

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue()) {		if (I->isDebugInstr()) {
continue;		continue;
}		}

// Working from the bottom, when we see a non-terminator		// Working from the bottom, when we see a non-terminator
// instruction, we're done.		// instruction, we're done.
if (!isUnpredicatedTerminator(*I)) {		if (!isUnpredicatedTerminator(*I)) {
break;		break;
}		}
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
if (BytesRemoved) *BytesRemoved = 0;		if (BytesRemoved) *BytesRemoved = 0;

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue()) {		if (I->isDebugInstr()) {
continue;		continue;
}		}
//:TODO: add here the missing jmp instructions once they are implemented		//:TODO: add here the missing jmp instructions once they are implemented
// like jmp, {e}ijmp, and other cond branches, ...		// like jmp, {e}ijmp, and other cond branches, ...
if (I->getOpcode() != AVR::RJMPk &&		if (I->getOpcode() != AVR::RJMPk &&
getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {		getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
break;		break;
}		}
▲ Show 20 Lines • Show All 119 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines	bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&FBB,		MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,		SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {		bool AllowModify) const {
// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

// Working from the bottom, when we see a non-terminator		// Working from the bottom, when we see a non-terminator
// instruction, we're done.		// instruction, we're done.
if (!isUnpredicatedTerminator(*I))		if (!isUnpredicatedTerminator(*I))
break;		break;

// A terminator that isn't a branch can't easily be handled		// A terminator that isn't a branch can't easily be handled
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines	unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (I->getOpcode() != BPF::JMP)		if (I->getOpcode() != BPF::JMP)
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
I = MBB.end();		I = MBB.end();
++Count;		++Count;
}		}

return Count;		return Count;
}		}

llvm/trunk/lib/Target/Hexagon/BitTracker.cpp

Show First 20 Lines • Show All 837 Lines • ▼ Show 20 Lines	if (Changed) {
ME.putCell(DefRR, DefC, Map);		ME.putCell(DefRR, DefC, Map);
visitUsesOf(DefRR.Reg);		visitUsesOf(DefRR.Reg);
}		}
}		}

void BT::visitNonBranch(const MachineInstr &MI) {		void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace)		if (Trace)
dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;		dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
if (MI.isDebugValue())		if (MI.isDebugInstr())
return;		return;
assert(!MI.isBranch() && "Unexpected branch instruction");		assert(!MI.isBranch() && "Unexpected branch instruction");

CellMapType ResMap;		CellMapType ResMap;
bool Eval = ME.evaluate(MI, Map, ResMap);		bool Eval = ME.evaluate(MI, Map, ResMap);

if (Trace && Eval) {		if (Trace && Eval) {
for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {		for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp

Show First 20 Lines • Show All 754 Lines • ▼ Show 20 Lines	void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
const MCInstrInfo &MCII = *Subtarget->getInstrInfo();		const MCInstrInfo &MCII = *Subtarget->getInstrInfo();

if (MI->isBundle()) {		if (MI->isBundle()) {
assert(Subtarget->usePackets() && "Support for packets is disabled");		assert(Subtarget->usePackets() && "Support for packets is disabled");
const MachineBasicBlock* MBB = MI->getParent();		const MachineBasicBlock* MBB = MI->getParent();
MachineBasicBlock::const_instr_iterator MII = MI->getIterator();		MachineBasicBlock::const_instr_iterator MII = MI->getIterator();

for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)		for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
if (!MII->isDebugValue() && !MII->isImplicitDef())		if (!MII->isDebugInstr() && !MII->isImplicitDef())
HexagonLowerToMC(MCII, &MII, MCB, this);		HexagonLowerToMC(MCII, &MII, MCB, this);
} else {		} else {
HexagonLowerToMC(MCII, MI, MCB, *this);		HexagonLowerToMC(MCII, MI, MCB, *this);
}		}

const MachineFunction &MF = *MI->getParent()->getParent();		const MachineFunction &MF = *MI->getParent()->getParent();
const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();		const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
if (MI->isBundle() && HII.getBundleNoShuf(*MI))		if (MI->isBundle() && HII.getBundleNoShuf(*MI))
Show All 14 Lines

llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	void HexagonBlockRanges::RangeList::subtract(const IndexRange &Range) {
include(T);		include(T);
}		}

HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B)		HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B)
: Block(B) {		: Block(B) {
IndexType Idx = IndexType::First;		IndexType Idx = IndexType::First;
First = Idx;		First = Idx;
for (auto &In : B) {		for (auto &In : B) {
if (In.isDebugValue())		if (In.isDebugInstr())
continue;		continue;
assert(getIndex(&In) == IndexType::None && "Instruction already in map");		assert(getIndex(&In) == IndexType::None && "Instruction already in map");
Map.insert(std::make_pair(Idx, &In));		Map.insert(std::make_pair(Idx, &In));
++Idx;		++Idx;
}		}
Last = B.empty() ? IndexType::None : unsigned(Idx)-1;		Last = B.empty() ? IndexType::None : unsigned(Idx)-1;
}		}

▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines	if (LU == IndexType::None)
LU = IndexType::Exit;		LU = IndexType::Exit;
LiveMap[R].add(LD, LU, false, false);		LiveMap[R].add(LD, LU, false, false);
LastUse[R] = LastDef[R] = IndexType::None;		LastUse[R] = LastDef[R] = IndexType::None;
};		};

RegisterSet Defs, Clobbers;		RegisterSet Defs, Clobbers;

for (auto &In : B) {		for (auto &In : B) {
if (In.isDebugValue())		if (In.isDebugInstr())
continue;		continue;
IndexType Index = IndexMap.getIndex(&In);		IndexType Index = IndexMap.getIndex(&In);
// Process uses first.		// Process uses first.
for (auto &Op : In.operands()) {		for (auto &Op : In.operands()) {
if (!Op.isReg() \|\| !Op.isUse() \|\| Op.isUndef())		if (!Op.isReg() \|\| !Op.isUse() \|\| Op.isUndef())
continue;		continue;
RegisterRef R = { Op.getReg(), Op.getSubReg() };		RegisterRef R = { Op.getReg(), Op.getSubReg() };
if (TargetRegisterInfo::isPhysicalRegister(R.Reg) && Reserved[R.Reg])		if (TargetRegisterInfo::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
▲ Show 20 Lines • Show All 212 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp

Show First 20 Lines • Show All 793 Lines • ▼ Show 20 Lines	else
visitBranchesFrom(MI);		visitBranchesFrom(MI);
}		}
}		}

bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB,		bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB,
SetVector<const MachineBasicBlock*> &Targets) {		SetVector<const MachineBasicBlock*> &Targets) {
MachineBasicBlock::const_iterator FirstBr = MB->end();		MachineBasicBlock::const_iterator FirstBr = MB->end();
for (const MachineInstr &MI : *MB) {		for (const MachineInstr &MI : *MB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
if (MI.isBranch()) {		if (MI.isBranch()) {
FirstBr = MI.getIterator();		FirstBr = MI.getIterator();
break;		break;
}		}
}		}

Targets.clear();		Targets.clear();
MachineBasicBlock::const_iterator End = MB->end();		MachineBasicBlock::const_iterator End = MB->end();

bool DoNext = true;		bool DoNext = true;
for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) {		for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) {
const MachineInstr &MI = *I;		const MachineInstr &MI = *I;
// Can there be debug instructions between branches?		// Can there be debug instructions between branches?
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
if (!InstrExec.count(&MI))		if (!InstrExec.count(&MI))
continue;		continue;
bool Eval = MCE.evaluate(MI, Cells, Targets, DoNext);		bool Eval = MCE.evaluate(MI, Cells, Targets, DoNext);
if (!Eval)		if (!Eval)
return false;		return false;
if (!DoNext)		if (!DoNext)
break;		break;
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	while (It != End && It->isPHI()) {
InstrExec.insert(&*It);		InstrExec.insert(&*It);
visitPHI(*It);		visitPHI(*It);
++It;		++It;
}		}

// If the successor block just became executable, visit all instructions.		// If the successor block just became executable, visit all instructions.
// To see if this is the first time we're visiting it, check the first		// To see if this is the first time we're visiting it, check the first
// non-debug instruction to see if it is executable.		// non-debug instruction to see if it is executable.
while (It != End && It->isDebugValue())		while (It != End && It->isDebugInstr())
++It;		++It;
assert(It == End \|\| !It->isPHI());		assert(It == End \|\| !It->isPHI());
// If this block has been visited, go on to the next one.		// If this block has been visited, go on to the next one.
if (It != End && InstrExec.count(&*It))		if (It != End && InstrExec.count(&*It))
continue;		continue;
// For now, scan all non-branch instructions. Branches require different		// For now, scan all non-branch instructions. Branches require different
// processing.		// processing.
while (It != End && !It->isBranch()) {		while (It != End && !It->isBranch()) {
if (!It->isDebugValue()) {		if (!It->isDebugInstr()) {
InstrExec.insert(&*It);		InstrExec.insert(&*It);
visitNonBranch(*It);		visitNonBranch(*It);
}		}
++It;		++It;
}		}

// Time to process the end of the block. This is different from		// Time to process the end of the block. This is different from
// processing regular (non-branch) instructions, because there can		// processing regular (non-branch) instructions, because there can
▲ Show 20 Lines • Show All 2,254 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Lines	// First try to move I2 towards I1.

for (; I != End; ++I) {		for (; I != End; ++I) {
// If the intervening instruction I:		// If the intervening instruction I:
// * modifies I2's use reg		// * modifies I2's use reg
// * modifies I2's def reg		// * modifies I2's def reg
// * reads I2's def reg		// * reads I2's def reg
// * or has unmodelled side effects		// * or has unmodelled side effects
// we can't move I2 across it.		// we can't move I2 across it.
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {		if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
isSafe = false;		isSafe = false;
break;		break;
}		}

// Update first use of the killed operand.		// Update first use of the killed operand.
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines	while(++I != End) {
// * or has a killed aliased register use of I1's use reg		// * or has a killed aliased register use of I1's use reg
// %d4 = A2_tfrpi 16		// %d4 = A2_tfrpi 16
// %r6 = A2_tfr %r9		// %r6 = A2_tfr %r9
// %r8 = KILL %r8, implicit killed %d4		// %r8 = KILL %r8, implicit killed %d4
// If we want to move R6 = across the KILL instruction we would have		// If we want to move R6 = across the KILL instruction we would have
// to remove the implicit killed %d4 operand. For now, we are		// to remove the implicit killed %d4 operand. For now, we are
// conservative and disallow the move.		// conservative and disallow the move.
// we can't move I1 across it.		// we can't move I1 across it.
if (MI.isDebugValue()) {		if (MI.isDebugInstr()) {
if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.		if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
DbgMItoMove.push_back(&MI);		DbgMItoMove.push_back(&MI);
continue;		continue;
}		}

if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) \|\|		if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) \|\|
// Check for an aliased register kill. Bail out if we see one.		// Check for an aliased register kill. Bail out if we see one.
(!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI)))		(!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI)))
Show All 21 Lines
}		}

/// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be		/// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
/// newified. (A use of a 64 bit register define can not be newified)		/// newified. (A use of a 64 bit register define can not be newified)
void		void
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {		HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
DenseMap<unsigned, MachineInstr *> LastDef;		DenseMap<unsigned, MachineInstr *> LastDef;
for (MachineInstr &MI : BB) {		for (MachineInstr &MI : BB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

// Mark TFRs that feed a potential new value store as such.		// Mark TFRs that feed a potential new value store as such.
if (TII->mayBeNewStore(MI)) {		if (TII->mayBeNewStore(MI)) {
// Look for uses of TFR instructions.		// Look for uses of TFR instructions.
for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;		for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;
++OpdIdx) {		++OpdIdx) {
MachineOperand &Op = MI.getOperand(OpdIdx);		MachineOperand &Op = MI.getOperand(OpdIdx);
Show All 10 Lines	if (TII->mayBeNewStore(MI)) {
if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))		if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
continue;		continue;

// Only close newifiable stores should influence the decision.		// Only close newifiable stores should influence the decision.
// Ignore the debug instructions in between.		// Ignore the debug instructions in between.
MachineBasicBlock::iterator It(DefInst);		MachineBasicBlock::iterator It(DefInst);
unsigned NumInstsToDef = 0;		unsigned NumInstsToDef = 0;
while (&*It != &MI) {		while (&*It != &MI) {
if (!It->isDebugValue())		if (!It->isDebugInstr())
++NumInstsToDef;		++NumInstsToDef;
++It;		++It;
}		}

if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)		if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
continue;		continue;

PotentiallyNewifiableTFR.insert(DefInst);		PotentiallyNewifiableTFR.insert(DefInst);
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
PotentiallyNewifiableTFR.clear();		PotentiallyNewifiableTFR.clear();
findPotentialNewifiableTFRs(*BI);		findPotentialNewifiableTFRs(*BI);

// Traverse instructions in basic block.		// Traverse instructions in basic block.
for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();		for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
MI != End;) {		MI != End;) {
MachineInstr &I1 = *MI++;		MachineInstr &I1 = *MI++;

if (I1.isDebugValue())		if (I1.isDebugInstr())
continue;		continue;

// Don't combine a TFR whose user could be newified (instructions that		// Don't combine a TFR whose user could be newified (instructions that
// define double registers can not be newified - Programmer's Ref Manual		// define double registers can not be newified - Programmer's Ref Manual
// 5.4.2 New-value stores).		// 5.4.2 New-value stores).
if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&I1))		if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&I1))
continue;		continue;

Show All 20 Lines
/// findPairable - Returns an instruction that can be merged with \p I1 into a		/// findPairable - Returns an instruction that can be merged with \p I1 into a
/// COMBINE instruction or 0 if no such instruction can be found. Returns true		/// COMBINE instruction or 0 if no such instruction can be found. Returns true
/// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1		/// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
/// false if the combine must be inserted at the returned instruction.		/// false if the combine must be inserted at the returned instruction.
MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,		MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
bool &DoInsertAtI1,		bool &DoInsertAtI1,
bool AllowC64) {		bool AllowC64) {
MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));		MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
while (I2 != I1.getParent()->end() && I2->isDebugValue())		while (I2 != I1.getParent()->end() && I2->isDebugInstr())
++I2;		++I2;

unsigned I1DestReg = I1.getOperand(0).getReg();		unsigned I1DestReg = I1.getOperand(0).getReg();

for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;		for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
++I2) {		++I2) {
// Bail out early if we see a second definition of I1DestReg.		// Bail out early if we see a second definition of I1DestReg.
if (I2->modifiesRegister(I1DestReg, TRI))		if (I2->modifiesRegister(I1DestReg, TRI))
▲ Show 20 Lines • Show All 349 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

Show First 20 Lines • Show All 361 Lines • ▼ Show 20 Lines	bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
if (!B)		if (!B)
return true;		return true;
if (B->isEHPad() \|\| B->hasAddressTaken())		if (B->isEHPad() \|\| B->hasAddressTaken())
return false;		return false;
if (B->succ_size() == 0)		if (B->succ_size() == 0)
return false;		return false;

for (auto &MI : *B) {		for (auto &MI : *B) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
if (MI.isConditionalBranch())		if (MI.isConditionalBranch())
return false;		return false;
unsigned Opc = MI.getOpcode();		unsigned Opc = MI.getOpcode();
bool IsJMP = (Opc == Hexagon::J2_jump);		bool IsJMP = (Opc == Hexagon::J2_jump);
if (!isPredicableStore(&MI) && !IsJMP && !isSafeToSpeculate(&MI))		if (!isPredicableStore(&MI) && !IsJMP && !isSafeToSpeculate(&MI))
return false;		return false;
// Look for predicate registers defined by this instruction. It's ok		// Look for predicate registers defined by this instruction. It's ok
▲ Show 20 Lines • Show All 697 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines	bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
LPR.addLiveOuts(B);		LPR.addLiveOuts(B);
auto IsLive = [&LPR,this] (unsigned Reg) -> bool {		auto IsLive = [&LPR,this] (unsigned Reg) -> bool {
for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S)		for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S)
if (LPR.contains(*S))		if (LPR.contains(*S))
return true;		return true;
return false;		return false;
};		};
for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {		for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
// This isn't 100% accurate, but it's safe.		// This isn't 100% accurate, but it's safe.
// It won't detect (as a kill) a case like this		// It won't detect (as a kill) a case like this
// r0 = add r0, 1 <-- r0 should be "killed"		// r0 = add r0, 1 <-- r0 should be "killed"
// ... = r0		// ... = r0
for (MachineOperand &Op : I->operands()) {		for (MachineOperand &Op : I->operands()) {
if (!Op.isReg() \|\| !Op.isUse())		if (!Op.isReg() \|\| !Op.isUse())
continue;		continue;
Show All 24 Lines

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines	return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));		isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
}		}

/// Calculate number of instructions excluding the debug instructions.		/// Calculate number of instructions excluding the debug instructions.
static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,		static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
MachineBasicBlock::const_instr_iterator MIE) {		MachineBasicBlock::const_instr_iterator MIE) {
unsigned Count = 0;		unsigned Count = 0;
for (; MIB != MIE; ++MIB) {		for (; MIB != MIE; ++MIB) {
if (!MIB->isDebugValue())		if (!MIB->isDebugInstr())
++Count;		++Count;
}		}
return Count;		return Count;
}		}

/// Find the hardware loop instruction used to set-up the specified loop.		/// Find the hardware loop instruction used to set-up the specified loop.
/// On Hexagon, we have two instructions used to set-up the hardware loop		/// On Hexagon, we have two instructions used to set-up the hardware loop
/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions		/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Lines	do {
if (I->isEHLabel())		if (I->isEHLabel())
// Don't analyze EH branches.		// Don't analyze EH branches.
return true;		return true;
} while (I != MBB.instr_begin());		} while (I != MBB.instr_begin());

I = MBB.instr_end();		I = MBB.instr_end();
--I;		--I;

while (I->isDebugValue()) {		while (I->isDebugInstr()) {
if (I == MBB.instr_begin())		if (I == MBB.instr_begin())
return false;		return false;
--I;		--I;
}		}

bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&		bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
I->getOperand(0).isMBB();		I->getOperand(0).isMBB();
// Delete the J2_jump if it's equivalent to a fall-through.		// Delete the J2_jump if it's equivalent to a fall-through.
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines	unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));		DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
// Only removing branches from end of MBB.		// Only removing branches from end of MBB.
if (!I->isBranch())		if (!I->isBranch())
return Count;		return Count;
if (Count && (I->getOpcode() == Hexagon::J2_jump))		if (Count && (I->getOpcode() == Hexagon::J2_jump))
llvm_unreachable("Malformed basic block: unconditional branch not last");		llvm_unreachable("Malformed basic block: unconditional branch not last");
MBB.erase(&MBB.back());		MBB.erase(&MBB.back());
I = MBB.end();		I = MBB.end();
▲ Show 20 Lines • Show All 1,047 Lines • ▼ Show 20 Lines	bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,		const MachineBasicBlock *MBB,
const MachineFunction &MF) const {		const MachineFunction &MF) const {
// Debug info is never a scheduling boundary. It's necessary to be explicit		// Debug info is never a scheduling boundary. It's necessary to be explicit
// due to the special treatment of IT instructions below, otherwise a		// due to the special treatment of IT instructions below, otherwise a
// dbg_value followed by an IT will result in the IT instruction being		// dbg_value followed by an IT will result in the IT instruction being
// considered a scheduling hazard, which is wrong. It should be the actual		// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is		// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.		// when debug info is not present.
if (MI.isDebugValue())		if (MI.isDebugInstr())
return false;		return false;

// Throwing call is a boundary.		// Throwing call is a boundary.
if (MI.isCall()) {		if (MI.isCall()) {
// Don't mess around with no return calls.		// Don't mess around with no return calls.
if (doesNotReturn(MI))		if (doesNotReturn(MI))
return true;		return true;
// If any of the block's successors is a landing pad, this could be a		// If any of the block's successors is a landing pad, this could be a
▲ Show 20 Lines • Show All 1,521 Lines • ▼ Show 20 Lines	do {
--I;		--I;
if (I->isEHLabel())		if (I->isEHLabel())
return Jumpers;		return Jumpers;
} while (I != MBB.instr_begin());		} while (I != MBB.instr_begin());

I = MBB.instr_end();		I = MBB.instr_end();
--I;		--I;

while (I->isDebugValue()) {		while (I->isDebugInstr()) {
if (I == MBB.instr_begin())		if (I == MBB.instr_begin())
return Jumpers;		return Jumpers;
--I;		--I;
}		}
if (!isUnpredicatedTerminator(*I))		if (!isUnpredicatedTerminator(*I))
return Jumpers;		return Jumpers;

// Get the last instruction in the block.		// Get the last instruction in the block.
▲ Show 20 Lines • Show All 1,020 Lines • ▼ Show 20 Lines	short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
return Hexagon::getRegForm(MI.getOpcode());		return Hexagon::getRegForm(MI.getOpcode());
}		}

// Return the number of bytes required to encode the instruction.		// Return the number of bytes required to encode the instruction.
// Hexagon instructions are fixed length, 4 bytes, unless they		// Hexagon instructions are fixed length, 4 bytes, unless they
// use a constant extender, which requires another 4 bytes.		// use a constant extender, which requires another 4 bytes.
// For debug instructions and prolog labels, return 0.		// For debug instructions and prolog labels, return 0.
unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {		unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
if (MI.isDebugValue() \|\| MI.isPosition())		if (MI.isDebugInstr() \|\| MI.isPosition())
return 0;		return 0;

unsigned Size = MI.getDesc().getSize();		unsigned Size = MI.getDesc().getSize();
if (!Size)		if (!Size)
// Assume the default insn size in case it cannot be determined		// Assume the default insn size in case it cannot be determined
// for whatever reason.		// for whatever reason.
Size = HEXAGON_INSTR_SIZE;		Size = HEXAGON_INSTR_SIZE;

▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Lines	if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
return false;		return false;
}		}
}		}

// Walk the instructions after the compare (predicate def) to the jump,		// Walk the instructions after the compare (predicate def) to the jump,
// and satisfy the following conditions.		// and satisfy the following conditions.
++II;		++II;
for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {		for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
if (localII->isDebugValue())		if (localII->isDebugInstr())
continue;		continue;

// Check 1.		// Check 1.
// If "common" checks fail, bail out.		// If "common" checks fail, bail out.
if (!commonChecksToProhibitNewValueJump(optLocation, localII))		if (!commonChecksToProhibitNewValueJump(optLocation, localII))
return false;		return false;

// Check 2.		// Check 2.
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines	for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
MachineBasicBlock *jmpTarget = nullptr;		MachineBasicBlock *jmpTarget = nullptr;
bool afterRA = false;		bool afterRA = false;
bool isSecondOpReg = false;		bool isSecondOpReg = false;
bool isSecondOpNewified = false;		bool isSecondOpNewified = false;
// Traverse the basic block - bottom up		// Traverse the basic block - bottom up
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();		for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
MII != E;) {		MII != E;) {
MachineInstr &MI = *--MII;		MachineInstr &MI = *--MII;
if (MI.isDebugValue()) {		if (MI.isDebugInstr()) {
continue;		continue;
}		}

if ((nvjCount == 0) \|\| (nvjCount > -1 && nvjCount <= nvjGenerated))		if ((nvjCount == 0) \|\| (nvjCount > -1 && nvjCount <= nvjGenerated))
break;		break;

DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");		DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");

▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines	if (I->isVolatile())
return true;		return true;
return false;		return false;
}		}

bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {		bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
if (MI->mayLoad() \|\| MI->mayStore())		if (MI->mayLoad() \|\| MI->mayStore())
if (MemRefsFixed \|\| isVolatileInstr(MI))		if (MemRefsFixed \|\| isVolatileInstr(MI))
return true;		return true;
if (MI->isDebugValue())		if (MI->isDebugInstr())
return false;		return false;

unsigned Opc = MI->getOpcode();		unsigned Opc = MI->getOpcode();
switch (Opc) {		switch (Opc) {
default:		default:
return true;		return true;

case TargetOpcode::PHI:		case TargetOpcode::PHI:
▲ Show 20 Lines • Show All 1,063 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Show First 20 Lines • Show All 1,031 Lines • ▼ Show 20 Lines	void HexagonPacketizerList::initPacketizerState() {
GlueAllocframeStore = false;		GlueAllocframeStore = false;
FoundSequentialDependence = false;		FoundSequentialDependence = false;
ChangedOffset = INT64_MAX;		ChangedOffset = INT64_MAX;
}		}

// Ignore bundling of pseudo instructions.		// Ignore bundling of pseudo instructions.
bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,		bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
const MachineBasicBlock *) {		const MachineBasicBlock *) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
return true;		return true;

if (MI.isCFIInstruction())		if (MI.isCFIInstruction())
return false;		return false;

// We must print out inline assembly.		// We must print out inline assembly.
if (MI.isInlineAsm())		if (MI.isInlineAsm())
return false;		return false;
▲ Show 20 Lines • Show All 814 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp

Show First 20 Lines • Show All 887 Lines • ▼ Show 20 Lines	void DataFlowGraph::build(unsigned Options) {

if (MF.empty())		if (MF.empty())
return;		return;

for (MachineBasicBlock &B : MF) {		for (MachineBasicBlock &B : MF) {
NodeAddr<BlockNode*> BA = newBlock(Func, &B);		NodeAddr<BlockNode*> BA = newBlock(Func, &B);
BlockNodes.insert(std::make_pair(&B, BA));		BlockNodes.insert(std::make_pair(&B, BA));
for (MachineInstr &I : B) {		for (MachineInstr &I : B) {
if (I.isDebugValue())		if (I.isDebugInstr())
continue;		continue;
buildStmt(BA, I);		buildStmt(BA, I);
}		}
}		}

NodeAddr<BlockNode> EA = Func.Addr->getEntryBlock(this);		NodeAddr<BlockNode> EA = Func.Addr->getEntryBlock(this);
NodeList Blocks = Func.Addr->members(*this);		NodeList Blocks = Func.Addr->members(*this);

▲ Show 20 Lines • Show All 950 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp

Show First 20 Lines • Show All 874 Lines • ▼ Show 20 Lines	void Liveness::resetKills(MachineBasicBlock *B) {

BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());		BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
CopyLiveIns(B, LiveIn);		CopyLiveIns(B, LiveIn);
for (auto SI : B->successors())		for (auto SI : B->successors())
CopyLiveIns(SI, Live);		CopyLiveIns(SI, Live);

for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {		for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
MachineInstr MI = &I;		MachineInstr MI = &I;
if (MI->isDebugValue())		if (MI->isDebugInstr())
continue;		continue;

MI->clearKillInfo();		MI->clearKillInfo();
for (auto &Op : MI->operands()) {		for (auto &Op : MI->operands()) {
// An implicit def of a super-register may not necessarily start a		// An implicit def of a super-register may not necessarily start a
// live range of it, since an implicit use could be used to keep parts		// live range of it, since an implicit use could be used to keep parts
// of it live. Instead of analyzing the implicit operands, ignore		// of it live. Instead of analyzing the implicit operands, ignore
// implicit defs.		// implicit defs.
▲ Show 20 Lines • Show All 229 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines	bool Filler::findDelayInstr(MachineBasicBlock &MBB,
insertDefsUses(Slot, RegDefs, RegUses);		insertDefsUses(Slot, RegDefs, RegUses);

bool SawLoad = false;		bool SawLoad = false;
bool SawStore = false;		bool SawStore = false;

for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();		for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
I != MBB.instr_rend(); ++I) {		I != MBB.instr_rend(); ++I) {
// skip debug value		// skip debug value
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

// Convert to forward iterator.		// Convert to forward iterator.
MachineBasicBlock::instr_iterator FI = I.getReverse();		MachineBasicBlock::instr_iterator FI = I.getReverse();

if (I->hasUnmodeledSideEffects() \|\| I->isInlineAsm() \|\| I->isLabel() \|\|		if (I->hasUnmodeledSideEffects() \|\| I->isInlineAsm() \|\| I->isLabel() \|\|
FI == LastFiller \|\| I->isPseudo())		FI == LastFiller \|\| I->isPseudo())
break;		break;
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp

Show First 20 Lines • Show All 567 Lines • ▼ Show 20 Lines	bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
// Iterator to current instruction being considered.		// Iterator to current instruction being considered.
MachineBasicBlock::iterator Instruction = MBB.end();		MachineBasicBlock::iterator Instruction = MBB.end();

// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
while (Instruction != MBB.begin()) {		while (Instruction != MBB.begin()) {
--Instruction;		--Instruction;

// Skip over debug values.		// Skip over debug instructions.
if (Instruction->isDebugValue())		if (Instruction->isDebugInstr())
continue;		continue;

// Working from the bottom, when we see a non-terminator		// Working from the bottom, when we see a non-terminator
// instruction, we're done.		// instruction, we're done.
if (!isUnpredicatedTerminator(*Instruction))		if (!isUnpredicatedTerminator(*Instruction))
break;		break;

// A terminator that isn't a branch can't easily be handled		// A terminator that isn't a branch can't easily be handled
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines	unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::iterator Instruction = MBB.end();		MachineBasicBlock::iterator Instruction = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (Instruction != MBB.begin()) {		while (Instruction != MBB.begin()) {
--Instruction;		--Instruction;
if (Instruction->isDebugValue())		if (Instruction->isDebugInstr())
continue;		continue;
if (Instruction->getOpcode() != Lanai::BT &&		if (Instruction->getOpcode() != Lanai::BT &&
Instruction->getOpcode() != Lanai::BRCC) {		Instruction->getOpcode() != Lanai::BRCC) {
break;		break;
}		}

// Remove the branch.		// Remove the branch.
Instruction->eraseFromParent();		Instruction->eraseFromParent();
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp

Show First 20 Lines • Show All 337 Lines • ▼ Show 20 Lines	MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr(

while (First != Last) {		while (First != Last) {
Decrement ? --First : ++First;		Decrement ? --First : ++First;

if (First == Last)		if (First == Last)
break;		break;

// Skip over debug instructions		// Skip over debug instructions
if (First->isDebugValue())		if (First->isDebugInstr())
continue;		continue;

if (isSuitableAluInstr(IsSpls, First, Base, Offset)) {		if (isSuitableAluInstr(IsSpls, First, Base, Offset)) {
return First;		return First;
}		}

// Usage of the base or offset register is not a form suitable for merging.		// Usage of the base or offset register is not a form suitable for merging.
if (First != Last) {		if (First != Last) {
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines	unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (I->getOpcode() != MSP430::JMP &&		if (I->getOpcode() != MSP430::JMP &&
I->getOpcode() != MSP430::JCC &&		I->getOpcode() != MSP430::JCC &&
I->getOpcode() != MSP430::Br &&		I->getOpcode() != MSP430::Br &&
I->getOpcode() != MSP430::Bm)		I->getOpcode() != MSP430::Bm)
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&FBB,		MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,		SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {		bool AllowModify) const {
// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

// Working from the bottom, when we see a non-terminator		// Working from the bottom, when we see a non-terminator
// instruction, we're done.		// instruction, we're done.
if (!isUnpredicatedTerminator(*I))		if (!isUnpredicatedTerminator(*I))
break;		break;

// A terminator that isn't a branch can't easily be handled		// A terminator that isn't a branch can't easily be handled
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {

if (MI->isDebugValue()) {		if (MI->isDebugValue()) {
SmallString<128> Str;		SmallString<128> Str;
raw_svector_ostream OS(Str);		raw_svector_ostream OS(Str);

PrintDebugValueComment(MI, OS);		PrintDebugValueComment(MI, OS);
return;		return;
}		}
		if (MI->isDebugLabel())
		return;

// If we just ended a constant pool, mark it as such.		// If we just ended a constant pool, mark it as such.
if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {		if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);		OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
InConstantPool = false;		InConstantPool = false;
}		}
if (Opc == Mips::CONSTPOOL_ENTRY) {		if (Opc == Mips::CONSTPOOL_ENTRY) {
// CONSTPOOL_ENTRY - This instruction represents a floating		// CONSTPOOL_ENTRY - This instruction represents a floating
▲ Show 20 Lines • Show All 1,081 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp

Show First 20 Lines • Show All 655 Lines • ▼ Show 20 Lines	initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {

// Now go back through the instructions and build up our data structures.		// Now go back through the instructions and build up our data structures.
for (MachineBasicBlock &MBB : *MF) {		for (MachineBasicBlock &MBB : *MF) {
// If this block doesn't fall through into the next MBB, then this is		// If this block doesn't fall through into the next MBB, then this is
// 'water' that a constant pool island could be placed.		// 'water' that a constant pool island could be placed.
if (!BBHasFallthrough(&MBB))		if (!BBHasFallthrough(&MBB))
WaterList.push_back(&MBB);		WaterList.push_back(&MBB);
for (MachineInstr &MI : MBB) {		for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

int Opc = MI.getOpcode();		int Opc = MI.getOpcode();
if (MI.isBranch()) {		if (MI.isBranch()) {
bool isCond = false;		bool isCond = false;
unsigned Bits = 0;		unsigned Bits = 0;
unsigned Scale = 1;		unsigned Scale = 1;
int UOpc = Opc;		int UOpc = Opc;
▲ Show 20 Lines • Show All 1,016 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

	Show First 20 Lines • Show All 673 Lines • ▼ Show 20 Lines
	bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,			bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
	RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,			RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
	IterTy &Filler) const {			IterTy &Filler) const {
	for (IterTy I = Begin; I != End;) {			for (IterTy I = Begin; I != End;) {
	IterTy CurrI = I;			IterTy CurrI = I;
	++I;			++I;

	// skip debug value			// skip debug value
	if (CurrI->isDebugValue())			if (CurrI->isDebugInstr())
	continue;			continue;

	if (terminateSearch(*CurrI))			if (terminateSearch(*CurrI))
	break;			break;

	assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&			assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
	"Cannot put calls, returns or branches in delay slot.");			"Cannot put calls, returns or branches in delay slot.");

	▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines	unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,

MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();		MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
unsigned removed = 0;		unsigned removed = 0;

// Up to 2 branches are removed.		// Up to 2 branches are removed.
// Note that indirect branches are not removed.		// Note that indirect branches are not removed.
while (I != REnd && removed < 2) {		while (I != REnd && removed < 2) {
// Skip past debug instructions.		// Skip past debug instructions.
if (I->isDebugValue()) {		if (I->isDebugInstr()) {
++I;		++I;
continue;		continue;
}		}
if (!getAnalyzableBrOpc(I->getOpcode()))		if (!getAnalyzableBrOpc(I->getOpcode()))
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
I = MBB.rbegin();		I = MBB.rbegin();
Show All 15 Lines

MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(		MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB,		MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB,
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,		SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
SmallVectorImpl<MachineInstr *> &BranchInstrs) const {		SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();		MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();

// Skip all the debug instructions.		// Skip all the debug instructions.
while (I != REnd && I->isDebugValue())		while (I != REnd && I->isDebugInstr())
++I;		++I;

if (I == REnd \|\| !isUnpredicatedTerminator(*I)) {		if (I == REnd \|\| !isUnpredicatedTerminator(*I)) {
// This block ends with no branches (it just falls through to its succ).		// This block ends with no branches (it just falls through to its succ).
// Leave TBB/FBB null.		// Leave TBB/FBB null.
TBB = FBB = nullptr;		TBB = FBB = nullptr;
return BT_NoBranch;		return BT_NoBranch;
}		}

MachineInstr LastInst = &I;		MachineInstr LastInst = &I;
unsigned LastOpc = LastInst->getOpcode();		unsigned LastOpc = LastInst->getOpcode();
BranchInstrs.push_back(LastInst);		BranchInstrs.push_back(LastInst);

// Not an analyzable branch (e.g., indirect jump).		// Not an analyzable branch (e.g., indirect jump).
if (!getAnalyzableBrOpc(LastOpc))		if (!getAnalyzableBrOpc(LastOpc))
return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;		return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;

// Get the second to last instruction in the block.		// Get the second to last instruction in the block.
unsigned SecondLastOpc = 0;		unsigned SecondLastOpc = 0;
MachineInstr *SecondLastInst = nullptr;		MachineInstr *SecondLastInst = nullptr;

// Skip past any debug instruction to see if the second last actual		// Skip past any debug instruction to see if the second last actual
// is a branch.		// is a branch.
++I;		++I;
while (I != REnd && I->isDebugValue())		while (I != REnd && I->isDebugInstr())
++I;		++I;

if (I != REnd) {		if (I != REnd) {
SecondLastInst = &*I;		SecondLastInst = &*I;
SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());		SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());

// Not an analyzable branch (must be an indirect jump).		// Not an analyzable branch (must be an indirect jump).
if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)		if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
▲ Show 20 Lines • Show All 442 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines	static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {

llvm_unreachable("This instruction does not have an MBB operand.");		llvm_unreachable("This instruction does not have an MBB operand.");
}		}

// Traverse the list of instructions backwards until a non-debug instruction is		// Traverse the list of instructions backwards until a non-debug instruction is
// found or it reaches E.		// found or it reaches E.
static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {		static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
for (; B != E; ++B)		for (; B != E; ++B)
if (!B->isDebugValue())		if (!B->isDebugInstr())
return B;		return B;

return E;		return E;
}		}

// Split MBB if it has two direct jumps/branches.		// Split MBB if it has two direct jumps/branches.
void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {		void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
ReverseIter End = MBB->rend();		ReverseIter End = MBB->rend();
▲ Show 20 Lines • Show All 492 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines	bool processBlock(MachineBasicBlock &ReturnMBB) {
if (J->isIndirectBranch()) {		if (J->isIndirectBranch()) {
if (ReturnMBB.hasAddressTaken())		if (ReturnMBB.hasAddressTaken())
OtherReference = true;		OtherReference = true;
} else		} else
for (unsigned i = 0; i < J->getNumOperands(); ++i)		for (unsigned i = 0; i < J->getNumOperands(); ++i)
if (J->getOperand(i).isMBB() &&		if (J->getOperand(i).isMBB() &&
J->getOperand(i).getMBB() == &ReturnMBB)		J->getOperand(i).getMBB() == &ReturnMBB)
OtherReference = true;		OtherReference = true;
} else if (!J->isTerminator() && !J->isDebugValue())		} else if (!J->isTerminator() && !J->isDebugInstr())
break;		break;

if (J == (*PI)->begin())		if (J == (*PI)->begin())
break;		break;

--J;		--J;
}		}

▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Lines
/// instructions that wouldn't terminate the dispatch group that would cause a		/// instructions that wouldn't terminate the dispatch group that would cause a
/// pipeline flush.		/// pipeline flush.
ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::		ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
getHazardType(SUnit *SU, int Stalls) {		getHazardType(SUnit *SU, int Stalls) {
assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");		assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");

MachineInstr *MI = SU->getInstr();		MachineInstr *MI = SU->getInstr();

if (MI->isDebugValue())		if (MI->isDebugInstr())
return NoHazard;		return NoHazard;

unsigned Opcode = MI->getOpcode();		unsigned Opcode = MI->getOpcode();
bool isFirst, isSingle, isCracked, isLoad, isStore;		bool isFirst, isSingle, isCracked, isLoad, isStore;
PPCII::PPC970_Unit InstrType =		PPCII::PPC970_Unit InstrType =
GetInstrType(Opcode, isFirst, isSingle, isCracked,		GetInstrType(Opcode, isFirst, isSingle, isCracked,
isLoad, isStore);		isLoad, isStore);
if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;		if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines	getHazardType(SUnit *SU, int Stalls) {
}		}

return NoHazard;		return NoHazard;
}		}

void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {		void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
MachineInstr *MI = SU->getInstr();		MachineInstr *MI = SU->getInstr();

if (MI->isDebugValue())		if (MI->isDebugInstr())
return;		return;

unsigned Opcode = MI->getOpcode();		unsigned Opcode = MI->getOpcode();
bool isFirst, isSingle, isCracked, isLoad, isStore;		bool isFirst, isSingle, isCracked, isLoad, isStore;
PPCII::PPC970_Unit InstrType =		PPCII::PPC970_Unit InstrType =
GetInstrType(Opcode, isFirst, isSingle, isCracked,		GetInstrType(Opcode, isFirst, isSingle, isCracked,
isLoad, isStore);		isLoad, isStore);
if (InstrType == PPCII::PPC970_Pseudo) return;		if (InstrType == PPCII::PPC970_Pseudo) return;
Show All 37 Lines

llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines	if (ConvertRegReg) {
// into reg/imm instructions. FIXME: This is expensive, control it with		// into reg/imm instructions. FIXME: This is expensive, control it with
// an option.		// an option.
bool SomethingChanged = false;		bool SomethingChanged = false;
do {		do {
NumFixedPointIterations++;		NumFixedPointIterations++;
SomethingChanged = false;		SomethingChanged = false;
for (MachineBasicBlock &MBB : *MF) {		for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {		for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

if (TII->convertToImmediateForm(MI)) {		if (TII->convertToImmediateForm(MI)) {
// We don't erase anything in case the def has other uses. Let DCE		// We don't erase anything in case the def has other uses. Let DCE
// remove it if it can be removed.		// remove it if it can be removed.
DEBUG(dbgs() << "Converted instruction to imm form: ");		DEBUG(dbgs() << "Converted instruction to imm form: ");
DEBUG(MI.dump());		DEBUG(MI.dump());
NumConvertedToImmediateForm++;		NumConvertedToImmediateForm++;
Show All 12 Lines	for (MachineInstr &MI : MBB) {
// If the previous instruction was marked for elimination,		// If the previous instruction was marked for elimination,
// remove it now.		// remove it now.
if (ToErase) {		if (ToErase) {
ToErase->eraseFromParent();		ToErase->eraseFromParent();
ToErase = nullptr;		ToErase = nullptr;
}		}

// Ignore debug instructions.		// Ignore debug instructions.
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

// Per-opcode peepholes.		// Per-opcode peepholes.
switch (MI.getOpcode()) {		switch (MI.getOpcode()) {

default:		default:
break;		break;

▲ Show 20 Lines • Show All 1,018 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

	Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
	// a full vector register, recording various characteristics of the			// a full vector register, recording various characteristics of the
	// instructions there.			// instructions there.
	bool PPCVSXSwapRemoval::gatherVectorInstructions() {			bool PPCVSXSwapRemoval::gatherVectorInstructions() {
	bool RelevantFunction = false;			bool RelevantFunction = false;

	for (MachineBasicBlock &MBB : *MF) {			for (MachineBasicBlock &MBB : *MF) {
	for (MachineInstr &MI : MBB) {			for (MachineInstr &MI : MBB) {

	if (MI.isDebugValue())			if (MI.isDebugInstr())
	continue;			continue;

	bool RelevantInstr = false;			bool RelevantInstr = false;
	bool Partial = false;			bool Partial = false;

	for (const MachineOperand &MO : MI.operands()) {			for (const MachineOperand &MO : MI.operands()) {
	if (!MO.isReg())			if (!MO.isReg())
	continue;			continue;
	▲ Show 20 Lines • Show All 783 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines	Filler::findDelayInstr(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I = slot;		MachineBasicBlock::iterator I = slot;

while (!done) {		while (!done) {
done = (I == MBB.begin());		done = (I == MBB.begin());

if (!done)		if (!done)
--I;		--I;

// skip debug value		// skip debug instruction
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

if (I->hasUnmodeledSideEffects() \|\| I->isInlineAsm() \|\| I->isPosition() \|\|		if (I->hasUnmodeledSideEffects() \|\| I->isInlineAsm() \|\| I->isPosition() \|\|
I->hasDelaySlot() \|\| I->isBundledWithSucc())		I->hasDelaySlot() \|\| I->isBundledWithSucc())
break;		break;

if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {		if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
insertDefsUses(I, RegDefs, RegUses);		insertDefsUses(I, RegDefs, RegUses);
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines	unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;

if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

if (I->getOpcode() != SP::BA		if (I->getOpcode() != SP::BA
&& I->getOpcode() != SP::BCOND		&& I->getOpcode() != SP::BCOND
&& I->getOpcode() != SP::FBCOND)		&& I->getOpcode() != SP::FBCOND)
break; // Not a branch		break; // Not a branch

I->eraseFromParent();		I->eraseFromParent();
▲ Show 20 Lines • Show All 219 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp

Show First 20 Lines • Show All 383 Lines • ▼ Show 20 Lines	bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
bool AllowModify) const {		bool AllowModify) const {
// Most of the code and comments here are boilerplate.		// Most of the code and comments here are boilerplate.

// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

// Working from the bottom, when we see a non-terminator instruction, we're		// Working from the bottom, when we see a non-terminator instruction, we're
// done.		// done.
if (!isUnpredicatedTerminator(*I))		if (!isUnpredicatedTerminator(*I))
break;		break;

// A terminator that isn't a branch can't easily be handled by this		// A terminator that isn't a branch can't easily be handled by this
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

// Most of the code and comments here are boilerplate.		// Most of the code and comments here are boilerplate.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (!I->isBranch())		if (!I->isBranch())
break;		break;
if (!getBranchInfo(*I).Target->isMBB())		if (!getBranchInfo(*I).Target->isMBB())
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
I = MBB.end();		I = MBB.end();
▲ Show 20 Lines • Show All 1,402 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Lines	for (unsigned I = 0; I < NumBlocks; ++I) {
while (MI != End && !MI->isTerminator()) {		while (MI != End && !MI->isTerminator()) {
Block.Size += TII->getInstSizeInBytes(*MI);		Block.Size += TII->getInstSizeInBytes(*MI);
++MI;		++MI;
}		}
skipNonTerminators(Position, Block);		skipNonTerminators(Position, Block);

// Add the terminators.		// Add the terminators.
while (MI != End) {		while (MI != End) {
if (!MI->isDebugValue()) {		if (!MI->isDebugInstr()) {
assert(MI->isTerminator() && "Terminator followed by non-terminator");		assert(MI->isTerminator() && "Terminator followed by non-terminator");
Terminators.push_back(describeTerminator(*MI));		Terminators.push_back(describeTerminator(*MI));
skipTerminator(Position, Terminators.back(), false);		skipTerminator(Position, Terminators.back(), false);
++Block.NumTerminators;		++Block.NumTerminators;
}		}
++MI;		++MI;
}		}
}		}
▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp

	Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
	void SystemZPostRASchedStrategy::			void SystemZPostRASchedStrategy::
	advanceTo(MachineBasicBlock::iterator NextBegin) {			advanceTo(MachineBasicBlock::iterator NextBegin) {
	MachineBasicBlock::iterator LastEmittedMI = HazardRec->getLastEmittedMI();			MachineBasicBlock::iterator LastEmittedMI = HazardRec->getLastEmittedMI();
	MachineBasicBlock::iterator I =			MachineBasicBlock::iterator I =
	((LastEmittedMI != nullptr && LastEmittedMI->getParent() == MBB) ?			((LastEmittedMI != nullptr && LastEmittedMI->getParent() == MBB) ?
	std::next(LastEmittedMI) : MBB->begin());			std::next(LastEmittedMI) : MBB->begin());

	for (; I != NextBegin; ++I) {			for (; I != NextBegin; ++I) {
	if (I->isPosition() \|\| I->isDebugValue())			if (I->isPosition() \|\| I->isDebugInstr())
	continue;			continue;
	HazardRec->emitInstruction(&*I);			HazardRec->emitInstruction(&*I);
	}			}
	}			}

	void SystemZPostRASchedStrategy::initialize(ScheduleDAGMI *dag) {			void SystemZPostRASchedStrategy::initialize(ScheduleDAGMI *dag) {
	DEBUG(HazardRec->dumpState(););			DEBUG(HazardRec->dumpState(););
	}			}
	▲ Show 20 Lines • Show All 191 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines	static void FixEndsAtEndOfFunction(
case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;		case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;
case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;		case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;
case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;		case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
default: llvm_unreachable("unexpected return type");		default: llvm_unreachable("unexpected return type");
}		}

for (MachineBasicBlock &MBB : reverse(MF)) {		for (MachineBasicBlock &MBB : reverse(MF)) {
for (MachineInstr &MI : reverse(MBB)) {		for (MachineInstr &MI : reverse(MBB)) {
if (MI.isPosition() \|\| MI.isDebugValue())		if (MI.isPosition() \|\| MI.isDebugInstr())
continue;		continue;
if (MI.getOpcode() == WebAssembly::END_BLOCK) {		if (MI.getOpcode() == WebAssembly::END_BLOCK) {
BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));		BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));
continue;		continue;
}		}
if (MI.getOpcode() == WebAssembly::END_LOOP) {		if (MI.getOpcode() == WebAssembly::END_LOOP) {
LoopTops[&MI]->getOperand(0).setImm(int32_t(retType));		LoopTops[&MI]->getOperand(0).setImm(int32_t(retType));
continue;		continue;
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines	for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i)
UseEmpty[i] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(i));		UseEmpty[i] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(i));

// Visit each instruction in the function.		// Visit each instruction in the function.
for (MachineBasicBlock &MBB : MF) {		for (MachineBasicBlock &MBB : MF) {
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {		for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++;		MachineInstr &MI = *I++;
assert(!WebAssembly::isArgument(MI));		assert(!WebAssembly::isArgument(MI));

if (MI.isDebugValue() \|\| MI.isLabel())		if (MI.isDebugInstr() \|\| MI.isLabel())
continue;		continue;

// Replace tee instructions with tee_local. The difference is that tee		// Replace tee instructions with tee_local. The difference is that tee
// instructins have two defs, while tee_local instructions have one def		// instructins have two defs, while tee_local instructions have one def
// and an index of a local to write to.		// and an index of a local to write to.
if (WebAssembly::isTee(MI)) {		if (WebAssembly::isTee(MI)) {
assert(MFI.isVRegStackified(MI.getOperand(0).getReg()));		assert(MFI.isVRegStackified(MI.getOperand(0).getReg()));
assert(!MFI.isVRegStackified(MI.getOperand(1).getReg()));		assert(!MFI.isVRegStackified(MI.getOperand(1).getReg()));
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines	MFI.setLocal(I->second - MFI.getParams().size(),
typeForRegClass(MRI.getRegClass(Reg)));		typeForRegClass(MRI.getRegClass(Reg)));
Changed = true;		Changed = true;
}		}

#ifndef NDEBUG		#ifndef NDEBUG
// Assert that all registers have been stackified at this point.		// Assert that all registers have been stackified at this point.
for (const MachineBasicBlock &MBB : MF) {		for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {		for (const MachineInstr &MI : MBB) {
if (MI.isDebugValue() \|\| MI.isLabel())		if (MI.isDebugInstr() \|\| MI.isLabel())
continue;		continue;
for (const MachineOperand &MO : MI.explicit_operands()) {		for (const MachineOperand &MO : MI.explicit_operands()) {
assert(		assert(
(!MO.isReg() \|\| MRI.use_empty(MO.getReg()) \|\|		(!MO.isReg() \|\| MRI.use_empty(MO.getReg()) \|\|
MFI.isVRegStackified(MO.getReg())) &&		MFI.isVRegStackified(MO.getReg())) &&
"WebAssemblyExplicitLocals failed to stackify a register operand");		"WebAssemblyExplicitLocals failed to stackify a register operand");
}		}
}		}
}		}
#endif		#endif

return Changed;		return Changed;
}		}

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines	unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::instr_iterator I = MBB.instr_end();		MachineBasicBlock::instr_iterator I = MBB.instr_end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.instr_begin()) {		while (I != MBB.instr_begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (!I->isTerminator())		if (!I->isTerminator())
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
I = MBB.instr_end();		I = MBB.instr_end();
++Count;		++Count;
}		}
Show All 40 Lines

llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines

// Determine whether MI reads memory, writes memory, has side effects,		// Determine whether MI reads memory, writes memory, has side effects,
// and/or uses the stack pointer value.		// and/or uses the stack pointer value.
static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read,		static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read,
bool &Write, bool &Effects, bool &StackPointer) {		bool &Write, bool &Effects, bool &StackPointer) {
assert(!MI.isPosition());		assert(!MI.isPosition());
assert(!MI.isTerminator());		assert(!MI.isTerminator());

if (MI.isDebugValue())		if (MI.isDebugInstr())
return;		return;

// Check for loads.		// Check for loads.
if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(&AA))		if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(&AA))
Read = true;		Read = true;

// Check for stores.		// Check for stores.
if (MI.mayStore()) {		if (MI.mayStore()) {
▲ Show 20 Lines • Show All 691 Lines • ▼ Show 20 Lines	for (MachineBasicBlock &MBB : MF)
MBB.addLiveIn(WebAssembly::VALUE_STACK);		MBB.addLiveIn(WebAssembly::VALUE_STACK);
}		}

#ifndef NDEBUG		#ifndef NDEBUG
// Verify that pushes and pops are performed in LIFO order.		// Verify that pushes and pops are performed in LIFO order.
SmallVector<unsigned, 0> Stack;		SmallVector<unsigned, 0> Stack;
for (MachineBasicBlock &MBB : MF) {		for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {		for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
for (MachineOperand &MO : reverse(MI.explicit_operands())) {		for (MachineOperand &MO : reverse(MI.explicit_operands())) {
if (!MO.isReg())		if (!MO.isReg())
continue;		continue;
unsigned Reg = MO.getReg();		unsigned Reg = MO.getReg();

if (MFI.isVRegStackified(Reg)) {		if (MFI.isVRegStackified(Reg)) {
if (MO.isDef())		if (MO.isDef())
Show All 16 Lines

llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Lines	void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
if (!MaxAdjust) {		if (!MaxAdjust) {
Context.NoStackParams = true;		Context.NoStackParams = true;
return;		return;
}		}

// Skip over DEBUG_VALUE.		// Skip over DEBUG_VALUE.
// For globals in PIC mode, we can have some LEAs here. Skip them as well.		// For globals in PIC mode, we can have some LEAs here. Skip them as well.
// TODO: Extend this to something that covers more cases.		// TODO: Extend this to something that covers more cases.
while (I->getOpcode() == X86::LEA32r \|\| I->isDebugValue())		while (I->getOpcode() == X86::LEA32r \|\| I->isDebugInstr())
++I;		++I;

unsigned StackPtr = RegInfo.getStackRegister();		unsigned StackPtr = RegInfo.getStackRegister();
auto StackPtrCopyInst = MBB.end();		auto StackPtrCopyInst = MBB.end();
// SelectionDAG (but not FastISel) inserts a copy of ESP into a virtual		// SelectionDAG (but not FastISel) inserts a copy of ESP into a virtual
// register. If it's there, use that virtual register as stack pointer		// register. If it's there, use that virtual register as stack pointer
// instead. Also, we need to locate this instruction so that we can later		// instead. Also, we need to locate this instruction so that we can later
// safely ignore it while doing the conservative processing of the call chain.		// safely ignore it while doing the conservative processing of the call chain.
▲ Show 20 Lines • Show All 250 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86CmovConversion.cpp

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Lines	for (auto *MBB : Blocks) {
X86::CondCode FirstCC, FirstOppCC, MemOpCC;		X86::CondCode FirstCC, FirstOppCC, MemOpCC;
// Indicator of a non CMOVrr instruction in the current processed range.		// Indicator of a non CMOVrr instruction in the current processed range.
bool FoundNonCMOVInst = false;		bool FoundNonCMOVInst = false;
// Indicator for current processed CMOV-group if it should be skipped.		// Indicator for current processed CMOV-group if it should be skipped.
bool SkipGroup = false;		bool SkipGroup = false;

for (auto &I : *MBB) {		for (auto &I : *MBB) {
// Skip debug instructions.		// Skip debug instructions.
if (I.isDebugValue())		if (I.isDebugInstr())
continue;		continue;
X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode());		X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode());
// Check if we found a X86::CMOVrr instruction.		// Check if we found a X86::CMOVrr instruction.
if (CC != X86::COND_INVALID && (IncludeLoads \|\| !I.mayLoad())) {		if (CC != X86::COND_INVALID && (IncludeLoads \|\| !I.mayLoad())) {
if (Group.empty()) {		if (Group.empty()) {
// We found first CMOV in the range, reset flags.		// We found first CMOV in the range, reset flags.
FirstCC = CC;		FirstCC = CC;
FirstOppCC = X86::GetOppositeBranchCondition(CC);		FirstOppCC = X86::GetOppositeBranchCondition(CC);
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines	bool X86CmovConverterPass::checkForProfitableCmovCandidates(
//===--------------------------------------------------------------------===//		//===--------------------------------------------------------------------===//
for (unsigned I = 0; I < LoopIterations; ++I) {		for (unsigned I = 0; I < LoopIterations; ++I) {
DepthInfo &MaxDepth = LoopDepth[I];		DepthInfo &MaxDepth = LoopDepth[I];
for (auto *MBB : Blocks) {		for (auto *MBB : Blocks) {
// Clear physical registers Def map.		// Clear physical registers Def map.
RegDefMaps[PhyRegType].clear();		RegDefMaps[PhyRegType].clear();
for (MachineInstr &MI : *MBB) {		for (MachineInstr &MI : *MBB) {
// Skip debug instructions.		// Skip debug instructions.
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
unsigned MIDepth = 0;		unsigned MIDepth = 0;
unsigned MIDepthOpt = 0;		unsigned MIDepthOpt = 0;
bool IsCMOV = CmovInstructions.count(&MI);		bool IsCMOV = CmovInstructions.count(&MI);
for (auto &MO : MI.uses()) {		for (auto &MO : MI.uses()) {
// Checks for "isUse()" as "uses()" returns also implicit definitions.		// Checks for "isUse()" as "uses()" returns also implicit definitions.
if (!MO.isReg() \|\| !MO.isUse())		if (!MO.isReg() \|\| !MO.isUse())
continue;		continue;
▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
/// move all debug instructions to after the last CMOV instruction, making the		/// move all debug instructions to after the last CMOV instruction, making the
/// CMOV group consecutive.		/// CMOV group consecutive.
static void packCmovGroup(MachineInstr First, MachineInstr Last) {		static void packCmovGroup(MachineInstr First, MachineInstr Last) {
assert(X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID &&		assert(X86::getCondFromCMovOpc(Last->getOpcode()) != X86::COND_INVALID &&
"Last instruction in a CMOV group must be a CMOV instruction");		"Last instruction in a CMOV group must be a CMOV instruction");

SmallVector<MachineInstr *, 2> DBGInstructions;		SmallVector<MachineInstr *, 2> DBGInstructions;
for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) {		for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) {
if (I->isDebugValue())		if (I->isDebugInstr())
DBGInstructions.push_back(&*I);		DBGInstructions.push_back(&*I);
}		}

// Splice the debug instruction after the cmov group.		// Splice the debug instruction after the cmov group.
MachineBasicBlock *MBB = First->getParent();		MachineBasicBlock *MBB = First->getParent();
for (auto *MI : DBGInstructions)		for (auto *MI : DBGInstructions)
MBB->insertAfter(Last, MI->removeFromParent());		MBB->insertAfter(Last, MI->removeFromParent());
}		}
▲ Show 20 Lines • Show All 252 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

Show First 20 Lines • Show All 1,669 Lines • ▼ Show 20 Lines	void FPS::setKillFlags(MachineBasicBlock &MBB) const {
const TargetRegisterInfo &TRI =		const TargetRegisterInfo &TRI =
*MBB.getParent()->getSubtarget().getRegisterInfo();		*MBB.getParent()->getSubtarget().getRegisterInfo();
LivePhysRegs LPR(TRI);		LivePhysRegs LPR(TRI);

LPR.addLiveOuts(MBB);		LPR.addLiveOuts(MBB);

for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();		for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {		I != E; ++I) {
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

std::bitset<8> Defs;		std::bitset<8> Defs;
SmallVector<MachineOperand *, 2> Uses;		SmallVector<MachineOperand *, 2> Uses;
MachineInstr &MI = *I;		MachineInstr &MI = *I;

for (auto &MO : I->operands()) {		for (auto &MO : I->operands()) {
if (!MO.isReg())		if (!MO.isReg())
Show All 22 Lines

llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Show First 20 Lines • Show All 3,019 Lines • ▼ Show 20 Lines	if (ObjectSize == 0)
SortingObjects[Obj].ObjectSize = 4;		SortingObjects[Obj].ObjectSize = 4;
else		else
SortingObjects[Obj].ObjectSize = ObjectSize;		SortingObjects[Obj].ObjectSize = ObjectSize;
}		}

// Count the number of uses for each object.		// Count the number of uses for each object.
for (auto &MBB : MF) {		for (auto &MBB : MF) {
for (auto &MI : MBB) {		for (auto &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;
for (const MachineOperand &MO : MI.operands()) {		for (const MachineOperand &MO : MI.operands()) {
// Check to see if it's a local stack symbol.		// Check to see if it's a local stack symbol.
if (!MO.isFI())		if (!MO.isFI())
continue;		continue;
int Index = MO.getIndex();		int Index = MO.getIndex();
// Check to see if it falls within our range, and is tagged		// Check to see if it falls within our range, and is tagged
// to require ordering.		// to require ordering.
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 27,760 Lines • ▼ Show 20 Lines	X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
DenseMap<unsigned, SmallVector<MachineBasicBlock *, 2>> CallSiteNumToLPad;		DenseMap<unsigned, SmallVector<MachineBasicBlock *, 2>> CallSiteNumToLPad;
unsigned MaxCSNum = 0;		unsigned MaxCSNum = 0;
for (auto &MBB : *MF) {		for (auto &MBB : *MF) {
if (!MBB.isEHPad())		if (!MBB.isEHPad())
continue;		continue;

MCSymbol *Sym = nullptr;		MCSymbol *Sym = nullptr;
for (const auto &MI : MBB) {		for (const auto &MI : MBB) {
if (MI.isDebugValue())		if (MI.isDebugInstr())
continue;		continue;

assert(MI.isEHLabel() && "expected EH_LABEL");		assert(MI.isEHLabel() && "expected EH_LABEL");
Sym = MI.getOperand(0).getMCSymbol();		Sym = MI.getOperand(0).getMCSymbol();
break;		break;
}		}

if (!MF->hasCallSiteLandingPad(Sym))		if (!MF->hasCallSiteLandingPad(Sym))
▲ Show 20 Lines • Show All 11,999 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 4,334 Lines • ▼ Show 20 Lines	for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
SeenDef = true;		SeenDef = true;
}		}
}		}

if (SeenDef)		if (SeenDef)
// This instruction defines EFLAGS, no need to look any further.		// This instruction defines EFLAGS, no need to look any further.
return true;		return true;
++Iter;		++Iter;
// Skip over DBG_VALUE.		// Skip over debug instructions.
while (Iter != E && Iter->isDebugValue())		while (Iter != E && Iter->isDebugInstr())
++Iter;		++Iter;
}		}

// It is safe to clobber EFLAGS at the end of a block of no successor has it		// It is safe to clobber EFLAGS at the end of a block of no successor has it
// live in.		// live in.
if (Iter == E) {		if (Iter == E) {
for (MachineBasicBlock *S : MBB.successors())		for (MachineBasicBlock *S : MBB.successors())
if (S->isLiveIn(X86::EFLAGS))		if (S->isLiveIn(X86::EFLAGS))
return false;		return false;
return true;		return true;
}		}

MachineBasicBlock::iterator B = MBB.begin();		MachineBasicBlock::iterator B = MBB.begin();
Iter = I;		Iter = I;
for (unsigned i = 0; i < 4; ++i) {		for (unsigned i = 0; i < 4; ++i) {
// If we make it to the beginning of the block, it's safe to clobber		// If we make it to the beginning of the block, it's safe to clobber
// EFLAGS iff EFLAGS is not live-in.		// EFLAGS iff EFLAGS is not live-in.
if (Iter == B)		if (Iter == B)
return !MBB.isLiveIn(X86::EFLAGS);		return !MBB.isLiveIn(X86::EFLAGS);

--Iter;		--Iter;
// Skip over DBG_VALUE.		// Skip over debug instructions.
while (Iter != B && Iter->isDebugValue())		while (Iter != B && Iter->isDebugInstr())
--Iter;		--Iter;

bool SawKill = false;		bool SawKill = false;
for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {		for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
MachineOperand &MO = Iter->getOperand(j);		MachineOperand &MO = Iter->getOperand(j);
// A register mask may clobber EFLAGS, but we should still look for a		// A register mask may clobber EFLAGS, but we should still look for a
// live EFLAGS def.		// live EFLAGS def.
if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))		if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
▲ Show 20 Lines • Show All 1,873 Lines • ▼ Show 20 Lines
void X86InstrInfo::replaceBranchWithTailCall(		void X86InstrInfo::replaceBranchWithTailCall(
MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,		MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
const MachineInstr &TailCall) const {		const MachineInstr &TailCall) const {
assert(canMakeTailCallConditional(BranchCond, TailCall));		assert(canMakeTailCallConditional(BranchCond, TailCall));

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (!I->isBranch())		if (!I->isBranch())
assert(0 && "Can't find the branch to replace!");		assert(0 && "Can't find the branch to replace!");

X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());		X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
assert(BranchCond.size() == 1);		assert(BranchCond.size() == 1);
if (CC != BranchCond[0].getImm())		if (CC != BranchCond[0].getImm())
continue;		continue;
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	bool X86InstrInfo::AnalyzeBranchImpl(
SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {		SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {

// Start from the bottom of the block and work up, examining the		// Start from the bottom of the block and work up, examining the
// terminator instructions.		// terminator instructions.
MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
MachineBasicBlock::iterator UnCondBrIter = MBB.end();		MachineBasicBlock::iterator UnCondBrIter = MBB.end();
while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;

// Working from the bottom, when we see a non-terminator instruction, we're		// Working from the bottom, when we see a non-terminator instruction, we're
// done.		// done.
if (!isUnpredicatedTerminator(*I))		if (!isUnpredicatedTerminator(*I))
break;		break;

// A terminator that isn't a branch can't easily be handled by this		// A terminator that isn't a branch can't easily be handled by this
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines	unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {		int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");		assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::iterator I = MBB.end();		MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;		unsigned Count = 0;

while (I != MBB.begin()) {		while (I != MBB.begin()) {
--I;		--I;
if (I->isDebugValue())		if (I->isDebugInstr())
continue;		continue;
if (I->getOpcode() != X86::JMP_1 &&		if (I->getOpcode() != X86::JMP_1 &&
X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)		X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
break;		break;
// Remove the branch.		// Remove the branch.
I->eraseFromParent();		I->eraseFromParent();
I = MBB.end();		I = MBB.end();
++Count;		++Count;
▲ Show 20 Lines • Show All 4,596 Lines • ▼ Show 20 Lines	bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
// This function is viable for outlining, so return true.		// This function is viable for outlining, so return true.
return true;		return true;
}		}

X86GenInstrInfo::MachineOutlinerInstrType		X86GenInstrInfo::MachineOutlinerInstrType
X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {		X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
MachineInstr &MI = *MIT;		MachineInstr &MI = *MIT;
// Don't allow debug values to impact outlining type.		// Don't allow debug values to impact outlining type.
if (MI.isDebugValue() \|\| MI.isIndirectDebugValue())		if (MI.isDebugInstr() \|\| MI.isIndirectDebugValue())
return MachineOutlinerInstrType::Invisible;		return MachineOutlinerInstrType::Invisible;

// At this point, KILL instructions don't really tell us much so we can go		// At this point, KILL instructions don't really tell us much so we can go
// ahead and skip over them.		// ahead and skip over them.
if (MI.isKill())		if (MI.isKill())
return MachineOutlinerInstrType::Invisible;		return MachineOutlinerInstrType::Invisible;

// Is this a tail call? If yes, we can outline as a tail call.		// Is this a tail call? If yes, we can outline as a tail call.
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines	for (DenseMap<MachineBasicBlock*, unsigned int>::iterator I = ReturnBBs.begin();

if (Cycles < Threshold) {		if (Cycles < Threshold) {
// BB ends in a return. Skip over any DBG_VALUE instructions		// BB ends in a return. Skip over any DBG_VALUE instructions
// trailing the terminator.		// trailing the terminator.
assert(MBB->size() > 0 &&		assert(MBB->size() > 0 &&
"Basic block should contain at least a RET but is empty");		"Basic block should contain at least a RET but is empty");
MachineBasicBlock::iterator ReturnLoc = --MBB->end();		MachineBasicBlock::iterator ReturnLoc = --MBB->end();

while (ReturnLoc->isDebugValue())		while (ReturnLoc->isDebugInstr())
--ReturnLoc;		--ReturnLoc;
assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() &&		assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() &&
"Basic block does not end with RET");		"Basic block does not end with RET");

addPadding(MBB, ReturnLoc, Threshold - Cycles);		addPadding(MBB, ReturnLoc, Threshold - Cycles);
NumBBsPadded++;		NumBBsPadded++;
MadeChange = true;		MadeChange = true;
}		}
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp

Show First 20 Lines • Show All 421 Lines • ▼ Show 20 Lines	if (CSI.empty())
return true;		return true;

MachineFunction *MF = MBB.getParent();		MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();		const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();		XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);		bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);

DebugLoc DL;		DebugLoc DL;
if (MI != MBB.end() && !MI->isDebugValue())		if (MI != MBB.end() && !MI->isDebugInstr())
DL = MI->getDebugLoc();		DL = MI->getDebugLoc();

for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();		for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
it != CSI.end(); ++it) {		it != CSI.end(); ++it) {
unsigned Reg = it->getReg();		unsigned Reg = it->getReg();
assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&		assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
"LR & FP are always handled in emitPrologue");		"LR & FP are always handled in emitPrologue");

▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,		void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,		MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill,		unsigned SrcReg, bool isKill,
int FrameIndex,		int FrameIndex,
const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const		const TargetRegisterInfo *TRI) const
{		{
DebugLoc DL;		DebugLoc DL;
if (I != MBB.end() && !I->isDebugValue())		if (I != MBB.end() && !I->isDebugInstr())
DL = I->getDebugLoc();		DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();		MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();		const MachineFrameInfo &MFI = MF->getFrameInfo();
MachineMemOperand *MMO = MF->getMachineMemOperand(		MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FrameIndex),		MachinePointerInfo::getFixedStack(*MF, FrameIndex),
MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),		MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
MFI.getObjectAlignment(FrameIndex));		MFI.getObjectAlignment(FrameIndex));
BuildMI(MBB, I, DL, get(XCore::STWFI))		BuildMI(MBB, I, DL, get(XCore::STWFI))
.addReg(SrcReg, getKillRegState(isKill))		.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIndex)		.addFrameIndex(FrameIndex)
.addImm(0)		.addImm(0)
.addMemOperand(MMO);		.addMemOperand(MMO);
}		}

void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,		void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,		MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIndex,		unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const		const TargetRegisterInfo *TRI) const
{		{
DebugLoc DL;		DebugLoc DL;
if (I != MBB.end() && !I->isDebugValue())		if (I != MBB.end() && !I->isDebugInstr())
DL = I->getDebugLoc();		DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();		MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();		const MachineFrameInfo &MFI = MF->getFrameInfo();
MachineMemOperand *MMO = MF->getMachineMemOperand(		MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FrameIndex),		MachinePointerInfo::getFixedStack(*MF, FrameIndex),
MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),		MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
MFI.getObjectAlignment(FrameIndex));		MFI.getObjectAlignment(FrameIndex));
BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)		BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
Show All 26 Lines	static bool isImmMskBitp(unsigned val) {
return (N >= 1 && N <= 8) \|\| N == 16 \|\| N == 24 \|\| N == 32;		return (N >= 1 && N <= 8) \|\| N == 16 \|\| N == 24 \|\| N == 32;
}		}

MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(		MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
MachineBasicBlock &MBB,		MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,		MachineBasicBlock::iterator MI,
unsigned Reg, uint64_t Value) const {		unsigned Reg, uint64_t Value) const {
DebugLoc dl;		DebugLoc dl;
if (MI != MBB.end() && !MI->isDebugValue())		if (MI != MBB.end() && !MI->isDebugInstr())
dl = MI->getDebugLoc();		dl = MI->getDebugLoc();
if (isImmMskBitp(Value)) {		if (isImmMskBitp(Value)) {
int N = Log2_32(Value) + 1;		int N = Log2_32(Value) + 1;
return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)		return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
.addImm(N)		.addImm(N)
.getInstr();		.getInstr();
}		}
if (isImmU16(Value)) {		if (isImmU16(Value)) {
Show All 11 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[DebugInfo] Examine all uses of isDebugValue() for debug instructions.ClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 145850

llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h

llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h

llvm/trunk/include/llvm/CodeGen/SlotIndexes.h

llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp

llvm/trunk/lib/CodeGen/BranchFolding.cpp

llvm/trunk/lib/CodeGen/BreakFalseDeps.cpp

llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp

llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp

llvm/trunk/lib/CodeGen/ExecutionDomainFix.cpp

llvm/trunk/lib/CodeGen/IfConversion.cpp

llvm/trunk/lib/CodeGen/InlineSpiller.cpp

llvm/trunk/lib/CodeGen/LiveIntervals.cpp

llvm/trunk/lib/CodeGen/LiveRangeShrink.cpp

llvm/trunk/lib/CodeGen/LiveVariables.cpp

llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp

llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp

llvm/trunk/lib/CodeGen/MachineCSE.cpp

llvm/trunk/lib/CodeGen/MachineInstr.cpp

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

llvm/trunk/lib/CodeGen/MachineSink.cpp

llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

llvm/trunk/lib/CodeGen/PHIElimination.cpp

llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp

llvm/trunk/lib/CodeGen/ReachingDefAnalysis.cpp

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

llvm/trunk/lib/CodeGen/RegisterPressure.cpp

llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

llvm/trunk/lib/CodeGen/SlotIndexes.cpp

llvm/trunk/lib/CodeGen/SplitKit.cpp

llvm/trunk/lib/CodeGen/StackColoring.cpp

llvm/trunk/lib/CodeGen/StackSlotColoring.cpp

llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp

llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp

llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp

llvm/trunk/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp

llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp

llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp

llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp

llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp

llvm/trunk/lib/Target/Hexagon/BitTracker.cpp

llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp

llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp

llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp

llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp

llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp

llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp

llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

[DebugInfo] Examine all uses of isDebugValue() for debug instructions.
ClosedPublic