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Differential D44830

Introduce codegen for the Signal Processing Engine
ClosedPublic

Authored by jhibbits on Mar 23 2018, 7:27 AM.

Details

Reviewers
nemanjai
hfinkel
joerg
Commits
rGd52990c71b6f: Introduce codegen for the Signal Processing Engine
rL337347: Introduce codegen for the Signal Processing Engine
Summary

The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,
e500v2, and several e200 cores. This adds support targeting the e500v2,
as this is more common than the e500v1, and is in SoCs still on the
market.

This patch is very intrusive because the SPE is binary incompatible with
the traditional FPU. After discussing with others, the cleanest
solution was to make both SPE and FPU features on top of a base PowerPC
subset, so all FPU instructions are now wrapped with HasFPU predicates.

Supported by this are:

  • Code generation following the SPE ABI at the LLVM IR level (calling

conventions)

  • Single- and Double-precision math at the level supported by the APU.

Still to do:

  • Vector operations
  • SPE intrinsics

Diff Detail

Event Timeline

jhibbits created this revision.Mar 23 2018, 7:27 AM
Herald added a subscriber: kbarton. · View Herald TranscriptMar 23 2018, 7:27 AM
nemanjai added a comment.Apr 9 2018, 2:51 PM

This is much easier to follow now that it is much smaller. Thank you for breaking it apart.

Also, can you please add test cases for the invalid combinations of target features (both implicit and explicit)?
Things like -mcpu=pwr8 -mattr=+spe, etc.

lib/Target/PowerPC/PPCAsmPrinter.cpp
513

I think it would be appropriate to do this check only in debug builds, so I'd wrap this into
#ifndef NDEBUG.

518

s/reg/Reg

520

Don't you have to check for classes like VSSRCRegClass, VSFRCRegClass, etc. I imagine VSX scalar instructions can't exist with SPE ones either, right? Can SPE even coexist with Altivec/VSX vectors?

lib/Target/PowerPC/PPCCallingConv.td
214–218

Line too long.

287

I would probably use "common" instead of "base" (and perhaps CSR_SVR432_COMM), but I don't feel all that strong about it.

lib/Target/PowerPC/PPCFastISel.cpp
1999–2005

Can you please use the same variable name to be consistent? You have uses of UseSPE as well as HasSPE in this code. The latter seems to be more in-line with similar predicates.

lib/Target/PowerPC/PPCFrameLowering.cpp
1908

This entire block is common with the one directly above it. Can you combine them and just use HasSPESaveArea in a conditional operator on the only line that is different? If you do that, please update the comment to specify that the two save areas have the same alignment requirements.

lib/Target/PowerPC/PPCInstrInfo.cpp
301–302

We've recently completely changed the handling for these functions for spills and restores, so this part will need to be reworked to merge with ToT.

lib/Target/PowerPC/PPCRegisterInfo.cpp
156

There is a note below describing the alternate allocation order of SPE registers for PPC64 SVR4 ABI. This somewhat implies that if R2 is allocatable (i.e. no TOC uses), that it needs to be saved/restored. Do we not want to make R2 a callee-saved register if it is allocatable?

lib/Target/PowerPC/PPCRegisterInfo.td
306

I may have mixed things up here, but for some reason I was under the impression that SPE isn't available on 64-bit PPC targets.

nemanjai requested changes to this revision.Apr 9 2018, 2:55 PM

This will certainly need another cycle to at least account for the recent changes in PPCInstrInfo.cpp.

This revision now requires changes to proceed.Apr 9 2018, 2:55 PM
jhibbits marked 8 inline comments as done.Apr 10 2018, 2:54 PM
jhibbits added inline comments.
lib/Target/PowerPC/PPCInstrInfo.cpp
301–302

I've recently rebased and reconciled. I'll update the review shortly.

lib/Target/PowerPC/PPCRegisterInfo.td
306

Yeah, this was a copy&paste. Doesn't make sense to have the body.

jhibbits updated this revision to Diff 143499.Apr 22 2018, 8:06 PM
jhibbits marked an inline comment as done.

Rebase against newer head. Address several comments.

Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 22 2018, 8:06 PM
Harbormaster completed remote builds in B17317: Diff 143499.Apr 22 2018, 8:08 PM
nemanjai accepted this revision.May 1 2018, 3:32 PM

Thank you so much for your patience with this long review cycle. Aside from a few minor nits, LGTM.
I also imagine you'll need something for the P9 scheduler since we've now marked the model as complete. Probably something along the lines of:

Index: lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- lib/Target/PowerPC/PPCScheduleP9.td (revision 331260)
+++ lib/Target/PowerPC/PPCScheduleP9.td (working copy)
@@ -35,8 +35,9 @@
 
   let CompleteModel = 1;
 
-  // Do not support QPX (Quad Processing eXtension) on Power 9.
-  let UnsupportedFeatures = [HasQPX];
+  // Do not support QPX (Quad Processing eXtension) or SPE (Signal Processing
+  // Engine) on Power 9.
+  let UnsupportedFeatures = [HasQPX, HasSPE];
 
 }
lib/Target/PowerPC/PPCAsmPrinter.cpp
516

I think this can be a range-based for loop over MI->operands().

lib/Target/PowerPC/PPCCallingConv.td
286–291

Nit: full sentence comments with a period.

This revision is now accepted and ready to land.May 1 2018, 3:32 PM
jhibbits updated this revision to Diff 155610.Jul 15 2018, 8:02 PM

Update diff to fix a test with the new register order.

jhibbits mentioned this in D44829: Complete the SPE instruction set patterns.Jul 15 2018, 8:14 PM
nemanjai added a comment.Jul 17 2018, 4:50 AM

I don't see anything in the update that would cause me to reverse the approval, so I'd say this is still fine.

Closed by commit rL337347: Introduce codegen for the Signal Processing Engine (authored by jhibbits). · Explain WhyJul 17 2018, 9:30 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
PowerPC/
AsmParser/
20 lines
Disassembler/
23 lines
MCTargetDesc/
3 lines
31 lines
26 lines
42 lines
148 lines
34 lines
78 lines
9 lines
117 lines
27 lines
112 lines
1218 lines
11 lines
25 lines
2 lines
11 lines
test/
CodeGen/
PowerPC/
20 lines
9 lines
25 lines
13 lines
542 lines

Diff 155610

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Linesstatic const MCPhysReg FRegs[32] = {
PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F8, PPC::F9, PPC::F10, PPC::F11,
PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F12, PPC::F13, PPC::F14, PPC::F15,
PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F16, PPC::F17, PPC::F18, PPC::F19,
PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F20, PPC::F21, PPC::F22, PPC::F23,
PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F24, PPC::F25, PPC::F26, PPC::F27,
PPC::F28, PPC::F29, PPC::F30, PPC::F31 PPC::F28, PPC::F29, PPC::F30, PPC::F31
}; };
static const MCPhysReg SPERegs[32] = {
PPC::S0, PPC::S1, PPC::S2, PPC::S3,
PPC::S4, PPC::S5, PPC::S6, PPC::S7,
PPC::S8, PPC::S9, PPC::S10, PPC::S11,
PPC::S12, PPC::S13, PPC::S14, PPC::S15,
PPC::S16, PPC::S17, PPC::S18, PPC::S19,
PPC::S20, PPC::S21, PPC::S22, PPC::S23,
PPC::S24, PPC::S25, PPC::S26, PPC::S27,
PPC::S28, PPC::S29, PPC::S30, PPC::S31
};
static const MCPhysReg VFRegs[32] = { static const MCPhysReg VFRegs[32] = {
PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
▲ Show 20 Lines • Show All 549 Lines • ▼ Show 20 Lines void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
} }
void addRegQBRCOperands(MCInst &Inst, unsigned N) const { void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
} }
void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
}
void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
}
void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
} }
void addRegCRRCOperands(MCInst &Inst, unsigned N) const { void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
▲ Show 20 Lines • Show All 1,339 Lines • Show Last 20 Lines

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Linesstatic const unsigned QFRegs[] = {
PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15, PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19, PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23, PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27, PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
}; };
static const unsigned SPERegs[] = {
PPC::S0, PPC::S1, PPC::S2, PPC::S3,
PPC::S4, PPC::S5, PPC::S6, PPC::S7,
PPC::S8, PPC::S9, PPC::S10, PPC::S11,
PPC::S12, PPC::S13, PPC::S14, PPC::S15,
PPC::S16, PPC::S17, PPC::S18, PPC::S19,
PPC::S20, PPC::S21, PPC::S22, PPC::S23,
PPC::S24, PPC::S25, PPC::S26, PPC::S27,
PPC::S28, PPC::S29, PPC::S30, PPC::S31
};
template <std::size_t N> template <std::size_t N>
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
const unsigned (&Regs)[N]) { const unsigned (&Regs)[N]) {
assert(RegNo < N && "Invalid register number"); assert(RegNo < N && "Invalid register number");
Inst.addOperand(MCOperand::createReg(Regs[RegNo])); Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, QFRegs); return decodeRegisterClass(Inst, RegNo, QFRegs);
} }
static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, GPRegs);
}
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SPERegs);
}
#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
template<unsigned N> template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) { int64_t Address, const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate"); assert(isUInt<N>(Imm) && "Invalid immediate");
Inst.addOperand(MCOperand::createImm(Imm)); Inst.addOperand(MCOperand::createImm(Imm));
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines enum Predicate {
PRED_LE_PLUS = (1 << 5) | 7, PRED_LE_PLUS = (1 << 5) | 7,
PRED_EQ_PLUS = (2 << 5) | 15, PRED_EQ_PLUS = (2 << 5) | 15,
PRED_GE_PLUS = (0 << 5) | 7, PRED_GE_PLUS = (0 << 5) | 7,
PRED_GT_PLUS = (1 << 5) | 15, PRED_GT_PLUS = (1 << 5) | 15,
PRED_NE_PLUS = (2 << 5) | 7, PRED_NE_PLUS = (2 << 5) | 7,
PRED_UN_PLUS = (3 << 5) | 15, PRED_UN_PLUS = (3 << 5) | 15,
PRED_NU_PLUS = (3 << 5) | 7, PRED_NU_PLUS = (3 << 5) | 7,
// SPE scalar compare instructions always set the GT bit.
PRED_SPE = PRED_GT,
// When dealing with individual condition-register bits, we have simple set // When dealing with individual condition-register bits, we have simple set
// and unset predicates. // and unset predicates.
PRED_BIT_SET = 1024, PRED_BIT_SET = 1024,
PRED_BIT_UNSET = 1025 PRED_BIT_UNSET = 1025
}; };
// Bit for branch taken (plus) or not-taken (minus) hint // Bit for branch taken (plus) or not-taken (minus) hint
enum BranchHintBit { enum BranchHintBit {
Show All 32 Lines

lib/Target/PowerPC/PPC.td

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">; "Enable 64-bit instructions">;
def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
"Enable floating-point instructions">; "Enable floating-point instructions">;
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">; "Enable 64-bit registers usage for ppc32 [beta]">;
def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
"Use condition-register bits individually">; "Use condition-register bits individually">;
def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
"Enable classic FPU instructions",
[FeatureHardFloat]>;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions", "Enable Altivec instructions",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
"Enable SPE instructions", "Enable SPE instructions",
[FeatureHardFloat]>; [FeatureHardFloat]>;
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
"Enable the MFOCRF instruction">; "Enable the MFOCRF instruction">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction", "Enable the fsqrt instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
"Enable the fcpsgn instruction", "Enable the fcpsgn instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
"Enable the fre instruction", "Enable the fre instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
"Enable the fres instruction", "Enable the fres instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
"Enable the frsqrte instruction", "Enable the frsqrte instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
"Enable the frsqrtes instruction", "Enable the frsqrtes instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
"Assume higher precision reciprocal estimates">; "Assume higher precision reciprocal estimates">;
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
"Enable the stfiwx instruction", "Enable the stfiwx instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
"Enable the lfiwax instruction", "Enable the lfiwax instruction",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
"Enable the fri[mnpz] instructions", "Enable the fri[mnpz] instructions",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
"Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">; "Enable the isel instruction">;
def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
"Enable the bpermd instruction">; "Enable the bpermd instruction">;
def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
"Enable extended divide instructions">; "Enable extended divide instructions">;
def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
"Enable the ldbrx instruction">; "Enable the ldbrx instruction">;
Show All 12 Lines
def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
"Enable secure plt mode">; "Enable secure plt mode">;
def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
"Enable PPC 4xx instructions">; "Enable PPC 4xx instructions">;
def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
"Enable PPC 6xx instructions">; "Enable PPC 6xx instructions">;
def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
"Enable QPX instructions", "Enable QPX instructions",
[FeatureHardFloat]>; [FeatureFPU]>;
def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
"Enable VSX instructions", "Enable VSX instructions",
[FeatureAltivec]>; [FeatureAltivec]>;
def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
"Enable POWER8 Altivec instructions", "Enable POWER8 Altivec instructions",
[FeatureAltivec]>; [FeatureAltivec]>;
def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
"Enable POWER8 Crypto instructions", "Enable POWER8 Crypto instructions",
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE, FeatureFRES, FeatureFRSQRTE,
FeatureICBT, FeatureBookE, FeatureICBT, FeatureBookE,
FeatureMSYNC, FeatureMFTB]>; FeatureMSYNC, FeatureMFTB]>;
def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE, FeatureFRES, FeatureFRSQRTE,
FeatureICBT, FeatureBookE, FeatureICBT, FeatureBookE,
FeatureMSYNC, FeatureMFTB]>; FeatureMSYNC, FeatureMFTB]>;
def : Processor<"601", G3Itineraries, [Directive601, FeatureHardFloat]>; def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
def : Processor<"602", G3Itineraries, [Directive602, FeatureHardFloat, def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
FeatureMFTB]>; FeatureMFTB]>;
def : Processor<"603", G3Itineraries, [Directive603, def : Processor<"603", G3Itineraries, [Directive603,
FeatureFRES, FeatureFRSQRTE, FeatureFRES, FeatureFRSQRTE,
FeatureMFTB]>; FeatureMFTB]>;
def : Processor<"603e", G3Itineraries, [Directive603, def : Processor<"603e", G3Itineraries, [Directive603,
FeatureFRES, FeatureFRSQRTE, FeatureFRES, FeatureFRSQRTE,
FeatureMFTB]>; FeatureMFTB]>;
def : Processor<"603ev", G3Itineraries, [Directive603, def : Processor<"603ev", G3Itineraries, [Directive603,
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCAsmPrinter.cpp

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Lines
/// ///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst; MCInst TmpInst;
bool isPPC64 = Subtarget->isPPC64(); bool isPPC64 = Subtarget->isPPC64();
bool isDarwin = TM.getTargetTriple().isOSDarwin(); bool isDarwin = TM.getTargetTriple().isOSDarwin();
const Module *M = MF->getFunction().getParent(); const Module *M = MF->getFunction().getParent();
PICLevel::Level PL = M->getPICLevel(); PICLevel::Level PL = M->getPICLevel();
#ifndef NDEBUG
nemanjaiUnsubmitted
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I think it would be appropriate to do this check only in debug builds, so I'd wrap this into
#ifndef NDEBUG.

nemanjai: I think it would be appropriate to do this check only in debug builds, so I'd wrap this into…
// Validate that SPE and FPU are mutually exclusive in codegen
if (!MI->isInlineAsm()) {
for (const MachineOperand &MO: MI->operands()) {
nemanjaiUnsubmitted
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I think this can be a range-based for loop over MI->operands().

nemanjai: I think this can be a range-based for loop over `MI->operands()`.
if (MO.isReg()) {
unsigned Reg = MO.getReg();
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s/reg/Reg

nemanjai: s/reg/Reg
if (Subtarget->hasSPE()) {
if (PPC::F4RCRegClass.contains(Reg) ||
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Don't you have to check for classes like VSSRCRegClass, VSFRCRegClass, etc. I imagine VSX scalar instructions can't exist with SPE ones either, right? Can SPE even coexist with Altivec/VSX vectors?

nemanjai: Don't you have to check for classes like `VSSRCRegClass`, `VSFRCRegClass`, etc. I imagine VSX…
PPC::F8RCRegClass.contains(Reg) ||
PPC::QBRCRegClass.contains(Reg) ||
PPC::QFRCRegClass.contains(Reg) ||
PPC::QSRCRegClass.contains(Reg) ||
PPC::VFRCRegClass.contains(Reg) ||
PPC::VRRCRegClass.contains(Reg) ||
PPC::VSFRCRegClass.contains(Reg) ||
PPC::VSSRCRegClass.contains(Reg)
)
llvm_unreachable("SPE targets cannot have FPRegs!");
} else {
if (PPC::SPERCRegClass.contains(Reg))
llvm_unreachable("SPE register found in FPU-targeted code!");
}
}
}
}
#endif
// Lower multi-instruction pseudo operations. // Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: break; default: break;
case TargetOpcode::DBG_VALUE: case TargetOpcode::DBG_VALUE:
llvm_unreachable("Should be handled target independently"); llvm_unreachable("Should be handled target independently");
case TargetOpcode::STACKMAP: case TargetOpcode::STACKMAP:
return LowerSTACKMAP(SM, *MI); return LowerSTACKMAP(SM, *MI);
case TargetOpcode::PATCHPOINT: case TargetOpcode::PATCHPOINT:
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lib/Target/PowerPC/PPCCallingConv.td

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Linesdef RetCC_PPC : CallingConv<[
CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
// Floating point types returned as "direct" go into F1 .. F8; note that // Floating point types returned as "direct" go into F1 .. F8; note that
// only the ELFv2 ABI fully utilizes all these registers. // only the ELFv2 ABI fully utilizes all these registers.
CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, CCIfNotSubtarget<"hasSPE()",
CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
CCIfNotSubtarget<"hasSPE()",
CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
CCIfSubtarget<"hasSPE()",
CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
CCIfSubtarget<"hasSPE()",
CCIfType<[f64], CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
// For P9, f128 are passed in vector registers. // For P9, f128 are passed in vector registers.
CCIfType<[f128], CCIfType<[f128],
CCIfSubtarget<"hasP9Vector()", CCIfSubtarget<"hasP9Vector()",
CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
// QPX vectors are returned in QF1 and QF2. // QPX vectors are returned in QF1 and QF2.
CCIfType<[v4f64, v4f32, v4i1], CCIfType<[v4f64, v4f32, v4i1],
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesdef CC_PPC32_SVR4_Common : CallingConv<[
// The first 8 integer arguments are passed in integer registers. // The first 8 integer arguments are passed in integer registers.
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
// Make sure the i64 words from a long double are either both passed in // Make sure the i64 words from a long double are either both passed in
// registers or both passed on the stack. // registers or both passed on the stack.
CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
// FP values are passed in F1 - F8. // FP values are passed in F1 - F8.
CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, CCIfType<[f32, f64],
CCIfNotSubtarget<"hasSPE()",
CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
CCIfType<[f64],
CCIfSubtarget<"hasSPE()",
CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
CCIfType<[f32],
CCIfSubtarget<"hasSPE()",
CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
// Split arguments have an alignment of 8 bytes on the stack. // Split arguments have an alignment of 8 bytes on the stack.
CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
CCIfType<[i32], CCAssignToStack<4, 4>>, CCIfType<[i32], CCAssignToStack<4, 4>>,
// Floats are stored in double precision format, thus they have the same // Floats are stored in double precision format, thus they have the same
// alignment and size as doubles. // alignment and size as doubles.
CCIfType<[f32,f64], CCAssignToStack<8, 8>>, // With SPE floats are stored as single precision, so have alignment and
// size of int.
CCIfType<[f32,f64], CCIfNotSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToStack<4, 4>>>,
CCIfType<[f64], CCIfSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
nemanjaiUnsubmitted
Done
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Line too long.

nemanjai: Line too long.
// QPX vectors that are stored in double precision need 32-byte alignment. // QPX vectors that are stored in double precision need 32-byte alignment.
CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>, CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
// Vectors and float128 get 16-byte stack slots that are 16-byte aligned. // Vectors and float128 get 16-byte stack slots that are 16-byte aligned.
CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>, CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>> CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>>
]>; ]>;
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesdef CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
R21, R22, R23, R24, R25, R26, R27, R28, R21, R22, R23, R24, R25, R26, R27, R28,
R29, R30, R31, F14, F15, F16, F17, F18, R29, R30, R31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26, F19, F20, F21, F22, F23, F24, F25, F26,
F27, F28, F29, F30, F31, CR2, CR3, CR4 F27, F28, F29, F30, F31, CR2, CR3, CR4
)>; )>;
def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, // SPE does not use FPRs, so break out the common register set as base.
R21, R22, R23, R24, R25, R26, R27, R28, def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
nemanjaiUnsubmitted
Done
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I would probably use "common" instead of "base" (and perhaps CSR_SVR432_COMM), but I don't feel all that strong about it.

nemanjai: I would probably use "common" instead of "base" (and perhaps `CSR_SVR432_COMM`), but I don't…
R29, R30, R31, F14, F15, F16, F17, F18, R21, R22, R23, R24, R25, R26, R27,
R28, R29, R30, R31, CR2, CR3, CR4
)>;
def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
nemanjaiUnsubmitted
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Nit: full sentence comments with a period.

nemanjai: Nit: full sentence comments with a period.
F19, F20, F21, F22, F23, F24, F25, F26, F19, F20, F21, F22, F23, F24, F25, F26,
F27, F28, F29, F30, F31, CR2, CR3, CR4 F27, F28, F29, F30, F31
)>;
def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
S23, S24, S25, S26, S27, S28, S29, S30, S31
)>; )>;
def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
X21, X22, X23, X24, X25, X26, X27, X28, X21, X22, X23, X24, X25, X26, X27, X28,
X29, X30, X31, F14, F15, F16, F17, F18, X29, X30, X31, F14, F15, F16, F17, F18,
F19, F20, F21, F22, F23, F24, F25, F26, F19, F20, F21, F22, F23, F24, F25, F26,
F27, F28, F29, F30, F31, CR2, CR3, CR4 F27, F28, F29, F30, F31, CR2, CR3, CR4
)>; )>;
def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
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lib/Target/PowerPC/PPCFastISel.cpp

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines private:
bool isValueAvailable(const Value *V) const; bool isValueAvailable(const Value *V) const;
bool isVSFRCRegClass(const TargetRegisterClass *RC) const { bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
return RC->getID() == PPC::VSFRCRegClassID; return RC->getID() == PPC::VSFRCRegClassID;
} }
bool isVSSRCRegClass(const TargetRegisterClass *RC) const { bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
return RC->getID() == PPC::VSSRCRegClassID; return RC->getID() == PPC::VSSRCRegClassID;
} }
bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt, unsigned DestReg); bool isZExt, unsigned DestReg,
const PPC::Predicate Pred);
bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
const TargetRegisterClass *RC, bool IsZExt = true, const TargetRegisterClass *RC, bool IsZExt = true,
unsigned FP64LoadOpc = PPC::LFD); unsigned FP64LoadOpc = PPC::LFD);
bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr); bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
bool PPCComputeAddress(const Value *Obj, Address &Addr); bool PPCComputeAddress(const Value *Obj, Address &Addr);
void PPCSimplifyAddress(Address &Addr, bool &UseOffset, void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
unsigned &IndexReg); unsigned &IndexReg);
bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
▲ Show 20 Lines • Show All 296 Lines • ▼ Show 20 Lines
// Emit a load instruction if possible, returning true if we succeeded, // Emit a load instruction if possible, returning true if we succeeded,
// otherwise false. See commentary below for how the register class of // otherwise false. See commentary below for how the register class of
// the load is determined. // the load is determined.
bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
bool IsZExt, unsigned FP64LoadOpc) { bool IsZExt, unsigned FP64LoadOpc) {
unsigned Opc; unsigned Opc;
bool UseOffset = true; bool UseOffset = true;
bool HasSPE = PPCSubTarget->hasSPE();
// If ResultReg is given, it determines the register class of the load. // If ResultReg is given, it determines the register class of the load.
// Otherwise, RC is the register class to use. If the result of the // Otherwise, RC is the register class to use. If the result of the
// load isn't anticipated in this block, both may be zero, in which // load isn't anticipated in this block, both may be zero, in which
// case we must make a conservative guess. In particular, don't assign // case we must make a conservative guess. In particular, don't assign
// R0 or X0 to the result register, as the result may be used in a load, // R0 or X0 to the result register, as the result may be used in a load,
// store, add-immediate, or isel that won't permit this. (Though // store, add-immediate, or isel that won't permit this. (Though
// perhaps the spill and reload of live-exit values would handle this?) // perhaps the spill and reload of live-exit values would handle this?)
const TargetRegisterClass *UseRC = const TargetRegisterClass *UseRC =
(ResultReg ? MRI.getRegClass(ResultReg) : (ResultReg ? MRI.getRegClass(ResultReg) :
(RC ? RC : (RC ? RC :
(VT == MVT::f64 ? &PPC::F8RCRegClass : (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
(VT == MVT::f32 ? &PPC::F4RCRegClass : (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
(VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
&PPC::GPRC_and_GPRC_NOR0RegClass))))); &PPC::GPRC_and_GPRC_NOR0RegClass)))));
bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
switch (VT.SimpleTy) { switch (VT.SimpleTy) {
default: // e.g., vector types not handled default: // e.g., vector types not handled
return false; return false;
Show All 12 Lines case MVT::i32:
break; break;
case MVT::i64: case MVT::i64:
Opc = PPC::LD; Opc = PPC::LD;
assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
"64-bit load with 32-bit target??"); "64-bit load with 32-bit target??");
UseOffset = ((Addr.Offset & 3) == 0); UseOffset = ((Addr.Offset & 3) == 0);
break; break;
case MVT::f32: case MVT::f32:
Opc = PPC::LFS; Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
break; break;
case MVT::f64: case MVT::f64:
Opc = FP64LoadOpc; Opc = FP64LoadOpc;
break; break;
} }
// If necessary, materialize the offset into a register and use // If necessary, materialize the offset into a register and use
// the indexed form. Also handle stack pointers with special needs. // the indexed form. Also handle stack pointers with special needs.
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines switch (Opc) {
case PPC::LHA8: Opc = PPC::LHAX8; break; case PPC::LHA8: Opc = PPC::LHAX8; break;
case PPC::LWZ: Opc = PPC::LWZX; break; case PPC::LWZ: Opc = PPC::LWZX; break;
case PPC::LWZ8: Opc = PPC::LWZX8; break; case PPC::LWZ8: Opc = PPC::LWZX8; break;
case PPC::LWA: Opc = PPC::LWAX; break; case PPC::LWA: Opc = PPC::LWAX; break;
case PPC::LWA_32: Opc = PPC::LWAX_32; break; case PPC::LWA_32: Opc = PPC::LWAX_32; break;
case PPC::LD: Opc = PPC::LDX; break; case PPC::LD: Opc = PPC::LDX; break;
case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break; case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break; case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
case PPC::EVLDD: Opc = PPC::EVLDDX; break;
case PPC::SPELWZ: Opc = PPC::SPELWZX; break;
} }
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
ResultReg); ResultReg);
// If we have an index register defined we use it in the store inst, // If we have an index register defined we use it in the store inst,
// otherwise we use X0 as base as it makes the vector instructions to // otherwise we use X0 as base as it makes the vector instructions to
// use zero in the computation of the effective address regardless the // use zero in the computation of the effective address regardless the
Show All 26 Linesbool PPCFastISel::SelectLoad(const Instruction *I) {
// Look at the currently assigned register for this instruction // Look at the currently assigned register for this instruction
// to determine the required register class. This is necessary // to determine the required register class. This is necessary
// to constrain RA from using R0/X0 when this is not legal. // to constrain RA from using R0/X0 when this is not legal.
unsigned AssignedReg = FuncInfo.ValueMap[I]; unsigned AssignedReg = FuncInfo.ValueMap[I];
const TargetRegisterClass *RC = const TargetRegisterClass *RC =
AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
unsigned ResultReg = 0; unsigned ResultReg = 0;
if (!PPCEmitLoad(VT, ResultReg, Addr, RC)) if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
return false; return false;
updateValueMap(I, ResultReg); updateValueMap(I, ResultReg);
return true; return true;
} }
// Emit a store instruction to store SrcReg at Addr. // Emit a store instruction to store SrcReg at Addr.
bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
assert(SrcReg && "Nothing to store!"); assert(SrcReg && "Nothing to store!");
Show All 16 Lines case MVT::i32:
assert(Is32BitInt && "Not GPRC for i32??"); assert(Is32BitInt && "Not GPRC for i32??");
Opc = PPC::STW; Opc = PPC::STW;
break; break;
case MVT::i64: case MVT::i64:
Opc = PPC::STD; Opc = PPC::STD;
UseOffset = ((Addr.Offset & 3) == 0); UseOffset = ((Addr.Offset & 3) == 0);
break; break;
case MVT::f32: case MVT::f32:
Opc = PPC::STFS; Opc = PPCSubTarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
break; break;
case MVT::f64: case MVT::f64:
Opc = PPC::STFD; Opc = PPCSubTarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
break; break;
} }
// If necessary, materialize the offset into a register and use // If necessary, materialize the offset into a register and use
// the indexed form. Also handle stack pointers with special needs. // the indexed form. Also handle stack pointers with special needs.
unsigned IndexReg = 0; unsigned IndexReg = 0;
PPCSimplifyAddress(Addr, UseOffset, IndexReg); PPCSimplifyAddress(Addr, UseOffset, IndexReg);
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines switch (Opc) {
case PPC::STH : Opc = PPC::STHX; break; case PPC::STH : Opc = PPC::STHX; break;
case PPC::STW : Opc = PPC::STWX; break; case PPC::STW : Opc = PPC::STWX; break;
case PPC::STB8: Opc = PPC::STBX8; break; case PPC::STB8: Opc = PPC::STBX8; break;
case PPC::STH8: Opc = PPC::STHX8; break; case PPC::STH8: Opc = PPC::STHX8; break;
case PPC::STW8: Opc = PPC::STWX8; break; case PPC::STW8: Opc = PPC::STWX8; break;
case PPC::STD: Opc = PPC::STDX; break; case PPC::STD: Opc = PPC::STDX; break;
case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break; case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break; case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
case PPC::SPESTW: Opc = PPC::SPESTWX; break;
} }
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
.addReg(SrcReg); .addReg(SrcReg);
// If we have an index register defined we use it in the store inst, // If we have an index register defined we use it in the store inst,
// otherwise we use X0 as base as it makes the vector instructions to // otherwise we use X0 as base as it makes the vector instructions to
// use zero in the computation of the effective address regardless the // use zero in the computation of the effective address regardless the
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines if (isValueAvailable(CI)) {
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
std::swap(TBB, FBB); std::swap(TBB, FBB);
PPCPred = PPC::InvertPredicate(PPCPred); PPCPred = PPC::InvertPredicate(PPCPred);
} }
unsigned CondReg = createResultReg(&PPC::CRRCRegClass); unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
CondReg)) CondReg, PPCPred))
return false; return false;
BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC)) BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
.addImm(PPCPred).addReg(CondReg).addMBB(TBB); .addImm(PPCSubTarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
.addReg(CondReg).addMBB(TBB);
finishCondBranch(BI->getParent(), TBB, FBB); finishCondBranch(BI->getParent(), TBB, FBB);
return true; return true;
} }
} else if (const ConstantInt *CI = } else if (const ConstantInt *CI =
dyn_cast<ConstantInt>(BI->getCondition())) { dyn_cast<ConstantInt>(BI->getCondition())) {
uint64_t Imm = CI->getZExtValue(); uint64_t Imm = CI->getZExtValue();
MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
fastEmitBranch(Target, DbgLoc); fastEmitBranch(Target, DbgLoc);
return true; return true;
} }
// FIXME: ARM looks for a case where the block containing the compare // FIXME: ARM looks for a case where the block containing the compare
// has been split from the block containing the branch. If this happens, // has been split from the block containing the branch. If this happens,
// there is a vreg available containing the result of the compare. I'm // there is a vreg available containing the result of the compare. I'm
// not sure we can do much, as we've lost the predicate information with // not sure we can do much, as we've lost the predicate information with
// the compare instruction -- we have a 4-bit CR but don't know which bit // the compare instruction -- we have a 4-bit CR but don't know which bit
// to test here. // to test here.
return false; return false;
} }
// Attempt to emit a compare of the two source values. Signed and unsigned // Attempt to emit a compare of the two source values. Signed and unsigned
// comparisons are supported. Return false if we can't handle it. // comparisons are supported. Return false if we can't handle it.
bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2, bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
bool IsZExt, unsigned DestReg) { bool IsZExt, unsigned DestReg,
const PPC::Predicate Pred) {
Type *Ty = SrcValue1->getType(); Type *Ty = SrcValue1->getType();
EVT SrcEVT = TLI.getValueType(DL, Ty, true); EVT SrcEVT = TLI.getValueType(DL, Ty, true);
if (!SrcEVT.isSimple()) if (!SrcEVT.isSimple())
return false; return false;
MVT SrcVT = SrcEVT.getSimpleVT(); MVT SrcVT = SrcEVT.getSimpleVT();
if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
return false; return false;
// See if operand 2 is an immediate encodeable in the compare. // See if operand 2 is an immediate encodeable in the compare.
// FIXME: Operands are not in canonical order at -O0, so an immediate // FIXME: Operands are not in canonical order at -O0, so an immediate
// operand in position 1 is a lost opportunity for now. We are // operand in position 1 is a lost opportunity for now. We are
// similar to ARM in this regard. // similar to ARM in this regard.
long Imm = 0; long Imm = 0;
bool UseImm = false; bool UseImm = false;
const bool HasSPE = PPCSubTarget->hasSPE();
// Only 16-bit integer constants can be represented in compares for // Only 16-bit integer constants can be represented in compares for
// PowerPC. Others will be materialized into a register. // PowerPC. Others will be materialized into a register.
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) { if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
SrcVT == MVT::i8 || SrcVT == MVT::i1) { SrcVT == MVT::i8 || SrcVT == MVT::i1) {
const APInt &CIVal = ConstInt->getValue(); const APInt &CIVal = ConstInt->getValue();
Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
UseImm = true; UseImm = true;
} }
} }
unsigned CmpOpc; unsigned CmpOpc;
bool NeedsExt = false; bool NeedsExt = false;
switch (SrcVT.SimpleTy) { switch (SrcVT.SimpleTy) {
default: return false; default: return false;
case MVT::f32: case MVT::f32:
if (HasSPE) {
switch (Pred) {
default: return false;
case PPC::PRED_EQ:
CmpOpc = PPC::EFSCMPEQ;
break;
case PPC::PRED_LT:
CmpOpc = PPC::EFSCMPLT;
break;
case PPC::PRED_GT:
CmpOpc = PPC::EFSCMPGT;
break;
}
} else
CmpOpc = PPC::FCMPUS; CmpOpc = PPC::FCMPUS;
break; break;
case MVT::f64: case MVT::f64:
if (HasSPE) {
switch (Pred) {
default: return false;
case PPC::PRED_EQ:
CmpOpc = PPC::EFDCMPEQ;
break;
case PPC::PRED_LT:
CmpOpc = PPC::EFDCMPLT;
break;
case PPC::PRED_GT:
CmpOpc = PPC::EFDCMPGT;
break;
}
} else
CmpOpc = PPC::FCMPUD; CmpOpc = PPC::FCMPUD;
break; break;
case MVT::i1: case MVT::i1:
case MVT::i8: case MVT::i8:
case MVT::i16: case MVT::i16:
NeedsExt = true; NeedsExt = true;
// Intentional fall-through. // Intentional fall-through.
case MVT::i32: case MVT::i32:
if (!UseImm) if (!UseImm)
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesbool PPCFastISel::SelectFPTrunc(const Instruction *I) {
if (SrcVT != MVT::f64 || DestVT != MVT::f32) if (SrcVT != MVT::f64 || DestVT != MVT::f32)
return false; return false;
unsigned SrcReg = getRegForValue(Src); unsigned SrcReg = getRegForValue(Src);
if (!SrcReg) if (!SrcReg)
return false; return false;
// Round the result to single precision. // Round the result to single precision.
unsigned DestReg = createResultReg(&PPC::F4RCRegClass); unsigned DestReg;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
if (PPCSubTarget->hasSPE()) {
DestReg = createResultReg(&PPC::SPE4RCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::EFSCFD), DestReg)
.addReg(SrcReg); .addReg(SrcReg);
} else {
DestReg = createResultReg(&PPC::F4RCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP), DestReg)
.addReg(SrcReg);
}
updateValueMap(I, DestReg); updateValueMap(I, DestReg);
return true; return true;
} }
// Move an i32 or i64 value in a GPR to an f64 value in an FPR. // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
// FIXME: When direct register moves are implemented (see PowerISA 2.07), // FIXME: When direct register moves are implemented (see PowerISA 2.07),
// those should be used instead of moving via a stack slot when the // those should be used instead of moving via a stack slot when the
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesbool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
SrcVT != MVT::i32 && SrcVT != MVT::i64) SrcVT != MVT::i32 && SrcVT != MVT::i64)
return false; return false;
unsigned SrcReg = getRegForValue(Src); unsigned SrcReg = getRegForValue(Src);
if (SrcReg == 0) if (SrcReg == 0)
return false; return false;
// Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs
if (PPCSubTarget->hasSPE()) {
unsigned Opc;
if (DstVT == MVT::f32)
Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
else
Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
unsigned DestReg = createResultReg(&PPC::SPERCRegClass);
// Generate the convert.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
.addReg(SrcReg);
updateValueMap(I, DestReg);
return true;
}
// We can only lower an unsigned convert if we have the newer // We can only lower an unsigned convert if we have the newer
// floating-point conversion operations. // floating-point conversion operations.
if (!IsSigned && !PPCSubTarget->hasFPCVT()) if (!IsSigned && !PPCSubTarget->hasFPCVT())
return false; return false;
// FIXME: For now we require the newer floating-point conversion operations // FIXME: For now we require the newer floating-point conversion operations
// (which are present only on P7 and A2 server models) when converting // (which are present only on P7 and A2 server models) when converting
// to single-precision float. Otherwise we have to generate a lot of // to single-precision float. Otherwise we have to generate a lot of
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesbool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
MVT DstVT, SrcVT; MVT DstVT, SrcVT;
Type *DstTy = I->getType(); Type *DstTy = I->getType();
if (!isTypeLegal(DstTy, DstVT)) if (!isTypeLegal(DstTy, DstVT))
return false; return false;
if (DstVT != MVT::i32 && DstVT != MVT::i64) if (DstVT != MVT::i32 && DstVT != MVT::i64)
return false; return false;
// If we don't have FCTIDUZ and we need it, punt to SelectionDAG. // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT()) if (DstVT == MVT::i64 && !IsSigned &&
!PPCSubTarget->hasFPCVT() && !PPCSubTarget->hasSPE())
return false; return false;
Value *Src = I->getOperand(0); Value *Src = I->getOperand(0);
Type *SrcTy = Src->getType(); Type *SrcTy = Src->getType();
if (!isTypeLegal(SrcTy, SrcVT)) if (!isTypeLegal(SrcTy, SrcVT))
return false; return false;
if (SrcVT != MVT::f32 && SrcVT != MVT::f64) if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
Show All 11 Lines if (InRC == &PPC::F4RCRegClass) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), TmpReg) TII.get(TargetOpcode::COPY), TmpReg)
.addReg(SrcReg); .addReg(SrcReg);
SrcReg = TmpReg; SrcReg = TmpReg;
} }
// Determine the opcode for the conversion, which takes place // Determine the opcode for the conversion, which takes place
// entirely within FPRs. // entirely within FPRs.
unsigned DestReg = createResultReg(&PPC::F8RCRegClass); unsigned DestReg;
unsigned Opc; unsigned Opc;
if (PPCSubTarget->hasSPE()) {
if (DstVT == MVT::i32) {
DestReg = createResultReg(&PPC::GPRCRegClass);
if (IsSigned)
Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
else
Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
}
} else {
DestReg = createResultReg(&PPC::F8RCRegClass);
if (DstVT == MVT::i32) if (DstVT == MVT::i32)
if (IsSigned) if (IsSigned)
Opc = PPC::FCTIWZ; Opc = PPC::FCTIWZ;
else else
Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ; Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
else else
Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ; Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
}
// Generate the convert. // Generate the convert.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
.addReg(SrcReg); .addReg(SrcReg);
// Now move the integer value from a float register to an integer register. // Now move the integer value from a float register to an integer register.
unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); unsigned IntReg = PPCSubTarget->hasSPE() ? DestReg :
PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
if (IntReg == 0) if (IntReg == 0)
return false; return false;
updateValueMap(I, IntReg); updateValueMap(I, IntReg);
return true; return true;
} }
// Attempt to fast-select a binary integer operation that isn't already // Attempt to fast-select a binary integer operation that isn't already
▲ Show 20 Lines • Show All 731 Lines • ▼ Show 20 Linesunsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
// No plans to handle long double here. // No plans to handle long double here.
if (VT != MVT::f32 && VT != MVT::f64) if (VT != MVT::f32 && VT != MVT::f64)
return 0; return 0;
// All FP constants are loaded from the constant pool. // All FP constants are loaded from the constant pool.
unsigned Align = DL.getPrefTypeAlignment(CFP->getType()); unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
assert(Align > 0 && "Unexpectedly missing alignment information!"); assert(Align > 0 && "Unexpectedly missing alignment information!");
unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
const TargetRegisterClass *RC = const bool HasSPE = PPCSubTarget->hasSPE();
(VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass; const TargetRegisterClass *RC;
if (HasSPE)
RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
else
RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
nemanjaiUnsubmitted
Done
ReplyInline Actions

Can you please use the same variable name to be consistent? You have uses of UseSPE as well as HasSPE in this code. The latter seems to be more in-line with similar predicates.

nemanjai: Can you please use the same variable name to be consistent? You have uses of `UseSPE` as well…
unsigned DestReg = createResultReg(RC); unsigned DestReg = createResultReg(RC);
CodeModel::Model CModel = TM.getCodeModel(); CodeModel::Model CModel = TM.getCodeModel();
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
MachinePointerInfo::getConstantPool(*FuncInfo.MF), MachinePointerInfo::getConstantPool(*FuncInfo.MF),
MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align); MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; unsigned Opc;
if (HasSPE)
Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
else
Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
PPCFuncInfo->setUsesTOCBasePtr(); PPCFuncInfo->setUsesTOCBasePtr();
// For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)). // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
if (CModel == CodeModel::Small) { if (CModel == CodeModel::Small) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT), BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
TmpReg) TmpReg)
.addConstantPoolIndex(Idx).addReg(PPC::X2); .addConstantPoolIndex(Idx).addReg(PPC::X2);
▲ Show 20 Lines • Show All 319 Lines • ▼ Show 20 Linesbool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
// See if we can handle this address. // See if we can handle this address.
Address Addr; Address Addr;
if (!PPCComputeAddress(LI->getOperand(0), Addr)) if (!PPCComputeAddress(LI->getOperand(0), Addr))
return false; return false;
unsigned ResultReg = MI->getOperand(0).getReg(); unsigned ResultReg = MI->getOperand(0).getReg();
if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt)) if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
return false; return false;
MI->eraseFromParent(); MI->eraseFromParent();
return true; return true;
} }
// Attempt to lower call arguments in a faster way than done by // Attempt to lower call arguments in a faster way than done by
// the selection DAG code. // the selection DAG code.
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCFrameLowering.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines static const SpillSlot Offsets[] = {
{PPC::V28, -64}, {PPC::V28, -64},
{PPC::V27, -80}, {PPC::V27, -80},
{PPC::V26, -96}, {PPC::V26, -96},
{PPC::V25, -112}, {PPC::V25, -112},
{PPC::V24, -128}, {PPC::V24, -128},
{PPC::V23, -144}, {PPC::V23, -144},
{PPC::V22, -160}, {PPC::V22, -160},
{PPC::V21, -176}, {PPC::V21, -176},
{PPC::V20, -192}}; {PPC::V20, -192},
// SPE register save area (overlaps Vector save area).
{PPC::S31, -8},
{PPC::S30, -16},
{PPC::S29, -24},
{PPC::S28, -32},
{PPC::S27, -40},
{PPC::S26, -48},
{PPC::S25, -56},
{PPC::S24, -64},
{PPC::S23, -72},
{PPC::S22, -80},
{PPC::S21, -88},
{PPC::S20, -96},
{PPC::S19, -104},
{PPC::S18, -112},
{PPC::S17, -120},
{PPC::S16, -128},
{PPC::S15, -136},
{PPC::S14, -144}};
static const SpillSlot Offsets64[] = { static const SpillSlot Offsets64[] = {
// Floating-point register save area offsets. // Floating-point register save area offsets.
{PPC::F31, -8}, {PPC::F31, -8},
{PPC::F30, -16}, {PPC::F30, -16},
{PPC::F29, -24}, {PPC::F29, -24},
{PPC::F28, -32}, {PPC::F28, -32},
{PPC::F27, -40}, {PPC::F27, -40},
▲ Show 20 Lines • Show All 1,486 Lines • ▼ Show 20 Linesvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
if (CSI.empty() && !needsFP(MF)) { if (CSI.empty() && !needsFP(MF)) {
addScavengingSpillSlot(MF, RS); addScavengingSpillSlot(MF, RS);
return; return;
} }
unsigned MinGPR = PPC::R31; unsigned MinGPR = PPC::R31;
unsigned MinG8R = PPC::X31; unsigned MinG8R = PPC::X31;
unsigned MinFPR = PPC::F31; unsigned MinFPR = PPC::F31;
unsigned MinVR = PPC::V31; unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
bool HasGPSaveArea = false; bool HasGPSaveArea = false;
bool HasG8SaveArea = false; bool HasG8SaveArea = false;
bool HasFPSaveArea = false; bool HasFPSaveArea = false;
bool HasVRSAVESaveArea = false; bool HasVRSAVESaveArea = false;
bool HasVRSaveArea = false; bool HasVRSaveArea = false;
SmallVector<CalleeSavedInfo, 18> GPRegs; SmallVector<CalleeSavedInfo, 18> GPRegs;
SmallVector<CalleeSavedInfo, 18> G8Regs; SmallVector<CalleeSavedInfo, 18> G8Regs;
SmallVector<CalleeSavedInfo, 18> FPRegs; SmallVector<CalleeSavedInfo, 18> FPRegs;
SmallVector<CalleeSavedInfo, 18> VRegs; SmallVector<CalleeSavedInfo, 18> VRegs;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg(); unsigned Reg = CSI[i].getReg();
if (PPC::GPRCRegClass.contains(Reg)) { if (PPC::GPRCRegClass.contains(Reg) ||
PPC::SPE4RCRegClass.contains(Reg)) {
HasGPSaveArea = true; HasGPSaveArea = true;
GPRegs.push_back(CSI[i]); GPRegs.push_back(CSI[i]);
if (Reg < MinGPR) { if (Reg < MinGPR) {
MinGPR = Reg; MinGPR = Reg;
} }
} else if (PPC::G8RCRegClass.contains(Reg)) { } else if (PPC::G8RCRegClass.contains(Reg)) {
Show All 12 Lines if (PPC::GPRCRegClass.contains(Reg) ||
if (Reg < MinFPR) { if (Reg < MinFPR) {
MinFPR = Reg; MinFPR = Reg;
} }
} else if (PPC::CRBITRCRegClass.contains(Reg) || } else if (PPC::CRBITRCRegClass.contains(Reg) ||
PPC::CRRCRegClass.contains(Reg)) { PPC::CRRCRegClass.contains(Reg)) {
; // do nothing, as we already know whether CRs are spilled ; // do nothing, as we already know whether CRs are spilled
} else if (PPC::VRSAVERCRegClass.contains(Reg)) { } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
HasVRSAVESaveArea = true; HasVRSAVESaveArea = true;
} else if (PPC::VRRCRegClass.contains(Reg)) { } else if (PPC::VRRCRegClass.contains(Reg) ||
PPC::SPERCRegClass.contains(Reg)) {
// Altivec and SPE are mutually exclusive, but have the same stack
// alignment requirements, so overload the save area for both cases.
HasVRSaveArea = true; HasVRSaveArea = true;
VRegs.push_back(CSI[i]); VRegs.push_back(CSI[i]);
if (Reg < MinVR) { if (Reg < MinVR) {
MinVR = Reg; MinVR = Reg;
} }
} else { } else {
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI)); MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
} }
} }
LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
} }
// Both Altivec and SPE have the same alignment and padding requirements
// within the stack frame.
if (HasVRSaveArea) { if (HasVRSaveArea) {
// Insert alignment padding, we need 16-byte alignment. Note: for positive // Insert alignment padding, we need 16-byte alignment. Note: for positive
// number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since // number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since
// we are using negative number here (the stack grows downward). We should // we are using negative number here (the stack grows downward). We should
// use formula : y = x & (~(n-1)). Where x is the size before aligning, n // use formula : y = x & (~(n-1)). Where x is the size before aligning, n
// is the alignment size ( n = 16 here) and y is the size after aligning. // is the alignment size ( n = 16 here) and y is the size after aligning.
assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!"); assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
LowerBound &= ~(15); LowerBound &= ~(15);
for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
int FI = VRegs[i].getFrameIdx(); int FI = VRegs[i].getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI)); MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
} }
} }
addScavengingSpillSlot(MF, RS); addScavengingSpillSlot(MF, RS);
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

This entire block is common with the one directly above it. Can you combine them and just use HasSPESaveArea in a conditional operator on the only line that is different? If you do that, please update the comment to specify that the two save areas have the same alignment requirements.

nemanjai: This entire block is common with the one directly above it. Can you combine them and just use…
} }
void void
PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
RegScavenger *RS) const { RegScavenger *RS) const {
// Reserve a slot closest to SP or frame pointer if we have a dynalloc or // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
// a large stack, which will require scavenging a register to materialize a // a large stack, which will require scavenging a register to materialize a
// large offset. // large offset.
▲ Show 20 Lines • Show All 276 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Show First 20 Lines • Show All 3,610 Lines • ▼ Show 20 Lines if (CC == ISD::SETEQ || CC == ISD::SETNE) {
int16_t SImm; int16_t SImm;
if (isIntS16Immediate(RHS, SImm)) if (isIntS16Immediate(RHS, SImm))
return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF, dl)), getI64Imm(SImm & 0xFFFF, dl)),
0); 0);
Opc = PPC::CMPD; Opc = PPC::CMPD;
} }
} else if (LHS.getValueType() == MVT::f32) { } else if (LHS.getValueType() == MVT::f32) {
if (PPCSubTarget->hasSPE()) {
switch (CC) {
default:
case ISD::SETEQ:
case ISD::SETNE:
Opc = PPC::EFSCMPEQ;
break;
case ISD::SETLT:
case ISD::SETGE:
case ISD::SETOLT:
case ISD::SETOGE:
case ISD::SETULT:
case ISD::SETUGE:
Opc = PPC::EFSCMPLT;
break;
case ISD::SETGT:
case ISD::SETLE:
case ISD::SETOGT:
case ISD::SETOLE:
case ISD::SETUGT:
case ISD::SETULE:
Opc = PPC::EFSCMPGT;
break;
}
} else
Opc = PPC::FCMPUS; Opc = PPC::FCMPUS;
} else if (LHS.getValueType() == MVT::f64) { } else if (LHS.getValueType() == MVT::f64) {
if (PPCSubTarget->hasSPE()) {
switch (CC) {
default:
case ISD::SETEQ:
case ISD::SETNE:
Opc = PPC::EFDCMPEQ;
break;
case ISD::SETLT:
case ISD::SETGE:
case ISD::SETOLT:
case ISD::SETOGE:
case ISD::SETULT:
case ISD::SETUGE:
Opc = PPC::EFDCMPLT;
break;
case ISD::SETGT:
case ISD::SETLE:
case ISD::SETOGT:
case ISD::SETOLE:
case ISD::SETUGT:
case ISD::SETULE:
Opc = PPC::EFDCMPGT;
break;
}
} else
Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
} else { } else {
assert(LHS.getValueType() == MVT::f128 && "Unknown vt!"); assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
assert(PPCSubTarget->hasVSX() && "__float128 requires VSX"); assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
Opc = PPC::XSCMPUQP; Opc = PPC::XSCMPUQP;
} }
return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
} }
▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Linesbool PPCDAGToDAGISel::trySETCC(SDNode *N) {
} }
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
// Altivec Vector compare instructions do not set any CR register by default and // Altivec Vector compare instructions do not set any CR register by default and
// vector compare operations return the same type as the operands. // vector compare operations return the same type as the operands.
if (LHS.getValueType().isVector()) { if (LHS.getValueType().isVector()) {
if (PPCSubTarget->hasQPX()) if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE())
return false; return false;
EVT VecVT = LHS.getValueType(); EVT VecVT = LHS.getValueType();
bool Swap, Negate; bool Swap, Negate;
unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC, unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
PPCSubTarget->hasVSX(), Swap, Negate); PPCSubTarget->hasVSX(), Swap, Negate);
if (Swap) if (Swap)
std::swap(LHS, RHS); std::swap(LHS, RHS);
Show All 13 Linesbool PPCDAGToDAGISel::trySETCC(SDNode *N) {
if (PPCSubTarget->useCRBits()) if (PPCSubTarget->useCRBits())
return false; return false;
bool Inv; bool Inv;
unsigned Idx = getCRIdxForSetCC(CC, Inv); unsigned Idx = getCRIdxForSetCC(CC, Inv);
SDValue CCReg = SelectCC(LHS, RHS, CC, dl); SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
SDValue IntCR; SDValue IntCR;
// SPE e*cmp* instructions only set the 'gt' bit, so hard-code that
// The correct compare instruction is already set by SelectCC()
if (PPCSubTarget->hasSPE() && LHS.getValueType().isFloatingPoint()) {
Idx = 1;
}
// Force the ccreg into CR7. // Force the ccreg into CR7.
SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDValue InFlag(nullptr, 0); // Null incoming flag value. SDValue InFlag(nullptr, 0); // Null incoming flag value.
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
InFlag).getValue(1); InFlag).getValue(1);
IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
▲ Show 20 Lines • Show All 615 Lines • ▼ Show 20 Lines case ISD::SELECT_CC: {
unsigned BROpc = getPredicateForSetCC(CC); unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp; unsigned SelectCCOp;
if (N->getValueType(0) == MVT::i32) if (N->getValueType(0) == MVT::i32)
SelectCCOp = PPC::SELECT_CC_I4; SelectCCOp = PPC::SELECT_CC_I4;
else if (N->getValueType(0) == MVT::i64) else if (N->getValueType(0) == MVT::i64)
SelectCCOp = PPC::SELECT_CC_I8; SelectCCOp = PPC::SELECT_CC_I8;
else if (N->getValueType(0) == MVT::f32) else if (N->getValueType(0) == MVT::f32) {
if (PPCSubTarget->hasP8Vector()) if (PPCSubTarget->hasP8Vector())
SelectCCOp = PPC::SELECT_CC_VSSRC; SelectCCOp = PPC::SELECT_CC_VSSRC;
else if (PPCSubTarget->hasSPE())
SelectCCOp = PPC::SELECT_CC_SPE4;
else else
SelectCCOp = PPC::SELECT_CC_F4; SelectCCOp = PPC::SELECT_CC_F4;
else if (N->getValueType(0) == MVT::f64) } else if (N->getValueType(0) == MVT::f64) {
if (PPCSubTarget->hasVSX()) if (PPCSubTarget->hasVSX())
SelectCCOp = PPC::SELECT_CC_VSFRC; SelectCCOp = PPC::SELECT_CC_VSFRC;
else if (PPCSubTarget->hasSPE())
SelectCCOp = PPC::SELECT_CC_SPE;
else else
SelectCCOp = PPC::SELECT_CC_F8; SelectCCOp = PPC::SELECT_CC_F8;
else if (N->getValueType(0) == MVT::f128) } else if (N->getValueType(0) == MVT::f128)
SelectCCOp = PPC::SELECT_CC_F16; SelectCCOp = PPC::SELECT_CC_F16;
else if (PPCSubTarget->hasSPE())
SelectCCOp = PPC::SELECT_CC_SPE;
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64) else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
SelectCCOp = PPC::SELECT_CC_QFRC; SelectCCOp = PPC::SELECT_CC_QFRC;
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32) else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
SelectCCOp = PPC::SELECT_CC_QSRC; SelectCCOp = PPC::SELECT_CC_QSRC;
else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1) else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
SelectCCOp = PPC::SELECT_CC_QBRC; SelectCCOp = PPC::SELECT_CC_QBRC;
else if (N->getValueType(0) == MVT::v2f64 || else if (N->getValueType(0) == MVT::v2f64 ||
N->getValueType(0) == MVT::v2i64) N->getValueType(0) == MVT::v2i64)
▲ Show 20 Lines • Show All 767 Lines • ▼ Show 20 Lines for (SDNode &Node : CurDAG->allnodes()) {
case PPC::BCn: case PPC::BCn:
case PPC::SELECT_I4: case PPC::SELECT_I4:
case PPC::SELECT_I8: case PPC::SELECT_I8:
case PPC::SELECT_F4: case PPC::SELECT_F4:
case PPC::SELECT_F8: case PPC::SELECT_F8:
case PPC::SELECT_QFRC: case PPC::SELECT_QFRC:
case PPC::SELECT_QSRC: case PPC::SELECT_QSRC:
case PPC::SELECT_QBRC: case PPC::SELECT_QBRC:
case PPC::SELECT_SPE:
case PPC::SELECT_SPE4:
case PPC::SELECT_VRRC: case PPC::SELECT_VRRC:
case PPC::SELECT_VSFRC: case PPC::SELECT_VSFRC:
case PPC::SELECT_VSSRC: case PPC::SELECT_VSSRC:
case PPC::SELECT_VSRC: { case PPC::SELECT_VSRC: {
SDValue Op = MachineNode->getOperand(0); SDValue Op = MachineNode->getOperand(0);
if (Op.isMachineOpcode()) { if (Op.isMachineOpcode()) {
if (Op.getMachineOpcode() == PPC::CRSET) if (Op.getMachineOpcode() == PPC::CRSET)
Op1Set = true; Op1Set = true;
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines for (SDNode &Node : CurDAG->allnodes()) {
break; break;
case PPC::SELECT_I4: case PPC::SELECT_I4:
case PPC::SELECT_I8: case PPC::SELECT_I8:
case PPC::SELECT_F4: case PPC::SELECT_F4:
case PPC::SELECT_F8: case PPC::SELECT_F8:
case PPC::SELECT_QFRC: case PPC::SELECT_QFRC:
case PPC::SELECT_QSRC: case PPC::SELECT_QSRC:
case PPC::SELECT_QBRC: case PPC::SELECT_QBRC:
case PPC::SELECT_SPE:
case PPC::SELECT_SPE4:
case PPC::SELECT_VRRC: case PPC::SELECT_VRRC:
case PPC::SELECT_VSFRC: case PPC::SELECT_VSFRC:
case PPC::SELECT_VSSRC: case PPC::SELECT_VSSRC:
case PPC::SELECT_VSRC: case PPC::SELECT_VSRC:
if (Op1Set) if (Op1Set)
ResNode = MachineNode->getOperand(1).getNode(); ResNode = MachineNode->getOperand(1).getNode();
else if (Op1Unset) else if (Op1Unset)
ResNode = MachineNode->getOperand(2).getNode(); ResNode = MachineNode->getOperand(2).getNode();
▲ Show 20 Lines • Show All 579 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCISelLowering.h

Show First 20 Lines • Show All 568 Lines • ▼ Show 20 Lines TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
const override { const override {
if (VT.getScalarSizeInBits() % 8 == 0) if (VT.getScalarSizeInBits() % 8 == 0)
return TypeWidenVector; return TypeWidenVector;
return TargetLoweringBase::getPreferredVectorAction(VT); return TargetLoweringBase::getPreferredVectorAction(VT);
} }
bool useSoftFloat() const override; bool useSoftFloat() const override;
bool hasSPE() const;
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
return MVT::i32; return MVT::i32;
} }
bool isCheapToSpeculateCttz() const override { bool isCheapToSpeculateCttz() const override {
return true; return true;
} }
▲ Show 20 Lines • Show All 279 Lines • ▼ Show 20 Lines public:
unsigned getJumpTableEncoding() const override; unsigned getJumpTableEncoding() const override;
bool isJumpTableRelative() const override; bool isJumpTableRelative() const override;
SDValue getPICJumpTableRelocBase(SDValue Table, SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
unsigned JTI, unsigned JTI,
MCContext &Ctx) const override; MCContext &Ctx) const override;
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
EVT VT) const override;
MVT getRegisterTypeForCallingConv(MVT VT) const;
MVT getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const;
private: private:
struct ReuseLoadInfo { struct ReuseLoadInfo {
SDValue Ptr; SDValue Ptr;
SDValue Chain; SDValue Chain;
SDValue ResChain; SDValue ResChain;
MachinePointerInfo MPI; MachinePointerInfo MPI;
bool IsDereferenceable = false; bool IsDereferenceable = false;
bool IsInvariant = false; bool IsInvariant = false;
▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 131 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// On PPC32/64, arguments smaller than 4/8 bytes are extended, so all // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
// arguments are at least 4/8 bytes aligned. // arguments are at least 4/8 bytes aligned.
bool isPPC64 = Subtarget.isPPC64(); bool isPPC64 = Subtarget.isPPC64();
setMinStackArgumentAlignment(isPPC64 ? 8:4); setMinStackArgumentAlignment(isPPC64 ? 8:4);
// Set up the register classes. // Set up the register classes.
addRegisterClass(MVT::i32, &PPC::GPRCRegClass); addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
if (!useSoftFloat()) { if (!useSoftFloat()) {
if (hasSPE()) {
addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
} else {
addRegisterClass(MVT::f32, &PPC::F4RCRegClass); addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
addRegisterClass(MVT::f64, &PPC::F8RCRegClass); addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
} }
}
// Match BITREVERSE to customized fast code sequence in the td file. // Match BITREVERSE to customized fast code sequence in the td file.
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
// Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended. // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD. // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
for (MVT VT : MVT::integer_valuetypes()) { for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
} }
setTruncStoreAction(MVT::f64, MVT::f32, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// PowerPC has pre-inc load and store's. // PowerPC has pre-inc load and store's.
setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
if (!Subtarget.hasSPE()) {
setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
}
// PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry. // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
for (MVT VT : ScalarIntVTs) { for (MVT VT : ScalarIntVTs) {
setOperationAction(ISD::ADDC, VT, Legal); setOperationAction(ISD::ADDC, VT, Legal);
setOperationAction(ISD::ADDE, VT, Legal); setOperationAction(ISD::ADDE, VT, Legal);
setOperationAction(ISD::SUBC, VT, Legal); setOperationAction(ISD::SUBC, VT, Legal);
setOperationAction(ISD::SUBE, VT, Legal); setOperationAction(ISD::SUBE, VT, Legal);
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SDIVREM, MVT::i64, Expand); setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
// We don't support sin/cos/sqrt/fmod/pow // We don't support sin/cos/sqrt/fmod/pow
setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FSINCOS, MVT::f64, Expand); setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FPOW , MVT::f64, Expand);
setOperationAction(ISD::FMA , MVT::f64, Legal);
setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FSINCOS, MVT::f32, Expand); setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand); setOperationAction(ISD::FPOW , MVT::f32, Expand);
if (Subtarget.hasSPE()) {
setOperationAction(ISD::FMA , MVT::f64, Expand);
setOperationAction(ISD::FMA , MVT::f32, Expand);
} else {
setOperationAction(ISD::FMA , MVT::f64, Legal);
setOperationAction(ISD::FMA , MVT::f32, Legal); setOperationAction(ISD::FMA , MVT::f32, Legal);
}
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
// If we're enabling GP optimizations, use hardware square root // If we're enabling GP optimizations, use hardware square root
if (!Subtarget.hasFSQRT() && if (!Subtarget.hasFSQRT() &&
!(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
Subtarget.hasFRE())) Subtarget.hasFRE()))
setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f64, Expand);
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines if (!Subtarget.useCRBits())
setOperationAction(ISD::SETCC, MVT::i32, Custom); setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND which requires SetCC // PowerPC does not have BRCOND which requires SetCC
if (!Subtarget.useCRBits()) if (!Subtarget.useCRBits())
setOperationAction(ISD::BRCOND, MVT::Other, Expand); setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_JT, MVT::Other, Expand);
if (Subtarget.hasSPE()) {
// SPE has built-in conversions
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
} else {
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// PowerPC does not have [U|S]INT_TO_FP // PowerPC does not have [U|S]INT_TO_FP
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
}
if (Subtarget.hasDirectMove() && isPPC64) { if (Subtarget.hasDirectMove() && isPPC64) {
setOperationAction(ISD::BITCAST, MVT::f32, Legal); setOperationAction(ISD::BITCAST, MVT::f32, Legal);
setOperationAction(ISD::BITCAST, MVT::i32, Legal); setOperationAction(ISD::BITCAST, MVT::i32, Legal);
setOperationAction(ISD::BITCAST, MVT::i64, Legal); setOperationAction(ISD::BITCAST, MVT::i64, Legal);
setOperationAction(ISD::BITCAST, MVT::f64, Legal); setOperationAction(ISD::BITCAST, MVT::f64, Legal);
} else { } else {
setOperationAction(ISD::BITCAST, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::f32, Expand);
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
// Comparisons that require checking two conditions. // Comparisons that require checking two conditions.
if (Subtarget.hasSPE()) {
setCondCodeAction(ISD::SETO, MVT::f32, Expand);
setCondCodeAction(ISD::SETO, MVT::f64, Expand);
setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
}
setCondCodeAction(ISD::SETULT, MVT::f32, Expand); setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::f64, Expand); setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
Show All 11 Lines if (Subtarget.has64BitSupport()) {
// This is just the low 32 bits of a (signed) fp->i64 conversion. // This is just the low 32 bits of a (signed) fp->i64 conversion.
// We cannot do this with Promote because i64 is not a legal type. // We cannot do this with Promote because i64 is not a legal type.
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
} else { } else {
// PowerPC does not have FP_TO_UINT on 32-bit implementations. // PowerPC does not have FP_TO_UINT on 32-bit implementations.
if (Subtarget.hasSPE())
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
else
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
} }
// With the instructions enabled under FPCVT, we can do everything. // With the instructions enabled under FPCVT, we can do everything.
if (Subtarget.hasFPCVT()) { if (Subtarget.hasFPCVT()) {
if (Subtarget.has64BitSupport()) { if (Subtarget.has64BitSupport()) {
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
▲ Show 20 Lines • Show All 685 Lines • ▼ Show 20 Linesunsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
// 16byte and wider vectors are passed on 16byte boundary. // 16byte and wider vectors are passed on 16byte boundary.
// The rest is 8 on PPC64 and 4 on PPC32 boundary. // The rest is 8 on PPC64 and 4 on PPC32 boundary.
unsigned Align = Subtarget.isPPC64() ? 8 : 4; unsigned Align = Subtarget.isPPC64() ? 8 : 4;
if (Subtarget.hasAltivec() || Subtarget.hasQPX()) if (Subtarget.hasAltivec() || Subtarget.hasQPX())
getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16); getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
return Align; return Align;
} }
unsigned PPCTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
EVT VT) const {
if (Subtarget.hasSPE() && VT == MVT::f64)
return 2;
return PPCTargetLowering::getNumRegisters(Context, VT);
}
MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const {
if (Subtarget.hasSPE() && VT == MVT::f64)
return MVT::i32;
return PPCTargetLowering::getRegisterType(Context, VT);
}
MVT PPCTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
if (Subtarget.hasSPE() && VT == MVT::f64)
return MVT::i32;
return PPCTargetLowering::getRegisterType(VT);
}
bool PPCTargetLowering::useSoftFloat() const { bool PPCTargetLowering::useSoftFloat() const {
return Subtarget.useSoftFloat(); return Subtarget.useSoftFloat();
} }
bool PPCTargetLowering::hasSPE() const {
return Subtarget.hasSPE();
}
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((PPCISD::NodeType)Opcode) { switch ((PPCISD::NodeType)Opcode) {
case PPCISD::FIRST_NUMBER: break; case PPCISD::FIRST_NUMBER: break;
case PPCISD::FSEL: return "PPCISD::FSEL"; case PPCISD::FSEL: return "PPCISD::FSEL";
case PPCISD::FCFID: return "PPCISD::FCFID"; case PPCISD::FCFID: return "PPCISD::FCFID";
case PPCISD::FCFIDU: return "PPCISD::FCFIDU"; case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
case PPCISD::FCFIDS: return "PPCISD::FCFIDS"; case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS"; case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
▲ Show 20 Lines • Show All 2,147 Lines • ▼ Show 20 LinesSDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
// Assign locations to all of the incoming arguments. // Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext()); *DAG.getContext());
// Reserve space for the linkage area on the stack. // Reserve space for the linkage area on the stack.
unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
CCInfo.AllocateStack(LinkageSize, PtrByteSize); CCInfo.AllocateStack(LinkageSize, PtrByteSize);
if (useSoftFloat()) if (useSoftFloat() || hasSPE())
CCInfo.PreAnalyzeFormalArguments(Ins); CCInfo.PreAnalyzeFormalArguments(Ins);
CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
CCInfo.clearWasPPCF128(); CCInfo.clearWasPPCF128();
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i]; CCValAssign &VA = ArgLocs[i];
// Arguments stored in registers. // Arguments stored in registers.
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
const TargetRegisterClass *RC; const TargetRegisterClass *RC;
EVT ValVT = VA.getValVT(); EVT ValVT = VA.getValVT();
switch (ValVT.getSimpleVT().SimpleTy) { switch (ValVT.getSimpleVT().SimpleTy) {
default: default:
llvm_unreachable("ValVT not supported by formal arguments Lowering"); llvm_unreachable("ValVT not supported by formal arguments Lowering");
case MVT::i1: case MVT::i1:
case MVT::i32: case MVT::i32:
RC = &PPC::GPRCRegClass; RC = &PPC::GPRCRegClass;
break; break;
case MVT::f32: case MVT::f32:
if (Subtarget.hasP8Vector()) if (Subtarget.hasP8Vector())
RC = &PPC::VSSRCRegClass; RC = &PPC::VSSRCRegClass;
else if (Subtarget.hasSPE())
RC = &PPC::SPE4RCRegClass;
else else
RC = &PPC::F4RCRegClass; RC = &PPC::F4RCRegClass;
break; break;
case MVT::f64: case MVT::f64:
if (Subtarget.hasVSX()) if (Subtarget.hasVSX())
RC = &PPC::VSFRCRegClass; RC = &PPC::VSFRCRegClass;
else if (Subtarget.hasSPE())
RC = &PPC::SPERCRegClass;
else else
RC = &PPC::F8RCRegClass; RC = &PPC::F8RCRegClass;
break; break;
case MVT::v16i8: case MVT::v16i8:
case MVT::v8i16: case MVT::v8i16:
case MVT::v4i32: case MVT::v4i32:
RC = &PPC::VRRCRegClass; RC = &PPC::VRRCRegClass;
break; break;
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines if (isVarArg) {
const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
static const MCPhysReg FPArgRegs[] = { static const MCPhysReg FPArgRegs[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8 PPC::F8
}; };
unsigned NumFPArgRegs = array_lengthof(FPArgRegs); unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
if (useSoftFloat()) if (useSoftFloat() || hasSPE())
NumFPArgRegs = 0; NumFPArgRegs = 0;
FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs)); FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs)); FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
// Make room for NumGPArgRegs and NumFPArgRegs. // Make room for NumGPArgRegs and NumFPArgRegs.
int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
▲ Show 20 Lines • Show All 6,733 Lines • ▼ Show 20 Lines TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
MI.getOpcode() == PPC::SELECT_CC_F16 || MI.getOpcode() == PPC::SELECT_CC_F16 ||
MI.getOpcode() == PPC::SELECT_CC_QFRC || MI.getOpcode() == PPC::SELECT_CC_QFRC ||
MI.getOpcode() == PPC::SELECT_CC_QSRC || MI.getOpcode() == PPC::SELECT_CC_QSRC ||
MI.getOpcode() == PPC::SELECT_CC_QBRC || MI.getOpcode() == PPC::SELECT_CC_QBRC ||
MI.getOpcode() == PPC::SELECT_CC_VRRC || MI.getOpcode() == PPC::SELECT_CC_VRRC ||
MI.getOpcode() == PPC::SELECT_CC_VSFRC || MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
MI.getOpcode() == PPC::SELECT_CC_VSSRC || MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
MI.getOpcode() == PPC::SELECT_CC_VSRC || MI.getOpcode() == PPC::SELECT_CC_VSRC ||
MI.getOpcode() == PPC::SELECT_CC_SPE4 ||
MI.getOpcode() == PPC::SELECT_CC_SPE ||
MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I4 ||
MI.getOpcode() == PPC::SELECT_I8 || MI.getOpcode() == PPC::SELECT_I8 ||
MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F4 ||
MI.getOpcode() == PPC::SELECT_F8 || MI.getOpcode() == PPC::SELECT_F8 ||
MI.getOpcode() == PPC::SELECT_F16 || MI.getOpcode() == PPC::SELECT_F16 ||
MI.getOpcode() == PPC::SELECT_QFRC || MI.getOpcode() == PPC::SELECT_QFRC ||
MI.getOpcode() == PPC::SELECT_QSRC || MI.getOpcode() == PPC::SELECT_QSRC ||
MI.getOpcode() == PPC::SELECT_QBRC || MI.getOpcode() == PPC::SELECT_QBRC ||
MI.getOpcode() == PPC::SELECT_SPE ||
MI.getOpcode() == PPC::SELECT_SPE4 ||
MI.getOpcode() == PPC::SELECT_VRRC || MI.getOpcode() == PPC::SELECT_VRRC ||
MI.getOpcode() == PPC::SELECT_VSFRC || MI.getOpcode() == PPC::SELECT_VSFRC ||
MI.getOpcode() == PPC::SELECT_VSSRC || MI.getOpcode() == PPC::SELECT_VSSRC ||
MI.getOpcode() == PPC::SELECT_VSRC) { MI.getOpcode() == PPC::SELECT_VSRC) {
// The incoming instruction knows the destination vreg to set, the // The incoming instruction knows the destination vreg to set, the
// condition code register to branch on, the true/false values to // condition code register to branch on, the true/false values to
// select between, and a branch opcode to use. // select between, and a branch opcode to use.
Show All 17 Lines if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
// Next, add the true and fallthrough blocks as its successors. // Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB); BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB); BB->addSuccessor(sinkMBB);
if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 || if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 || MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
MI.getOpcode() == PPC::SELECT_F16 || MI.getOpcode() == PPC::SELECT_F16 ||
MI.getOpcode() == PPC::SELECT_SPE4 ||
MI.getOpcode() == PPC::SELECT_SPE ||
MI.getOpcode() == PPC::SELECT_QFRC || MI.getOpcode() == PPC::SELECT_QFRC ||
MI.getOpcode() == PPC::SELECT_QSRC || MI.getOpcode() == PPC::SELECT_QSRC ||
MI.getOpcode() == PPC::SELECT_QBRC || MI.getOpcode() == PPC::SELECT_QBRC ||
MI.getOpcode() == PPC::SELECT_VRRC || MI.getOpcode() == PPC::SELECT_VRRC ||
MI.getOpcode() == PPC::SELECT_VSFRC || MI.getOpcode() == PPC::SELECT_VSFRC ||
MI.getOpcode() == PPC::SELECT_VSSRC || MI.getOpcode() == PPC::SELECT_VSSRC ||
MI.getOpcode() == PPC::SELECT_VSRC) { MI.getOpcode() == PPC::SELECT_VSRC) {
BuildMI(BB, dl, TII->get(PPC::BC)) BuildMI(BB, dl, TII->get(PPC::BC))
▲ Show 20 Lines • Show All 2,977 Lines • ▼ Show 20 Lines case 'r': // R0-R31
if (VT == MVT::i64 && Subtarget.isPPC64()) if (VT == MVT::i64 && Subtarget.isPPC64())
return std::make_pair(0U, &PPC::G8RCRegClass); return std::make_pair(0U, &PPC::G8RCRegClass);
return std::make_pair(0U, &PPC::GPRCRegClass); return std::make_pair(0U, &PPC::GPRCRegClass);
// 'd' and 'f' constraints are both defined to be "the floating point // 'd' and 'f' constraints are both defined to be "the floating point
// registers", where one is for 32-bit and the other for 64-bit. We don't // registers", where one is for 32-bit and the other for 64-bit. We don't
// really care overly much here so just give them all the same reg classes. // really care overly much here so just give them all the same reg classes.
case 'd': case 'd':
case 'f': case 'f':
if (Subtarget.hasSPE()) {
if (VT == MVT::f32 || VT == MVT::i32)
return std::make_pair(0U, &PPC::SPE4RCRegClass);
if (VT == MVT::f64 || VT == MVT::i64)
return std::make_pair(0U, &PPC::SPERCRegClass);
} else {
if (VT == MVT::f32 || VT == MVT::i32) if (VT == MVT::f32 || VT == MVT::i32)
return std::make_pair(0U, &PPC::F4RCRegClass); return std::make_pair(0U, &PPC::F4RCRegClass);
if (VT == MVT::f64 || VT == MVT::i64) if (VT == MVT::f64 || VT == MVT::i64)
return std::make_pair(0U, &PPC::F8RCRegClass); return std::make_pair(0U, &PPC::F8RCRegClass);
if (VT == MVT::v4f64 && Subtarget.hasQPX()) if (VT == MVT::v4f64 && Subtarget.hasQPX())
return std::make_pair(0U, &PPC::QFRCRegClass); return std::make_pair(0U, &PPC::QFRCRegClass);
if (VT == MVT::v4f32 && Subtarget.hasQPX()) if (VT == MVT::v4f32 && Subtarget.hasQPX())
return std::make_pair(0U, &PPC::QSRCRegClass); return std::make_pair(0U, &PPC::QSRCRegClass);
}
break; break;
case 'v': case 'v':
if (VT == MVT::v4f64 && Subtarget.hasQPX()) if (VT == MVT::v4f64 && Subtarget.hasQPX())
return std::make_pair(0U, &PPC::QFRCRegClass); return std::make_pair(0U, &PPC::QFRCRegClass);
if (VT == MVT::v4f32 && Subtarget.hasQPX()) if (VT == MVT::v4f32 && Subtarget.hasQPX())
return std::make_pair(0U, &PPC::QSRCRegClass); return std::make_pair(0U, &PPC::QSRCRegClass);
if (Subtarget.hasAltivec()) if (Subtarget.hasAltivec())
return std::make_pair(0U, &PPC::VRRCRegClass); return std::make_pair(0U, &PPC::VRRCRegClass);
▲ Show 20 Lines • Show All 829 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstrInfo.cpp

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesenum SpillOpcodeKey {
SOK_VSXVectorSpill, SOK_VSXVectorSpill,
SOK_VectorFloat8Spill, SOK_VectorFloat8Spill,
SOK_VectorFloat4Spill, SOK_VectorFloat4Spill,
SOK_VRSaveSpill, SOK_VRSaveSpill,
SOK_QuadFloat8Spill, SOK_QuadFloat8Spill,
SOK_QuadFloat4Spill, SOK_QuadFloat4Spill,
SOK_QuadBitSpill, SOK_QuadBitSpill,
SOK_SpillToVSR, SOK_SpillToVSR,
SOK_SPESpill,
SOK_SPE4Spill,
SOK_LastOpcodeSpill // This must be last on the enum. SOK_LastOpcodeSpill // This must be last on the enum.
}; };
// Pin the vtable to this file. // Pin the vtable to this file.
void PPCInstrInfo::anchor() {} void PPCInstrInfo::anchor() {}
PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI) PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines case PPC::EXTSW_32_64:
SrcReg = MI.getOperand(1).getReg(); SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg(); DstReg = MI.getOperand(0).getReg();
SubIdx = PPC::sub_32; SubIdx = PPC::sub_32;
return true; return true;
} }
} }
unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const { int &FrameIndex) const {
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
nemanjaiUnsubmitted
Done
ReplyInline Actions

We've recently completely changed the handling for these functions for spills and restores, so this part will need to be reworked to merge with ToT.

nemanjai: We've recently completely changed the handling for these functions for spills and restores, so…
jhibbitsAuthorUnsubmitted
Not Done
ReplyInline Actions

I've recently rebased and reconciled. I'll update the review shortly.

jhibbits: I've recently rebased and reconciled. I'll update the review shortly.
const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray(); const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill; const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
if (End != std::find(OpcodesForSpill, End, Opcode)) { if (End != std::find(OpcodesForSpill, End, Opcode)) {
// Check for the operands added by addFrameReference (the immediate is the // Check for the operands added by addFrameReference (the immediate is the
// offset which defaults to 0). // offset which defaults to 0).
if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
MI.getOperand(2).isFI()) { MI.getOperand(2).isFI()) {
▲ Show 20 Lines • Show All 635 Lines • ▼ Show 20 Lines if (PPC::CRBITRCRegClass.contains(SrcReg) &&
NumGPRtoVSRSpill++; NumGPRtoVSRSpill++;
getKillRegState(KillSrc); getKillRegState(KillSrc);
return; return;
} else if (PPC::VSFRCRegClass.contains(SrcReg) && } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
PPC::G8RCRegClass.contains(DestReg)) { PPC::G8RCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
getKillRegState(KillSrc); getKillRegState(KillSrc);
return; return;
} else if (PPC::SPERCRegClass.contains(SrcReg) &&
PPC::SPE4RCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
getKillRegState(KillSrc);
return;
} else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
PPC::SPERCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
getKillRegState(KillSrc);
return;
} }
unsigned Opc; unsigned Opc;
if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::OR; Opc = PPC::OR;
else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
Opc = PPC::OR8; Opc = PPC::OR8;
else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
Opc = PPC::FMR; Opc = PPC::FMR;
else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
Show All 16 Linesvoid PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::QVFMR; Opc = PPC::QVFMR;
else if (PPC::QSRCRegClass.contains(DestReg, SrcReg)) else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::QVFMRs; Opc = PPC::QVFMRs;
else if (PPC::QBRCRegClass.contains(DestReg, SrcReg)) else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::QVFMRb; Opc = PPC::QVFMRb;
else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::CROR; Opc = PPC::CROR;
else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
Opc = PPC::EVOR;
else else
llvm_unreachable("Impossible reg-to-reg copy"); llvm_unreachable("Impossible reg-to-reg copy");
const MCInstrDesc &MCID = get(Opc); const MCInstrDesc &MCID = get(Opc);
if (MCID.getNumOperands() == 3) if (MCID.getNumOperands() == 3)
BuildMI(MBB, I, DL, MCID, DestReg) BuildMI(MBB, I, DL, MCID, DestReg)
.addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
else else
Show All 12 Lines if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
OpcodeIndex = SOK_Int4Spill; OpcodeIndex = SOK_Int4Spill;
} else if (PPC::G8RCRegClass.hasSubClassEq(RC) || } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Int8Spill; OpcodeIndex = SOK_Int8Spill;
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Float8Spill; OpcodeIndex = SOK_Float8Spill;
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Float4Spill; OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPESpill;
} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRSpill; OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRBitSpill; OpcodeIndex = SOK_CRBitSpill;
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_VRVectorSpill; OpcodeIndex = SOK_VRVectorSpill;
} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_VSXVectorSpill; OpcodeIndex = SOK_VSXVectorSpill;
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
OpcodeIndex = SOK_Int4Spill; OpcodeIndex = SOK_Int4Spill;
} else if (PPC::G8RCRegClass.hasSubClassEq(RC) || } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Int8Spill; OpcodeIndex = SOK_Int8Spill;
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Float8Spill; OpcodeIndex = SOK_Float8Spill;
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_Float4Spill; OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPESpill;
} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRSpill; OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRBitSpill; OpcodeIndex = SOK_CRBitSpill;
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_VRVectorSpill; OpcodeIndex = SOK_VRVectorSpill;
} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_VSXVectorSpill; OpcodeIndex = SOK_VSXVectorSpill;
▲ Show 20 Lines • Show All 1,212 Lines • ▼ Show 20 Lines
} }
const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const { const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = { static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
// Power 8 // Power 8
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
PPC::SPILLTOVSR_ST}, PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
// Power 9 // Power 9
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
PPC::SPILLTOVSR_ST}}; PPC::SPILLTOVSR_ST}};
return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0]; return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
} }
const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const { const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = { static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
// Power 8 // Power 8
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
PPC::SPILLTOVSR_LD}, PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
// Power 9 // Power 9
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32, PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
PPC::SPILLTOVSR_LD}}; PPC::SPILLTOVSR_LD}};
return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0]; return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
} }
▲ Show 20 Lines • Show All 1,009 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 538 Lines • ▼ Show 20 Lines
} }
def crrc : RegisterOperand<CRRC> { def crrc : RegisterOperand<CRRC> {
let ParserMatchClass = PPCRegCRRCAsmOperand; let ParserMatchClass = PPCRegCRRCAsmOperand;
} }
def crrc0 : RegisterOperand<CRRC0> { def crrc0 : RegisterOperand<CRRC0> {
let ParserMatchClass = PPCRegCRRCAsmOperand; let ParserMatchClass = PPCRegCRRCAsmOperand;
} }
def PPCRegSPERCAsmOperand : AsmOperandClass {
let Name = "RegSPERC"; let PredicateMethod = "isRegNumber";
}
def sperc : RegisterOperand<SPERC> {
let ParserMatchClass = PPCRegSPERCAsmOperand;
}
def PPCRegSPE4RCAsmOperand : AsmOperandClass {
let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";
}
def spe4rc : RegisterOperand<SPE4RC> {
let ParserMatchClass = PPCRegSPE4RCAsmOperand;
}
def PPCU1ImmAsmOperand : AsmOperandClass { def PPCU1ImmAsmOperand : AsmOperandClass {
let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
} }
def u1imm : Operand<i32> { def u1imm : Operand<i32> {
let PrintMethod = "printU1ImmOperand"; let PrintMethod = "printU1ImmOperand";
let ParserMatchClass = PPCU1ImmAsmOperand; let ParserMatchClass = PPCU1ImmAsmOperand;
} }
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
def HasSPE : Predicate<"PPCSubTarget->hasSPE()">; def HasSPE : Predicate<"PPCSubTarget->hasSPE()">;
def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">; def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
def HasFPU : Predicate<"PPCSubTarget->hasFPU()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions. // PowerPC Multiclass Definitions.
multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin, string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> { list<dag> pattern> {
let BaseName = asmbase in { let BaseName = asmbase in {
▲ Show 20 Lines • Show All 324 Lines • ▼ Show 20 Lineslet usesCustomInserter = 1, // Expanded after instruction selection.
// SELECT_* pseudo instructions, like SELECT_CC_* but taking condition // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
// register bit directly. // register bit directly.
def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
[(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
[(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
let Predicates = [HasFPU] in {
def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
f4rc:$T, f4rc:$F), "#SELECT_F4", f4rc:$T, f4rc:$F), "#SELECT_F4",
[(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
f8rc:$T, f8rc:$F), "#SELECT_F8", f8rc:$T, f8rc:$F), "#SELECT_F8",
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
def SELECT_F16 : Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, def SELECT_F16 : Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
vrrc:$T, vrrc:$F), "#SELECT_F16", vrrc:$T, vrrc:$F), "#SELECT_F16",
[(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
}
def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
vrrc:$T, vrrc:$F), "#SELECT_VRRC", vrrc:$T, vrrc:$F), "#SELECT_VRRC",
[(set v4i32:$dst, [(set v4i32:$dst,
(select i1:$cond, v4i32:$T, v4i32:$F))]>; (select i1:$cond, v4i32:$T, v4i32:$F))]>;
} }
// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
// scavenge a register for it. // scavenge a register for it.
▲ Show 20 Lines • Show All 577 Lines • ▼ Show 20 Linesdef LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
"lhz $rD, $src", IIC_LdStLoad, "lhz $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (zextloadi16 iaddr:$src))]>; [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad, "lwz $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (load iaddr:$src))]>; [(set i32:$rD, (load iaddr:$src))]>;
let Predicates = [HasFPU] in {
def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
"lfs $rD, $src", IIC_LdStLFD, "lfs $rD, $src", IIC_LdStLFD,
[(set f32:$rD, (load iaddr:$src))]>; [(set f32:$rD, (load iaddr:$src))]>;
def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
"lfd $rD, $src", IIC_LdStLFD, "lfd $rD, $src", IIC_LdStLFD,
[(set f64:$rD, (load iaddr:$src))]>; [(set f64:$rD, (load iaddr:$src))]>;
}
// Unindexed (r+i) Loads with Update (preinc). // Unindexed (r+i) Loads with Update (preinc).
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lbzu $rD, $addr", IIC_LdStLoadUpd, "lbzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lhau $rD, $addr", IIC_LdStLHAU, "lhau $rD, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lhzu $rD, $addr", IIC_LdStLoadUpd, "lhzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lwzu $rD, $addr", IIC_LdStLoadUpd, "lwzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
let Predicates = [HasFPU] in {
def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lfsu $rD, $addr", IIC_LdStLFDU, "lfsu $rD, $addr", IIC_LdStLFDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lfdu $rD, $addr", IIC_LdStLFDU, "lfdu $rD, $addr", IIC_LdStLFDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
}
// Indexed (r+r) Loads with Update (preinc). // Indexed (r+r) Loads with Update (preinc).
def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lbzux $rD, $addr", IIC_LdStLoadUpdX, "lbzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
Show All 11 Linesdef LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lwzux $rD, $addr", IIC_LdStLoadUpdX, "lwzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
let Predicates = [HasFPU] in {
def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lfsux $rD, $addr", IIC_LdStLFDUX, "lfsux $rD, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lfdux $rD, $addr", IIC_LdStLFDUX, "lfdux $rD, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
} }
} }
}
// Indexed (r+r) Loads. // Indexed (r+r) Loads.
// //
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src),
"lbzx $rD, $src", IIC_LdStLoad, "lbzx $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (zextloadi8 xaddr:$src))]>; [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src),
"lhax $rD, $src", IIC_LdStLHA, "lhax $rD, $src", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 xaddr:$src))]>, [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src),
"lhzx $rD, $src", IIC_LdStLoad, "lhzx $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (zextloadi16 xaddr:$src))]>; [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad, "lwzx $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (load xaddr:$src))]>; [(set i32:$rD, (load xaddr:$src))]>;
def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src),
"lhbrx $rD, $src", IIC_LdStLoad, "lhbrx $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src),
"lwbrx $rD, $src", IIC_LdStLoad, "lwbrx $rD, $src", IIC_LdStLoad,
[(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
let Predicates = [HasFPU] in {
def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src),
"lfsx $frD, $src", IIC_LdStLFD, "lfsx $frD, $src", IIC_LdStLFD,
[(set f32:$frD, (load xaddr:$src))]>; [(set f32:$frD, (load xaddr:$src))]>;
def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src),
"lfdx $frD, $src", IIC_LdStLFD, "lfdx $frD, $src", IIC_LdStLFD,
[(set f64:$frD, (load xaddr:$src))]>; [(set f64:$frD, (load xaddr:$src))]>;
def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src),
"lfiwax $frD, $src", IIC_LdStLFD, "lfiwax $frD, $src", IIC_LdStLFD,
[(set f64:$frD, (PPClfiwax xoaddr:$src))]>; [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src),
"lfiwzx $frD, $src", IIC_LdStLFD, "lfiwzx $frD, $src", IIC_LdStLFD,
[(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
} }
}
// Load Multiple // Load Multiple
def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
"lmw $rD, $src", IIC_LdStLMW, []>; "lmw $rD, $src", IIC_LdStLMW, []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PPC32 Store Instructions. // PPC32 Store Instructions.
// //
// Unindexed (r+i) Stores. // Unindexed (r+i) Stores.
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
"stb $rS, $src", IIC_LdStStore, "stb $rS, $src", IIC_LdStStore,
[(truncstorei8 i32:$rS, iaddr:$src)]>; [(truncstorei8 i32:$rS, iaddr:$src)]>;
def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
"sth $rS, $src", IIC_LdStStore, "sth $rS, $src", IIC_LdStStore,
[(truncstorei16 i32:$rS, iaddr:$src)]>; [(truncstorei16 i32:$rS, iaddr:$src)]>;
def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
"stw $rS, $src", IIC_LdStStore, "stw $rS, $src", IIC_LdStStore,
[(store i32:$rS, iaddr:$src)]>; [(store i32:$rS, iaddr:$src)]>;
let Predicates = [HasFPU] in {
def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
"stfs $rS, $dst", IIC_LdStSTFD, "stfs $rS, $dst", IIC_LdStSTFD,
[(store f32:$rS, iaddr:$dst)]>; [(store f32:$rS, iaddr:$dst)]>;
def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
"stfd $rS, $dst", IIC_LdStSTFD, "stfd $rS, $dst", IIC_LdStSTFD,
[(store f64:$rS, iaddr:$dst)]>; [(store f64:$rS, iaddr:$dst)]>;
} }
}
// Unindexed (r+i) Stores with Update (preinc). // Unindexed (r+i) Stores with Update (preinc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"stbu $rS, $dst", IIC_LdStStoreUpd, []>, "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"sthu $rS, $dst", IIC_LdStStoreUpd, []>, "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
"stwu $rS, $dst", IIC_LdStStoreUpd, []>, "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
let Predicates = [HasFPU] in {
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
"stfsu $rS, $dst", IIC_LdStSTFDU, []>, "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
"stfdu $rS, $dst", IIC_LdStSTFDU, []>, "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
} }
}
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STBU $rS, iaddroff:$ptroff, $ptrreg)>; (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STHU $rS, iaddroff:$ptroff, $ptrreg)>; (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
Show All 23 Linesdef STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
"sthbrx $rS, $dst", IIC_LdStStore, "sthbrx $rS, $dst", IIC_LdStStore,
[(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
"stwbrx $rS, $dst", IIC_LdStStore, "stwbrx $rS, $dst", IIC_LdStStore,
[(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in {
def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
"stfiwx $frS, $dst", IIC_LdStSTFD, "stfiwx $frS, $dst", IIC_LdStSTFD,
[(PPCstfiwx f64:$frS, xoaddr:$dst)]>; [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
"stfsx $frS, $dst", IIC_LdStSTFD, "stfsx $frS, $dst", IIC_LdStSTFD,
[(store f32:$frS, xaddr:$dst)]>; [(store f32:$frS, xaddr:$dst)]>;
def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
"stfdx $frS, $dst", IIC_LdStSTFD, "stfdx $frS, $dst", IIC_LdStSTFD,
[(store f64:$frS, xaddr:$dst)]>; [(store f64:$frS, xaddr:$dst)]>;
} }
}
// Indexed (r+r) Stores with Update (preinc). // Indexed (r+r) Stores with Update (preinc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$rS, memrr:$dst),
"stbux $rS, $dst", IIC_LdStStoreUpd, []>, "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$rS, memrr:$dst),
"sthux $rS, $dst", IIC_LdStStoreUpd, []>, "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$rS, memrr:$dst),
"stwux $rS, $dst", IIC_LdStStoreUpd, []>, "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in {
def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),
(ins f4rc:$rS, memrr:$dst), (ins f4rc:$rS, memrr:$dst),
"stfsux $rS, $dst", IIC_LdStSTFDU, []>, "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),
(ins f8rc:$rS, memrr:$dst), (ins f8rc:$rS, memrr:$dst),
"stfdux $rS, $dst", IIC_LdStSTFDU, []>, "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
}
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STBUX $rS, $ptrreg, $ptroff)>; (STBUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STHUX $rS, $ptrreg, $ptroff)>; (STHUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STWUX $rS, $ptrreg, $ptroff)>; (STWUX $rS, $ptrreg, $ptroff)>;
let Predicates = [HasFPU] in {
def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STFSUX $rS, $ptrreg, $ptroff)>; (STFSUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STFDUX $rS, $ptrreg, $ptroff)>; (STFDUX $rS, $ptrreg, $ptroff)>;
}
// Store Multiple // Store Multiple
def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
"stmw $rS, $dst", IIC_LdStLMW, []>; "stmw $rS, $dst", IIC_LdStLMW, []>;
def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
"sync $L", IIC_LdStSync, []>; "sync $L", IIC_LdStSync, []>;
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
} }
let isCompare = 1, hasSideEffects = 0 in { let isCompare = 1, hasSideEffects = 0 in {
def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
"cmpw $crD, $rA, $rB", IIC_IntCompare>; "cmpw $crD, $rA, $rB", IIC_IntCompare>;
def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
"cmplw $crD, $rA, $rB", IIC_IntCompare>; "cmplw $crD, $rA, $rB", IIC_IntCompare>;
} }
} }
let PPC970_Unit = 3 in { // FPU Operations. let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations.
//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
let isCompare = 1, hasSideEffects = 0 in { let isCompare = 1, hasSideEffects = 0 in {
def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>; "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>; "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lineslet Uses = [RM] in {
} }
} }
} }
/// Note that FMR is defined as pseudo-ops on the PPC970 because they are /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
/// often coalesced away and we don't want the dispatch group builder to think /// often coalesced away and we don't want the dispatch group builder to think
/// that they will fill slots (which could cause the load of a LSU reject to /// that they will fill slots (which could cause the load of a LSU reject to
/// sneak into a d-group with a store). /// sneak into a d-group with a store).
let hasSideEffects = 0 in let hasSideEffects = 0, Predicates = [HasFPU] in
defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
"fmr", "$frD, $frB", IIC_FPGeneral, "fmr", "$frD, $frB", IIC_FPGeneral,
[]>, // (set f32:$frD, f32:$frB) []>, // (set f32:$frD, f32:$frB)
PPC970_Unit_Pseudo; PPC970_Unit_Pseudo;
let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations.
// These are artificially split into two different forms, for 4/8 byte FP. // These are artificially split into two different forms, for 4/8 byte FP.
defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
"fabs", "$frD, $frB", IIC_FPGeneral, "fabs", "$frD, $frB", IIC_FPGeneral,
[(set f32:$frD, (fabs f32:$frB))]>; [(set f32:$frD, (fabs f32:$frB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
"fabs", "$frD, $frB", IIC_FPGeneral, "fabs", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (fabs f64:$frB))]>; [(set f64:$frD, (fabs f64:$frB))]>;
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Linesdef MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
"mfcr $rT", IIC_SprMFCR>, "mfcr $rT", IIC_SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraSrcRegAllocReq = 1 } // hasExtraSrcRegAllocReq = 1
def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
"mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
} // hasSideEffects = 0 } // hasSideEffects = 0
let Predicates = [HasFPU] in {
// Pseudo instruction to perform FADD in round-to-zero mode. // Pseudo instruction to perform FADD in round-to-zero mode.
let usesCustomInserter = 1, Uses = [RM] in { let usesCustomInserter = 1, Uses = [RM] in {
def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
[(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
} }
// The above pseudo gets expanded to make use of the following instructions // The above pseudo gets expanded to make use of the following instructions
// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
(ins u2imm:$RM), "mffscrni $rT, $RM", (ins u2imm:$RM), "mffscrni $rT, $RM",
IIC_IntMFFS, []>, IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
"mffsl $rT", IIC_IntMFFS, []>, "mffsl $rT", IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
} }
}
let Predicates = [IsISA3_0] in { let Predicates = [IsISA3_0] in {
def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
"modsw $rT, $rA, $rB", IIC_IntDivW, "modsw $rT, $rA, $rB", IIC_IntDivW,
[(set i32:$rT, (srem i32:$rA, i32:$rB))]>; [(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
"moduw $rT, $rA, $rB", IIC_IntDivW, "moduw $rT, $rA, $rB", IIC_IntDivW,
[(set i32:$rT, (urem i32:$rA, i32:$rB))]>; [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Linesdefm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
"subfze", "$rT, $rA", IIC_IntGeneral, "subfze", "$rT, $rA", IIC_IntGeneral,
[(set i32:$rT, (sube 0, i32:$rA))]>; [(set i32:$rT, (sube 0, i32:$rA))]>;
} }
} }
// A-Form instructions. Most of the instructions executed in the FPU are of // A-Form instructions. Most of the instructions executed in the FPU are of
// this type. // this type.
// //
let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations.
let Uses = [RM] in { let Uses = [RM] in {
let isCommutable = 1 in { let isCommutable = 1 in {
defm FMADD : AForm_1r<63, 29, defm FMADD : AForm_1r<63, 29,
(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
"fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
[(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
defm FMADDS : AForm_1r<59, 29, defm FMADDS : AForm_1r<59, 29,
(outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
def : Pat<(extloadi8 iaddr:$src), def : Pat<(extloadi8 iaddr:$src),
(LBZ iaddr:$src)>; (LBZ iaddr:$src)>;
def : Pat<(extloadi8 xaddr:$src), def : Pat<(extloadi8 xaddr:$src),
(LBZX xaddr:$src)>; (LBZX xaddr:$src)>;
def : Pat<(extloadi16 iaddr:$src), def : Pat<(extloadi16 iaddr:$src),
(LHZ iaddr:$src)>; (LHZ iaddr:$src)>;
def : Pat<(extloadi16 xaddr:$src), def : Pat<(extloadi16 xaddr:$src),
(LHZX xaddr:$src)>; (LHZX xaddr:$src)>;
let Predicates = [HasFPU] in {
def : Pat<(f64 (extloadf32 iaddr:$src)), def : Pat<(f64 (extloadf32 iaddr:$src)),
(COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
def : Pat<(f64 (extloadf32 xaddr:$src)), def : Pat<(f64 (extloadf32 xaddr:$src)),
(COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
def : Pat<(f64 (fpextend f32:$src)), def : Pat<(f64 (fpextend f32:$src)),
(COPY_TO_REGCLASS $src, F8RC)>; (COPY_TO_REGCLASS $src, F8RC)>;
}
// Only seq_cst fences require the heavyweight sync (SYNC 0). // Only seq_cst fences require the heavyweight sync (SYNC 0).
// All others can use the lightweight sync (SYNC 1). // All others can use the lightweight sync (SYNC 1).
// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
// versions of Power. // versions of Power.
def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>; def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
let Predicates = [HasFPU] in {
// Additional FNMSUB patterns: -a*c + b == -(a*c - b) // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
(FNMSUB $A, $C, $B)>; (FNMSUB $A, $C, $B)>;
def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
(FNMSUB $A, $C, $B)>; (FNMSUB $A, $C, $B)>;
def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
(FNMSUBS $A, $C, $B)>; (FNMSUBS $A, $C, $B)>;
def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
(FNMSUBS $A, $C, $B)>; (FNMSUBS $A, $C, $B)>;
// FCOPYSIGN's operand types need not agree. // FCOPYSIGN's operand types need not agree.
def : Pat<(fcopysign f64:$frB, f32:$frA), def : Pat<(fcopysign f64:$frB, f32:$frA),
(FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
def : Pat<(fcopysign f32:$frB, f64:$frA), def : Pat<(fcopysign f32:$frB, f64:$frA),
(FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
}
include "PPCInstrAltivec.td" include "PPCInstrAltivec.td"
include "PPCInstrSPE.td" include "PPCInstrSPE.td"
include "PPCInstr64Bit.td" include "PPCInstr64Bit.td"
include "PPCInstrVSX.td" include "PPCInstrVSX.td"
include "PPCInstrQPX.td" include "PPCInstrQPX.td"
include "PPCInstrHTM.td" include "PPCInstrHTM.td"
▲ Show 20 Lines • Show All 426 Lines • ▼ Show 20 Lines
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
(EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
(EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
// SETCC for f32. // SETCC for f32.
let Predicates = [HasFPU] in {
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
(EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesdefm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)),
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)), defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)),
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)), defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)),
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)), defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)),
(EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
}
// This must be in this file because it relies on patterns defined in this file
// after the inclusion of the instruction sets.
let Predicates = [HasSPE] in {
// SETCC for f32.
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
(EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
(EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
(EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
(EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
(EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
(EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
(EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
(EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
(EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
(EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
(EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
(EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
// SETCC for f64.
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
(EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
(EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
(EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
(EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
(EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
(EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
(EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
(EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
(EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
(EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
(EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
(EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
}
// match select on i1 variables: // match select on i1 variables:
def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
(CROR (CRAND $cond , $tval), (CROR (CRAND $cond , $tval),
(CRAND (crnot $cond), $fval))>; (CRAND (crnot $cond), $fval))>;
// match selectcc on i1 variables: // match selectcc on i1 variables:
// select (lhs == rhs), tval, fval is: // select (lhs == rhs), tval, fval is:
// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesdef : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
(SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
(SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
(SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
(SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
let Predicates = [HasFPU] in {
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
(SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
(SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
(SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
(SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
Show All 25 Lines
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
(SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
(SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
(SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
(SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
}
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)),
(SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)),
(SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)),
(SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)),
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Linesdef MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
"mtfsfi $BF, $U, $W", IIC_IntMFFS>; "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
"mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT; "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>; def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
let Predicates = [HasFPU] in {
def MTFSF : XFLForm_1<63, 711, (outs), def MTFSF : XFLForm_1<63, 711, (outs),
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
"mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
def MTFSFo : XFLForm_1<63, 711, (outs), def MTFSFo : XFLForm_1<63, 711, (outs),
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
"mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT; "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>; def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
}
def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
"slbie $RB", IIC_SprSLBIE, []>; "slbie $RB", IIC_SprSLBIE, []>;
def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
"slbmte $RS, $RB", IIC_SprSLBMTE, []>; "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
▲ Show 20 Lines • Show All 892 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstrSPE.td

//=======-- PPCInstrSPE.td - The PowerPC SPE Extension -*- tablegen -*-=======// //=======-- PPCInstrSPE.td - The PowerPC SPE Extension -*- tablegen -*-=======//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file describes the Signal Processing Engine extension to // This file describes the Signal Processing Engine extension to
// the PowerPC instruction set. // the PowerPC instruction set.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class EFXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, class EFXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> { InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
let Pattern = []; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
class EFXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, class EFXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : EFXForm_1<xo, OOL, IOL, asmstr, itin> { InstrItinClass itin, list<dag> pattern> :
EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
let RB = 0; let RB = 0;
} }
class EFXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr, class EFXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : EFXForm_1<xo, OOL, IOL, asmstr, itin> { InstrItinClass itin, list<dag> pattern> :
EFXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
let RA = 0; let RA = 0;
} }
class EFXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, class EFXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> { InstrItinClass itin> :
I<4, OOL, IOL, asmstr, itin> {
bits<3> crD; bits<3> crD;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
let Pattern = [];
let Inst{6-8} = crD; let Inst{6-8} = crD;
let Inst{9-10} = 0; let Inst{9-10} = 0;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> { InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
class EVXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : InstrItinClass itin, list<dag> pattern> :
EVXForm_1<xo, OOL, IOL, asmstr, itin> { EVXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
let RB = 0; let RB = 0;
} }
class EVXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_2a<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : InstrItinClass itin, list<dag> pattern> :
EVXForm_1<xo, OOL, IOL, asmstr, itin> { EVXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
let RA = 0; let RA = 0;
} }
class EVXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> { I<4, OOL, IOL, asmstr, itin> {
bits<3> crD; bits<3> crD;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
let Pattern = pattern;
let Inst{6-8} = crD; let Inst{6-8} = crD;
let Inst{9-10} = 0; let Inst{9-10} = 0;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr, class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> { I<4, OOL, IOL, asmstr, itin> {
bits<3> crD; bits<3> crD;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
bits<5> RT; bits<5> RT;
let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-28} = xo; let Inst{21-28} = xo;
let Inst{29-31} = crD; let Inst{29-31} = crD;
} }
class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> { InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<21> D; bits<21> D;
let Pattern = []; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{20} = D{0}; let Inst{20} = D{0};
let Inst{19} = D{1}; let Inst{19} = D{1};
let Inst{18} = D{2}; let Inst{18} = D{2};
let Inst{17} = D{3}; let Inst{17} = D{3};
let Inst{16} = D{4}; let Inst{16} = D{4};
let Inst{15} = D{5}; let Inst{15} = D{5};
let Inst{14} = D{6}; let Inst{14} = D{6};
let Inst{13} = D{7}; let Inst{13} = D{7};
let Inst{12} = D{8}; let Inst{12} = D{8};
let Inst{11} = D{9}; let Inst{11} = D{9};
let Inst{11-20} = D{0-9}; let Inst{11-20} = D{0-9};
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
let DecoderNamespace = "SPE", Predicates = [HasSPE] in { let DecoderNamespace = "SPE", Predicates = [HasSPE] in {
def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"brinc $RT, $RA, $RB", IIC_IntSimple>; "brinc $RT, $RA, $RB", IIC_IntSimple, []>;
// Double-precision floating point // Double-precision floating point
def EFDABS : EFXForm_2<740, (outs gprc:$RT), (ins gprc:$RA), def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
"efdabs $RT, $RA", IIC_FPDGeneral>; "efdabs $RT, $RA", IIC_FPDGeneral,
[(set f64:$RT, (fabs f64:$RA))]>;
def EFDADD : EFXForm_1<736, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"efdadd $RT, $RA, $RB", IIC_FPAddSub>; def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efdadd $RT, $RA, $RB", IIC_FPAddSub,
def EFDCFS : EFXForm_2a<751, (outs gprc:$RT), (ins gprc:$RB), [(set f64:$RT, (fadd f64:$RA, f64:$RB))]>;
"efdcfs $RT, $RB", IIC_FPDGeneral>;
def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
def EFDCFSF : EFXForm_2a<755, (outs gprc:$RT), (ins gprc:$RB), "efdcfs $RT, $RB", IIC_FPDGeneral,
"efdcfsf $RT, $RB", IIC_FPDGeneral>; [(set f64:$RT, (fpextend f32:$RB))]>;
def EFDCFSI : EFXForm_2a<753, (outs gprc:$RT), (ins gprc:$RB), def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
"efdcfsi $RT, $RB", IIC_FPDGeneral>; "efdcfsf $RT, $RB", IIC_FPDGeneral, []>;
def EFDCFSID : EFXForm_2a<739, (outs gprc:$RT), (ins gprc:$RB), def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
"efdcfsid $RT, $RB", IIC_FPDGeneral>; "efdcfsi $RT, $RB", IIC_FPDGeneral,
[(set f64:$RT, (sint_to_fp i32:$RB))]>;
def EFDCFUF : EFXForm_2a<754, (outs gprc:$RT), (ins gprc:$RB),
"efdcfuf $RT, $RB", IIC_FPDGeneral>; def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
"efdcfsid $RT, $RB", IIC_FPDGeneral,
def EFDCFUI : EFXForm_2a<752, (outs gprc:$RT), (ins gprc:$RB), []>;
"efdcfui $RT, $RB", IIC_FPDGeneral>;
def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
def EFDCFUID : EFXForm_2a<738, (outs gprc:$RT), (ins gprc:$RB), "efdcfuf $RT, $RB", IIC_FPDGeneral, []>;
"efdcfuid $RT, $RB", IIC_FPDGeneral>;
def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
"efdcfui $RT, $RB", IIC_FPDGeneral,
[(set f64:$RT, (uint_to_fp i32:$RB))]>;
def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
"efdcfuid $RT, $RB", IIC_FPDGeneral,
[]>;
let isCompare = 1 in { let isCompare = 1 in {
def EFDCMPEQ : EFXForm_3<750, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDCMPEQ : EFXForm_3<750, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdcmpeq $crD, $RA, $RB", IIC_FPDGeneral>; "efdcmpeq $crD, $RA, $RB", IIC_FPDGeneral>;
def EFDCMPGT : EFXForm_3<748, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDCMPGT : EFXForm_3<748, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdcmpgt $crD, $RA, $RB", IIC_FPDGeneral>; "efdcmpgt $crD, $RA, $RB", IIC_FPDGeneral>;
def EFDCMPLT : EFXForm_3<749, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDCMPLT : EFXForm_3<749, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdcmplt $crD, $RA, $RB", IIC_FPDGeneral>; "efdcmplt $crD, $RA, $RB", IIC_FPDGeneral>;
} }
def EFDCTSF : EFXForm_2a<759, (outs gprc:$RT), (ins gprc:$RB), def EFDCTSF : EFXForm_2a<759, (outs sperc:$RT), (ins spe4rc:$RB),
"efdctsf $RT, $RB", IIC_FPDGeneral>; "efdctsf $RT, $RB", IIC_FPDGeneral, []>;
def EFDCTSI : EFXForm_2a<757, (outs gprc:$RT), (ins gprc:$RB),
"efdctsi $RT, $RB", IIC_FPDGeneral>;
def EFDCTSIDZ : EFXForm_2a<747, (outs gprc:$RT), (ins gprc:$RB),
"efdctsidz $RT, $RB", IIC_FPDGeneral>;
def EFDCTSIZ : EFXForm_2a<762, (outs gprc:$RT), (ins gprc:$RB),
"efdctsiz $RT, $RB", IIC_FPDGeneral>;
def EFDCTUF : EFXForm_2a<758, (outs gprc:$RT), (ins gprc:$RB),
"efdctuf $RT, $RB", IIC_FPDGeneral>;
def EFDCTUI : EFXForm_2a<756, (outs gprc:$RT), (ins gprc:$RB),
"efdctui $RT, $RB", IIC_FPDGeneral>;
def EFDCTUIDZ : EFXForm_2a<746, (outs gprc:$RT), (ins gprc:$RB), def EFDCTSI : EFXForm_2a<757, (outs gprc:$RT), (ins sperc:$RB),
"efdctuidz $RT, $RB", IIC_FPDGeneral>; "efdctsi $RT, $RB", IIC_FPDGeneral,
[]>;
def EFDCTUIZ : EFXForm_2a<760, (outs gprc:$RT), (ins gprc:$RB),
"efdctuiz $RT, $RB", IIC_FPDGeneral>; def EFDCTSIDZ : EFXForm_2a<747, (outs gprc:$RT), (ins sperc:$RB),
"efdctsidz $RT, $RB", IIC_FPDGeneral,
def EFDDIV : EFXForm_1<745, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"efddiv $RT, $RA, $RB", IIC_FPDivD>;
def EFDCTSIZ : EFXForm_2a<762, (outs gprc:$RT), (ins sperc:$RB),
def EFDMUL : EFXForm_1<744, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "efdctsiz $RT, $RB", IIC_FPDGeneral,
"efdmul $RT, $RA, $RB", IIC_FPDGeneral>; [(set i32:$RT, (fp_to_sint f64:$RB))]>;
def EFDNABS : EFXForm_2<741, (outs gprc:$RT), (ins gprc:$RA), def EFDCTUF : EFXForm_2a<758, (outs sperc:$RT), (ins spe4rc:$RB),
"efdnabs $RT, $RA", IIC_FPDGeneral>; "efdctuf $RT, $RB", IIC_FPDGeneral, []>;
def EFDNEG : EFXForm_2<742, (outs gprc:$RT), (ins gprc:$RA), def EFDCTUI : EFXForm_2a<756, (outs gprc:$RT), (ins sperc:$RB),
"efdneg $RT, $RA", IIC_FPDGeneral>; "efdctui $RT, $RB", IIC_FPDGeneral,
[]>;
def EFDSUB : EFXForm_1<737, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"efdsub $RT, $RA, $RB", IIC_FPDGeneral>; def EFDCTUIDZ : EFXForm_2a<746, (outs gprc:$RT), (ins sperc:$RB),
"efdctuidz $RT, $RB", IIC_FPDGeneral,
[]>;
def EFDCTUIZ : EFXForm_2a<760, (outs gprc:$RT), (ins sperc:$RB),
"efdctuiz $RT, $RB", IIC_FPDGeneral,
[(set i32:$RT, (fp_to_uint f64:$RB))]>;
def EFDDIV : EFXForm_1<745, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efddiv $RT, $RA, $RB", IIC_FPDivD,
[(set f64:$RT, (fdiv f64:$RA, f64:$RB))]>;
def EFDMUL : EFXForm_1<744, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efdmul $RT, $RA, $RB", IIC_FPDGeneral,
[(set f64:$RT, (fmul f64:$RA, f64:$RB))]>;
def EFDNABS : EFXForm_2<741, (outs sperc:$RT), (ins sperc:$RA),
"efdnabs $RT, $RA", IIC_FPDGeneral,
[(set f64:$RT, (fneg (fabs f64:$RA)))]>;
def EFDNEG : EFXForm_2<742, (outs sperc:$RT), (ins sperc:$RA),
"efdneg $RT, $RA", IIC_FPDGeneral,
[(set f64:$RT, (fneg f64:$RA))]>;
def EFDSUB : EFXForm_1<737, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efdsub $RT, $RA, $RB", IIC_FPDGeneral,
[(set f64:$RT, (fsub f64:$RA, f64:$RB))]>;
let isCompare = 1 in { let isCompare = 1 in {
def EFDTSTEQ : EFXForm_3<766, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDTSTEQ : EFXForm_3<766, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdtsteq $crD, $RA, $RB", IIC_FPDGeneral>; "efdtsteq $crD, $RA, $RB", IIC_FPDGeneral>;
def EFDTSTGT : EFXForm_3<764, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDTSTGT : EFXForm_3<764, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdtstgt $crD, $RA, $RB", IIC_FPDGeneral>; "efdtstgt $crD, $RA, $RB", IIC_FPDGeneral>;
def EFDTSTLT : EFXForm_3<765, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFDTSTLT : EFXForm_3<765, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdtstlt $crD, $RA, $RB", IIC_FPDGeneral>; "efdtstlt $crD, $RA, $RB", IIC_FPDGeneral>;
} }
// Single-precision floating point // Single-precision floating point
def EFSABS : EFXForm_2<708, (outs gprc:$RT), (ins gprc:$RA), def EFSABS : EFXForm_2<708, (outs spe4rc:$RT), (ins spe4rc:$RA),
"efsabs $RT, $RA", IIC_FPSGeneral>; "efsabs $RT, $RA", IIC_FPSGeneral,
[(set f32:$RT, (fabs f32:$RA))]>;
def EFSADD : EFXForm_1<704, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"efsadd $RT, $RA, $RB", IIC_FPAddSub>; def EFSADD : EFXForm_1<704, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
"efsadd $RT, $RA, $RB", IIC_FPAddSub,
def EFSCFD : EFXForm_2a<719, (outs gprc:$RT), (ins gprc:$RB), [(set f32:$RT, (fadd f32:$RA, f32:$RB))]>;
"efscfd $RT, $RB", IIC_FPSGeneral>;
def EFSCFD : EFXForm_2a<719, (outs spe4rc:$RT), (ins sperc:$RB),
def EFSCFSF : EFXForm_2a<723, (outs gprc:$RT), (ins gprc:$RB), "efscfd $RT, $RB", IIC_FPSGeneral,
"efscfsf $RT, $RB", IIC_FPSGeneral>; [(set f32:$RT, (fpround f64:$RB))]>;
def EFSCFSI : EFXForm_2a<721, (outs gprc:$RT), (ins gprc:$RB), def EFSCFSF : EFXForm_2a<723, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efscfsi $RT, $RB", IIC_FPSGeneral>; "efscfsf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCFUF : EFXForm_2a<722, (outs gprc:$RT), (ins gprc:$RB), def EFSCFSI : EFXForm_2a<721, (outs spe4rc:$RT), (ins gprc:$RB),
"efscfuf $RT, $RB", IIC_FPSGeneral>; "efscfsi $RT, $RB", IIC_FPSGeneral,
[(set f32:$RT, (sint_to_fp i32:$RB))]>;
def EFSCFUI : EFXForm_2a<720, (outs gprc:$RT), (ins gprc:$RB),
"efscfui $RT, $RB", IIC_FPSGeneral>; def EFSCFUF : EFXForm_2a<722, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efscfuf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCFUI : EFXForm_2a<720, (outs spe4rc:$RT), (ins gprc:$RB),
"efscfui $RT, $RB", IIC_FPSGeneral,
[(set f32:$RT, (uint_to_fp i32:$RB))]>;
let isCompare = 1 in { let isCompare = 1 in {
def EFSCMPEQ : EFXForm_3<718, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSCMPEQ : EFXForm_3<718, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmpeq $crD, $RA, $RB", IIC_FPCompare>; "efscmpeq $crD, $RA, $RB", IIC_FPCompare>;
def EFSCMPGT : EFXForm_3<716, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSCMPGT : EFXForm_3<716, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmpgt $crD, $RA, $RB", IIC_FPCompare>; "efscmpgt $crD, $RA, $RB", IIC_FPCompare>;
def EFSCMPLT : EFXForm_3<717, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSCMPLT : EFXForm_3<717, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmplt $crD, $RA, $RB", IIC_FPCompare>; "efscmplt $crD, $RA, $RB", IIC_FPCompare>;
} }
def EFSCTSF : EFXForm_2a<727, (outs gprc:$RT), (ins gprc:$RB), def EFSCTSF : EFXForm_2a<727, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efsctsf $RT, $RB", IIC_FPSGeneral>; "efsctsf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCTSI : EFXForm_2a<725, (outs gprc:$RT), (ins gprc:$RB),
"efsctsi $RT, $RB", IIC_FPSGeneral>;
def EFSCTSIZ : EFXForm_2a<730, (outs gprc:$RT), (ins gprc:$RB), def EFSCTSI : EFXForm_2a<725, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctsiz $RT, $RB", IIC_FPSGeneral>; "efsctsi $RT, $RB", IIC_FPSGeneral,
[]>;
def EFSCTUF : EFXForm_2a<726, (outs gprc:$RT), (ins gprc:$RB),
"efsctuf $RT, $RB", IIC_FPSGeneral>; def EFSCTSIZ : EFXForm_2a<730, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctsiz $RT, $RB", IIC_FPSGeneral,
def EFSCTUI : EFXForm_2a<724, (outs gprc:$RT), (ins gprc:$RB), [(set i32:$RT, (fp_to_sint f32:$RB))]>;
"efsctui $RT, $RB", IIC_FPSGeneral>;
def EFSCTUF : EFXForm_2a<726, (outs sperc:$RT), (ins spe4rc:$RB),
def EFSCTUIZ : EFXForm_2a<728, (outs gprc:$RT), (ins gprc:$RB), "efsctuf $RT, $RB", IIC_FPSGeneral, []>;
"efsctuiz $RT, $RB", IIC_FPSGeneral>;
def EFSCTUI : EFXForm_2a<724, (outs gprc:$RT), (ins spe4rc:$RB),
def EFSDIV : EFXForm_1<713, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "efsctui $RT, $RB", IIC_FPSGeneral,
"efsdiv $RT, $RA, $RB", IIC_FPDivD>; []>;
def EFSMUL : EFXForm_1<712, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EFSCTUIZ : EFXForm_2a<728, (outs gprc:$RT), (ins spe4rc:$RB),
"efsmul $RT, $RA, $RB", IIC_FPGeneral>; "efsctuiz $RT, $RB", IIC_FPSGeneral,
[(set i32:$RT, (fp_to_uint f32:$RB))]>;
def EFSNABS : EFXForm_2<709, (outs gprc:$RT), (ins gprc:$RA),
"efsnabs $RT, $RA", IIC_FPGeneral>; def EFSDIV : EFXForm_1<713, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
"efsdiv $RT, $RA, $RB", IIC_FPDivD,
def EFSNEG : EFXForm_2<710, (outs gprc:$RT), (ins gprc:$RA), [(set f32:$RT, (fdiv f32:$RA, f32:$RB))]>;
"efsneg $RT, $RA", IIC_FPGeneral>;
def EFSMUL : EFXForm_1<712, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
def EFSSUB : EFXForm_1<705, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "efsmul $RT, $RA, $RB", IIC_FPGeneral,
"efssub $RT, $RA, $RB", IIC_FPSGeneral>; [(set f32:$RT, (fmul f32:$RA, f32:$RB))]>;
def EFSNABS : EFXForm_2<709, (outs spe4rc:$RT), (ins spe4rc:$RA),
"efsnabs $RT, $RA", IIC_FPGeneral,
[(set f32:$RT, (fneg (fabs f32:$RA)))]>;
def EFSNEG : EFXForm_2<710, (outs spe4rc:$RT), (ins spe4rc:$RA),
"efsneg $RT, $RA", IIC_FPGeneral,
[(set f32:$RT, (fneg f32:$RA))]>;
def EFSSUB : EFXForm_1<705, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
"efssub $RT, $RA, $RB", IIC_FPSGeneral,
[(set f32:$RT, (fsub f32:$RA, f32:$RB))]>;
let isCompare = 1 in { let isCompare = 1 in {
def EFSTSTEQ : EFXForm_3<734, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSTSTEQ : EFXForm_3<734, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efststeq $crD, $RA, $RB", IIC_FPCompare>; "efststeq $crD, $RA, $RB", IIC_FPCompare>;
def EFSTSTGT : EFXForm_3<732, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSTSTGT : EFXForm_3<732, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efststgt $crD, $RA, $RB", IIC_FPCompare>; "efststgt $crD, $RA, $RB", IIC_FPCompare>;
def EFSTSTLT : EFXForm_3<733, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EFSTSTLT : EFXForm_3<733, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efststlt $crD, $RA, $RB", IIC_FPCompare>; "efststlt $crD, $RA, $RB", IIC_FPCompare>;
} }
// SPE Vector operations // SPE Vector operations
def EVABS : EVXForm_2<520, (outs gprc:$RT), (ins gprc:$RA), def EVABS : EVXForm_2<520, (outs sperc:$RT), (ins sperc:$RA),
"evabs $RT, $RA", IIC_VecGeneral>; "evabs $RT, $RA", IIC_VecGeneral,
[]>;
def EVADDIW : EVXForm_1<514, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB),
"evaddiw $RT, $RB, $RA", IIC_VecGeneral>; def EVADDIW : EVXForm_1<514, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
def EVADDSMIAAW : EVXForm_2<1225, (outs gprc:$RT), (ins gprc:$RA), "evaddiw $RT, $RB, $RA", IIC_VecGeneral, []>;
"evaddsmiaaw $RT, $RA", IIC_VecComplex>; def EVADDSMIAAW : EVXForm_2<1225, (outs sperc:$RT), (ins sperc:$RA),
def EVADDSSIAAW : EVXForm_2<1217, (outs gprc:$RT), (ins gprc:$RA), "evaddsmiaaw $RT, $RA", IIC_VecComplex, []>;
"evaddssiaaw $RT, $RA", IIC_VecComplex>; def EVADDSSIAAW : EVXForm_2<1217, (outs sperc:$RT), (ins sperc:$RA),
def EVADDUSIAAW : EVXForm_2<1216, (outs gprc:$RT), (ins gprc:$RA), "evaddssiaaw $RT, $RA", IIC_VecComplex, []>;
"evaddusiaaw $RT, $RA", IIC_VecComplex>; def EVADDUSIAAW : EVXForm_2<1216, (outs sperc:$RT), (ins sperc:$RA),
def EVADDUMIAAW : EVXForm_2<1224, (outs gprc:$RT), (ins gprc:$RA), "evaddusiaaw $RT, $RA", IIC_VecComplex, []>;
"evaddumiaaw $RT, $RA", IIC_VecComplex>; def EVADDUMIAAW : EVXForm_2<1224, (outs sperc:$RT), (ins sperc:$RA),
def EVADDW : EVXForm_1<512, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evaddumiaaw $RT, $RA", IIC_VecComplex, []>;
"evaddw $RT, $RA, $RB", IIC_VecGeneral>; def EVADDW : EVXForm_1<512, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evaddw $RT, $RA, $RB", IIC_VecGeneral,
def EVAND : EVXForm_1<529, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"evand $RT, $RA, $RB", IIC_VecGeneral>;
def EVANDC : EVXForm_1<530, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVAND : EVXForm_1<529, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evandc $RT, $RA, $RB", IIC_VecGeneral>; "evand $RT, $RA, $RB", IIC_VecGeneral,
[]>;
def EVANDC : EVXForm_1<530, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evandc $RT, $RA, $RB", IIC_VecGeneral,
[]>;
let isCompare = 1 in { let isCompare = 1 in {
def EVCMPEQ : EVXForm_3<564, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVCMPEQ : EVXForm_3<564, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evcmpeq $crD, $RA, $RB", IIC_VecGeneral>; "evcmpeq $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVCMPGTS : EVXForm_3<561, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVCMPGTS : EVXForm_3<561, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evcmpgts $crD, $RA, $RB", IIC_VecGeneral>; "evcmpgts $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVCMPGTU : EVXForm_3<560, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVCMPGTU : EVXForm_3<560, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evcmpgtu $crD, $RA, $RB", IIC_VecGeneral>; "evcmpgtu $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVCMPLTS : EVXForm_3<563, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVCMPLTS : EVXForm_3<563, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evcmplts $crD, $RA, $RB", IIC_VecGeneral>; "evcmplts $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVCMPLTU : EVXForm_3<562, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVCMPLTU : EVXForm_3<562, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evcmpltu $crD, $RA, $RB", IIC_VecGeneral>; "evcmpltu $crD, $RA, $RB", IIC_VecGeneral, []>;
} }
def EVCNTLSW : EVXForm_2<526, (outs gprc:$RT), (ins gprc:$RA), def EVCNTLSW : EVXForm_2<526, (outs sperc:$RT), (ins sperc:$RA),
"evcntlsw $RT, $RA", IIC_VecGeneral>; "evcntlsw $RT, $RA", IIC_VecGeneral, []>;
def EVCNTLZW : EVXForm_2<525, (outs gprc:$RT), (ins gprc:$RA), def EVCNTLZW : EVXForm_2<525, (outs sperc:$RT), (ins sperc:$RA),
"evcntlzw $RT, $RA", IIC_VecGeneral>; "evcntlzw $RT, $RA", IIC_VecGeneral,
[]>;
def EVDIVWS : EVXForm_1<1222, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"evdivws $RT, $RA, $RB", IIC_VecComplex>; def EVDIVWS : EVXForm_1<1222, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVDIVWU : EVXForm_1<1223, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evdivws $RT, $RA, $RB", IIC_VecComplex,
"evdivwu $RT, $RA, $RB", IIC_VecComplex>; []>;
def EVDIVWU : EVXForm_1<1223, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVEQV : EVXForm_1<537, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evdivwu $RT, $RA, $RB", IIC_VecComplex,
"eveqv $RT, $RA, $RB", IIC_VecGeneral>; []>;
def EVEXTSB : EVXForm_2<522, (outs gprc:$RT), (ins gprc:$RA), def EVEQV : EVXForm_1<537, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evextsb $RT, $RA", IIC_VecGeneral>; "eveqv $RT, $RA, $RB", IIC_VecGeneral,
def EVEXTSH : EVXForm_2<523, (outs gprc:$RT), (ins gprc:$RA), []>;
"evextsh $RT, $RA", IIC_VecGeneral>;
def EVEXTSB : EVXForm_2<522, (outs sperc:$RT), (ins sperc:$RA),
def EVFSABS : EVXForm_2<644, (outs gprc:$RT), (ins gprc:$RA), "evextsb $RT, $RA", IIC_VecGeneral,
"evfsabs $RT, $RA", IIC_VecGeneral>; []>;
def EVFSADD : EVXForm_1<640, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVEXTSH : EVXForm_2<523, (outs sperc:$RT), (ins sperc:$RA),
"evfsadd $RT, $RA, $RB", IIC_VecComplex>; "evextsh $RT, $RA", IIC_VecGeneral,
def EVFSCFSF : EVXForm_2a<659, (outs gprc:$RT), (ins gprc:$RB), []>;
"evfscfsf $RT, $RB", IIC_VecComplex>;
def EVFSCFSI : EVXForm_2a<657, (outs gprc:$RT), (ins gprc:$RB), def EVFSABS : EVXForm_2<644, (outs sperc:$RT), (ins sperc:$RA),
"evfscfsi $RT, $RB", IIC_VecComplex>; "evfsabs $RT, $RA", IIC_VecGeneral,
def EVFSCFUF : EVXForm_2a<658, (outs gprc:$RT), (ins gprc:$RB), []>;
"evfscfuf $RT, $RB", IIC_VecComplex>; def EVFSADD : EVXForm_1<640, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVFSCFUI : EVXForm_2a<650, (outs gprc:$RT), (ins gprc:$RB), "evfsadd $RT, $RA, $RB", IIC_VecComplex,
"evfscfui $RT, $RB", IIC_VecComplex>; []>;
def EVFSCFSF : EVXForm_2a<659, (outs sperc:$RT), (ins sperc:$RB),
"evfscfsf $RT, $RB", IIC_VecComplex, []>;
def EVFSCFSI : EVXForm_2a<657, (outs sperc:$RT), (ins sperc:$RB),
"evfscfsi $RT, $RB", IIC_VecComplex,
[]>;
def EVFSCFUF : EVXForm_2a<658, (outs sperc:$RT), (ins sperc:$RB),
"evfscfuf $RT, $RB", IIC_VecComplex, []>;
def EVFSCFUI : EVXForm_2a<650, (outs sperc:$RT), (ins sperc:$RB),
"evfscfui $RT, $RB", IIC_VecComplex,
[]>;
let isCompare = 1 in { let isCompare = 1 in {
def EVFSCMPEQ : EVXForm_3<654, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSCMPEQ : EVXForm_3<654, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfscmpeq $crD, $RA, $RB", IIC_FPSGeneral>; "evfscmpeq $crD, $RA, $RB", IIC_FPSGeneral, []>;
def EVFSCMPGT : EVXForm_3<652, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSCMPGT : EVXForm_3<652, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfscmpgt $crD, $RA, $RB", IIC_FPSGeneral>; "evfscmpgt $crD, $RA, $RB", IIC_FPSGeneral, []>;
def EVFSCMPLT : EVXForm_3<653, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSCMPLT : EVXForm_3<653, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfscmplt $crD, $RA, $RB", IIC_FPSGeneral>; "evfscmplt $crD, $RA, $RB", IIC_FPSGeneral, []>;
} }
def EVFSCTSF : EVXForm_2a<663, (outs gprc:$RT), (ins gprc:$RB), def EVFSCTSF : EVXForm_2a<663, (outs sperc:$RT), (ins sperc:$RB),
"evfsctsf $RT, $RB", IIC_VecComplex>; "evfsctsf $RT, $RB", IIC_VecComplex, []>;
def EVFSCTSI : EVXForm_2a<661, (outs gprc:$RT), (ins gprc:$RB), def EVFSCTSI : EVXForm_2a<661, (outs sperc:$RT), (ins sperc:$RB),
"evfsctsi $RT, $RB", IIC_VecComplex>; "evfsctsi $RT, $RB", IIC_VecComplex,
def EVFSCTSIZ : EVXForm_2a<666, (outs gprc:$RT), (ins gprc:$RB), []>;
"evfsctsiz $RT, $RB", IIC_VecComplex>; def EVFSCTSIZ : EVXForm_2a<666, (outs sperc:$RT), (ins sperc:$RB),
def EVFSCTUF : EVXForm_2a<662, (outs gprc:$RT), (ins gprc:$RB), "evfsctsiz $RT, $RB", IIC_VecComplex,
"evfsctsf $RT, $RB", IIC_VecComplex>; []>;
def EVFSCTUI : EVXForm_2a<660, (outs gprc:$RT), (ins gprc:$RB), def EVFSCTUF : EVXForm_2a<662, (outs sperc:$RT), (ins sperc:$RB),
"evfsctui $RT, $RB", IIC_VecComplex>; "evfsctsf $RT, $RB", IIC_VecComplex, []>;
def EVFSCTUIZ : EVXForm_2a<664, (outs gprc:$RT), (ins gprc:$RB), def EVFSCTUI : EVXForm_2a<660, (outs sperc:$RT), (ins sperc:$RB),
"evfsctsiz $RT, $RB", IIC_VecComplex>; "evfsctui $RT, $RB", IIC_VecComplex,
def EVFSDIV : EVXForm_1<649, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"evfsdiv $RT, $RA, $RB", IIC_FPDivD>; def EVFSCTUIZ : EVXForm_2a<664, (outs sperc:$RT), (ins sperc:$RB),
def EVFSMUL : EVXForm_1<648, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evfsctsiz $RT, $RB", IIC_VecComplex,
"evfsmul $RT, $RA, $RB", IIC_VecComplex>; []>;
def EVFSNABS : EVXForm_2<645, (outs gprc:$RT), (ins gprc:$RA), def EVFSDIV : EVXForm_1<649, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evfsnabs $RT, $RA", IIC_VecGeneral>; "evfsdiv $RT, $RA, $RB", IIC_FPDivD,
def EVFSNEG : EVXForm_2<646, (outs gprc:$RT), (ins gprc:$RA), []>;
"evfsneg $RT, $RA", IIC_VecGeneral>; def EVFSMUL : EVXForm_1<648, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVFSSUB : EVXForm_1<641, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evfsmul $RT, $RA, $RB", IIC_VecComplex,
"evfssub $RT, $RA, $RB", IIC_VecComplex>; []>;
def EVFSNABS : EVXForm_2<645, (outs sperc:$RT), (ins sperc:$RA),
"evfsnabs $RT, $RA", IIC_VecGeneral,
[]>;
def EVFSNEG : EVXForm_2<646, (outs sperc:$RT), (ins sperc:$RA),
"evfsneg $RT, $RA", IIC_VecGeneral,
[]>;
def EVFSSUB : EVXForm_1<641, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evfssub $RT, $RA, $RB", IIC_VecComplex,
[]>;
let isCompare = 1 in { let isCompare = 1 in {
def EVFSTSTEQ : EVXForm_3<670, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSTSTEQ : EVXForm_3<670, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfststeq $crD, $RA, $RB", IIC_VecGeneral>; "evfststeq $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVFSTSTGT : EVXForm_3<668, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSTSTGT : EVXForm_3<668, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfststgt $crD, $RA, $RB", IIC_VecGeneral>; "evfststgt $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVFSTSTLT : EVXForm_3<669, (outs crrc:$crD), (ins gprc:$RA, gprc:$RB), def EVFSTSTLT : EVXForm_3<669, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfststlt $crD, $RA, $RB", IIC_VecGeneral>; "evfststlt $crD, $RA, $RB", IIC_VecGeneral, []>;
} }
def EVLDD : EVXForm_D<769, (outs gprc:$RT), (ins spe8dis:$dst), def EVLDD : EVXForm_D<769, (outs sperc:$RT), (ins spe8dis:$dst),
"evldd $RT, $dst", IIC_LdStLoad>; "evldd $RT, $dst", IIC_LdStLoad,
def EVLDDX : EVXForm_1<768, (outs gprc:$RT), (ins memrr:$src), [(set f64:$RT, (load iaddr:$dst))]>;
"evlddx $RT, $src", IIC_LdStLoad>; def EVLDDX : EVXForm_1<768, (outs sperc:$RT), (ins memrr:$src),
def EVLDH : EVXForm_D<773, (outs gprc:$RT), (ins spe8dis:$dst), "evlddx $RT, $src", IIC_LdStLoad,
"evldh $RT, $dst", IIC_LdStLoad>; [(set f64:$RT, (load xaddr:$src))]>;
def EVLDHX : EVXForm_1<772, (outs gprc:$RT), (ins memrr:$src), def EVLDH : EVXForm_D<773, (outs sperc:$RT), (ins spe8dis:$dst),
"evldhx $RT, $src", IIC_LdStLoad>; "evldh $RT, $dst", IIC_LdStLoad, []>;
def EVLDW : EVXForm_D<771, (outs gprc:$RT), (ins spe8dis:$dst), def EVLDHX : EVXForm_1<772, (outs sperc:$RT), (ins memrr:$src),
"evldw $RT, $dst", IIC_LdStLoad>; "evldhx $RT, $src", IIC_LdStLoad, []>;
def EVLDWX : EVXForm_1<770, (outs gprc:$RT), (ins memrr:$src), def EVLDW : EVXForm_D<771, (outs sperc:$RT), (ins spe8dis:$dst),
"evldwx $RT, $src", IIC_LdStLoad>; "evldw $RT, $dst", IIC_LdStLoad,
def EVLHHESPLAT : EVXForm_D<777, (outs gprc:$RT), (ins spe2dis:$dst), []>;
"evlhhesplat $RT, $dst", IIC_LdStLoad>; def EVLDWX : EVXForm_1<770, (outs sperc:$RT), (ins memrr:$src),
def EVLHHESPLATX : EVXForm_1<776, (outs gprc:$RT), (ins memrr:$src), "evldwx $RT, $src", IIC_LdStLoad,
"evlhhesplatx $RT, $src", IIC_LdStLoad>; []>;
def EVLHHOUSPLAT : EVXForm_D<781, (outs gprc:$RT), (ins spe2dis:$dst), def EVLHHESPLAT : EVXForm_D<777, (outs sperc:$RT), (ins spe2dis:$dst),
"evlhhousplat $RT, $dst", IIC_LdStLoad>; "evlhhesplat $RT, $dst", IIC_LdStLoad, []>;
def EVLHHOUSPLATX : EVXForm_1<780, (outs gprc:$RT), (ins memrr:$src), def EVLHHESPLATX : EVXForm_1<776, (outs sperc:$RT), (ins memrr:$src),
"evlhhousplatx $RT, $src", IIC_LdStLoad>; "evlhhesplatx $RT, $src", IIC_LdStLoad, []>;
def EVLHHOSSPLAT : EVXForm_D<783, (outs gprc:$RT), (ins spe2dis:$dst), def EVLHHOUSPLAT : EVXForm_D<781, (outs sperc:$RT), (ins spe2dis:$dst),
"evlhhossplat $RT, $dst", IIC_LdStLoad>; "evlhhousplat $RT, $dst", IIC_LdStLoad, []>;
def EVLHHOSSPLATX : EVXForm_1<782, (outs gprc:$RT), (ins memrr:$src), def EVLHHOUSPLATX : EVXForm_1<780, (outs sperc:$RT), (ins memrr:$src),
"evlhhossplatx $RT, $src", IIC_LdStLoad>; "evlhhousplatx $RT, $src", IIC_LdStLoad, []>;
def EVLWHE : EVXForm_D<785, (outs gprc:$RT), (ins spe4dis:$dst), def EVLHHOSSPLAT : EVXForm_D<783, (outs sperc:$RT), (ins spe2dis:$dst),
"evlwhe $RT, $dst", IIC_LdStLoad>; "evlhhossplat $RT, $dst", IIC_LdStLoad, []>;
def EVLWHEX : EVXForm_1<784, (outs gprc:$RT), (ins memrr:$src), def EVLHHOSSPLATX : EVXForm_1<782, (outs sperc:$RT), (ins memrr:$src),
"evlwhex $RT, $src", IIC_LdStLoad>; "evlhhossplatx $RT, $src", IIC_LdStLoad, []>;
def EVLWHOS : EVXForm_D<791, (outs gprc:$RT), (ins spe4dis:$dst), def EVLWHE : EVXForm_D<785, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhos $RT, $dst", IIC_LdStLoad>; "evlwhe $RT, $dst", IIC_LdStLoad, []>;
def EVLWHOSX : EVXForm_1<790, (outs gprc:$RT), (ins memrr:$src), def EVLWHEX : EVXForm_1<784, (outs sperc:$RT), (ins memrr:$src),
"evlwhosx $RT, $src", IIC_LdStLoad>; "evlwhex $RT, $src", IIC_LdStLoad, []>;
def EVLWHOU : EVXForm_D<789, (outs gprc:$RT), (ins spe4dis:$dst), def EVLWHOS : EVXForm_D<791, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhou $RT, $dst", IIC_LdStLoad>; "evlwhos $RT, $dst", IIC_LdStLoad, []>;
def EVLWHOUX : EVXForm_1<788, (outs gprc:$RT), (ins memrr:$src), def EVLWHOSX : EVXForm_1<790, (outs sperc:$RT), (ins memrr:$src),
"evlwhoux $RT, $src", IIC_LdStLoad>; "evlwhosx $RT, $src", IIC_LdStLoad, []>;
def EVLWHSPLAT : EVXForm_D<797, (outs gprc:$RT), (ins spe4dis:$dst), def EVLWHOU : EVXForm_D<789, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhsplat $RT, $dst", IIC_LdStLoad>; "evlwhou $RT, $dst", IIC_LdStLoad, []>;
def EVLWHSPLATX : EVXForm_1<796, (outs gprc:$RT), (ins memrr:$src), def EVLWHOUX : EVXForm_1<788, (outs sperc:$RT), (ins memrr:$src),
"evlwhsplatx $RT, $src", IIC_LdStLoad>; "evlwhoux $RT, $src", IIC_LdStLoad, []>;
def EVLWWSPLAT : EVXForm_D<793, (outs gprc:$RT), (ins spe4dis:$dst), def EVLWHSPLAT : EVXForm_D<797, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwwsplat $RT, $dst", IIC_LdStLoad>; "evlwhsplat $RT, $dst", IIC_LdStLoad, []>;
def EVLWWSPLATX : EVXForm_1<792, (outs gprc:$RT), (ins memrr:$src), def EVLWHSPLATX : EVXForm_1<796, (outs sperc:$RT), (ins memrr:$src),
"evlwwsplatx $RT, $src", IIC_LdStLoad>; "evlwhsplatx $RT, $src", IIC_LdStLoad, []>;
def EVLWWSPLAT : EVXForm_D<793, (outs sperc:$RT), (ins spe4dis:$dst),
def EVMERGEHI : EVXForm_1<556, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evlwwsplat $RT, $dst", IIC_LdStLoad, []>;
"evmergehi $RT, $RA, $RB", IIC_VecGeneral>; def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins memrr:$src),
def EVMERGELO : EVXForm_1<557, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evlwwsplatx $RT, $src", IIC_LdStLoad, []>;
"evmergelo $RT, $RA, $RB", IIC_VecGeneral>;
def EVMERGEHILO : EVXForm_1<558, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmergehilo $RT, $RA, $RB", IIC_VecGeneral>; "evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVMERGELOHI : EVXForm_1<559, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmergelohi $RT, $RA, $RB", IIC_VecGeneral>; "evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMHEGSMFAA : EVXForm_1<1323, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>;
"evmhegsmfaa $RT, $RA, $RB", IIC_VecComplex>; def EVMERGELOHI : EVXForm_1<559, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMHEGSMFAN : EVXForm_1<1451, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmergelohi $RT, $RA, $RB", IIC_VecGeneral, []>;
"evmhegsmfan $RT, $RA, $RB", IIC_VecComplex>;
def EVMHEGSMIAA : EVXForm_1<1321, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEGSMFAA : EVXForm_1<1323, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhegsmiaa $RT, $RA, $RB", IIC_VecComplex>; "evmhegsmfaa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEGSMIAN : EVXForm_1<1449, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEGSMFAN : EVXForm_1<1451, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhegsmian $RT, $RA, $RB", IIC_VecComplex>; "evmhegsmfan $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEGUMIAA : EVXForm_1<1320, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEGSMIAA : EVXForm_1<1321, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhegumiaa $RT, $RA, $RB", IIC_VecComplex>; "evmhegsmiaa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEGUMIAN : EVXForm_1<1448, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEGSMIAN : EVXForm_1<1449, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhegumian $RT, $RA, $RB", IIC_VecComplex>; "evmhegsmian $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEGUMIAA : EVXForm_1<1320, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMHESMF : EVXForm_1<1035, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmhegumiaa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmhesmf $RT, $RA, $RB", IIC_VecComplex>; def EVMHEGUMIAN : EVXForm_1<1448, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMHESMFA : EVXForm_1<1067, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmhegumian $RT, $RA, $RB", IIC_VecComplex, []>;
"evmhesmfa $RT, $RA, $RB", IIC_VecComplex>;
def EVMHESMFAAW : EVXForm_1<1291, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMF : EVXForm_1<1035, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmfaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhesmf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESMFANW : EVXForm_1<1419, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMFA : EVXForm_1<1067, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmfanw $RT, $RA, $RB", IIC_VecComplex>; "evmhesmfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESMI : EVXForm_1<1033, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMFAAW : EVXForm_1<1291, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmi $RT, $RA, $RB", IIC_VecComplex>; "evmhesmfaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESMIA : EVXForm_1<1065, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMFANW : EVXForm_1<1419, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmia $RT, $RA, $RB", IIC_VecComplex>; "evmhesmfanw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESMIAAW : EVXForm_1<1289, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMI : EVXForm_1<1033, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhesmi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESMIANW : EVXForm_1<1417, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMIA : EVXForm_1<1065, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhesmianw $RT, $RA, $RB", IIC_VecComplex>; "evmhesmia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSF : EVXForm_1<1027, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMIAAW : EVXForm_1<1289, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessf $RT, $RA, $RB", IIC_VecComplex>; "evmhesmiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSFA : EVXForm_1<1059, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESMIANW : EVXForm_1<1417, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessfa $RT, $RA, $RB", IIC_VecComplex>; "evmhesmianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSFAAW : EVXForm_1<1283, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSF : EVXForm_1<1027, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessfaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhessf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSFANW : EVXForm_1<1411, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSFA : EVXForm_1<1059, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessfanw $RT, $RA, $RB", IIC_VecComplex>; "evmhessfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSIAAW : EVXForm_1<1281, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSFAAW : EVXForm_1<1283, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhessfaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHESSIANW : EVXForm_1<1409, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSFANW : EVXForm_1<1411, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhessianw $RT, $RA, $RB", IIC_VecComplex>; "evmhessfanw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUMI : EVXForm_1<1032, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSIAAW : EVXForm_1<1281, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheumi $RT, $RA, $RB", IIC_VecComplex>; "evmhessiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUMIA : EVXForm_1<1064, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHESSIANW : EVXForm_1<1409, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheumia $RT, $RA, $RB", IIC_VecComplex>; "evmhessianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUMIAAW : EVXForm_1<1288, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUMI : EVXForm_1<1032, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheumiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmheumi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUMIANW : EVXForm_1<1416, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUMIA : EVXForm_1<1064, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheumianw $RT, $RA, $RB", IIC_VecComplex>; "evmheumia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUSIAAW : EVXForm_1<1280, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUMIAAW : EVXForm_1<1288, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheusiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmheumiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHEUSIANW : EVXForm_1<1408, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUMIANW : EVXForm_1<1416, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmheusianw $RT, $RA, $RB", IIC_VecComplex>; "evmheumianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGSMFAA : EVXForm_1<1327, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUSIAAW : EVXForm_1<1280, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogsmfaa $RT, $RA, $RB", IIC_VecComplex>; "evmheusiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGSMFAN : EVXForm_1<1455, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHEUSIANW : EVXForm_1<1408, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogsmfan $RT, $RA, $RB", IIC_VecComplex>; "evmheusianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGSMIAA : EVXForm_1<1325, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGSMFAA : EVXForm_1<1327, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogsmiaa $RT, $RA, $RB", IIC_VecComplex>; "evmhogsmfaa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGSMIAN : EVXForm_1<1453, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGSMFAN : EVXForm_1<1455, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogsmian $RT, $RA, $RB", IIC_VecComplex>; "evmhogsmfan $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGUMIAA : EVXForm_1<1324, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGSMIAA : EVXForm_1<1325, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogumiaa $RT, $RA, $RB", IIC_VecComplex>; "evmhogsmiaa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOGUMIAN : EVXForm_1<1452, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGSMIAN : EVXForm_1<1453, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhogumian $RT, $RA, $RB", IIC_VecComplex>; "evmhogsmian $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMF : EVXForm_1<1039, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGUMIAA : EVXForm_1<1324, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmf $RT, $RA, $RB", IIC_VecComplex>; "evmhogumiaa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMFA : EVXForm_1<1071, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOGUMIAN : EVXForm_1<1452, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmfa $RT, $RA, $RB", IIC_VecComplex>; "evmhogumian $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMFAAW : EVXForm_1<1295, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMF : EVXForm_1<1039, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmfaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhosmf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMFANW : EVXForm_1<1423, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMFA : EVXForm_1<1071, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmfanw $RT, $RA, $RB", IIC_VecComplex>; "evmhosmfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMI : EVXForm_1<1037, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMFAAW : EVXForm_1<1295, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmi $RT, $RA, $RB", IIC_VecComplex>; "evmhosmfaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMIA : EVXForm_1<1069, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMFANW : EVXForm_1<1423, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmia $RT, $RA, $RB", IIC_VecComplex>; "evmhosmfanw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMIAAW : EVXForm_1<1293, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMI : EVXForm_1<1037, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhosmi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSMIANW : EVXForm_1<1421, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMIA : EVXForm_1<1069, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhosmianw $RT, $RA, $RB", IIC_VecComplex>; "evmhosmia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSF : EVXForm_1<1031, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMIAAW : EVXForm_1<1293, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossf $RT, $RA, $RB", IIC_VecComplex>; "evmhosmiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSFA : EVXForm_1<1063, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSMIANW : EVXForm_1<1421, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossfa $RT, $RA, $RB", IIC_VecComplex>; "evmhosmianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSFAAW : EVXForm_1<1287, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSF : EVXForm_1<1031, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossfaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhossf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSFANW : EVXForm_1<1415, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSFA : EVXForm_1<1063, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossfanw $RT, $RA, $RB", IIC_VecComplex>; "evmhossfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSIAAW : EVXForm_1<1285, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSFAAW : EVXForm_1<1287, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhossfaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOSSIANW : EVXForm_1<1413, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSFANW : EVXForm_1<1415, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhossianw $RT, $RA, $RB", IIC_VecComplex>; "evmhossfanw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUMI : EVXForm_1<1036, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSIAAW : EVXForm_1<1285, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhoumi $RT, $RA, $RB", IIC_VecComplex>; "evmhossiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUMIA : EVXForm_1<1068, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOSSIANW : EVXForm_1<1413, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhoumia $RT, $RA, $RB", IIC_VecComplex>; "evmhossianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUMIAAW : EVXForm_1<1292, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOUMI : EVXForm_1<1036, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhoumiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhoumi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUMIANW : EVXForm_1<1420, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOUMIA : EVXForm_1<1068, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhoumianw $RT, $RA, $RB", IIC_VecComplex>; "evmhoumia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUSIAAW : EVXForm_1<1284, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOUMIAAW : EVXForm_1<1292, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhousiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmhoumiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUSIANW : EVXForm_1<1412, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMHOUMIANW : EVXForm_1<1420, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhousianw $RT, $RA, $RB", IIC_VecComplex>; "evmhoumianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMHOUSIAAW : EVXForm_1<1284, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMRA : EVXForm_2<1220, (outs gprc:$RT), (ins gprc:$RA), "evmhousiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
"evmra $RT, $RA", IIC_VecComplex>; def EVMHOUSIANW : EVXForm_1<1412, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmhousianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHSMF : EVXForm_1<1103, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"evmwhsmf $RT, $RA, $RB", IIC_VecComplex>; def EVMRA : EVXForm_2<1220, (outs sperc:$RT), (ins sperc:$RA),
def EVMWHSMFA : EVXForm_1<1135, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmra $RT, $RA", IIC_VecComplex, []>;
"evmwhsmfa $RT, $RA, $RB", IIC_VecComplex>;
def EVMWHSMI : EVXForm_1<1101, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSMF : EVXForm_1<1103, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhsmi $RT, $RA, $RB", IIC_VecComplex>; "evmwhsmf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHSMIA : EVXForm_1<1133, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSMFA : EVXForm_1<1135, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhsmia $RT, $RA, $RB", IIC_VecComplex>; "evmwhsmfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHSSF : EVXForm_1<1095, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSMI : EVXForm_1<1101, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhssf $RT, $RA, $RB", IIC_VecComplex>; "evmwhsmi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHSSFA : EVXForm_1<1127, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSMIA : EVXForm_1<1133, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhssfa $RT, $RA, $RB", IIC_VecComplex>; "evmwhsmia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHUMI : EVXForm_1<1100, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSSF : EVXForm_1<1095, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhumi $RT, $RA, $RB", IIC_VecComplex>; "evmwhssf $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWHUMIA : EVXForm_1<1132, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHSSFA : EVXForm_1<1127, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwhumia $RT, $RA, $RB", IIC_VecComplex>; "evmwhssfa $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLSMIAAW : EVXForm_1<1353, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHUMI : EVXForm_1<1100, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlsmiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmwhumi $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLSMIANW : EVXForm_1<1481, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWHUMIA : EVXForm_1<1132, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlsmianw $RT, $RA, $RB", IIC_VecComplex>; "evmwhumia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLSSIAAW : EVXForm_1<1345, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWLSMIAAW : EVXForm_1<1353, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlssiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmwlsmiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLSSIANW : EVXForm_1<1473, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWLSMIANW : EVXForm_1<1481, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlssianw $RT, $RA, $RB", IIC_VecComplex>; "evmwlsmianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLUMI : EVXForm_1<1096, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWLSSIAAW : EVXForm_1<1345, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlumi $RT, $RA, $RB", IIC_VecComplex>; "evmwlssiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLUMIA : EVXForm_1<1128, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWLSSIANW : EVXForm_1<1473, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlumia $RT, $RA, $RB", IIC_VecComplex>; "evmwlssianw $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWLUMIAAW : EVXForm_1<1352, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def EVMWLUMI : EVXForm_1<1096, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwlumiaaw $RT, $RA, $RB", IIC_VecComplex>; "evmwlumi $RT, $RA, $RB", IIC_VecComplex,
def EVMWLUMIANW : EVXForm_1<1480, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"evmwlumianw $RT, $RA, $RB", IIC_VecComplex>; def EVMWLUMIA : EVXForm_1<1128, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWLUSIAAW : EVXForm_1<1344, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwlumia $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwlusiaaw $RT, $RA, $RB", IIC_VecComplex>; def EVMWLUMIAAW : EVXForm_1<1352, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWLUSIANW : EVXForm_1<1472, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwlumiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwlusianw $RT, $RA, $RB", IIC_VecComplex>; def EVMWLUMIANW : EVXForm_1<1480, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMF : EVXForm_1<1115, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwlumianw $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmf $RT, $RA, $RB", IIC_VecComplex>; def EVMWLUSIAAW : EVXForm_1<1344, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMFA : EVXForm_1<1147, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwlusiaaw $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmfa $RT, $RA, $RB", IIC_VecComplex>; def EVMWLUSIANW : EVXForm_1<1472, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMFAA : EVXForm_1<1371, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwlusianw $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmfaa $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMF : EVXForm_1<1115, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMFAN : EVXForm_1<1499, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmf $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmfan $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMFA : EVXForm_1<1147, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMI : EVXForm_1<1113, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmfa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmi $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMFAA : EVXForm_1<1371, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMIA : EVXForm_1<1145, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmfaa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmia $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMFAN : EVXForm_1<1499, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMIAA : EVXForm_1<1369, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmfan $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmiaa $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMI : EVXForm_1<1113, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSMIAN : EVXForm_1<1497, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmi $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwsmian $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMIA : EVXForm_1<1145, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSSF : EVXForm_1<1107, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmia $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwssf $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMIAA : EVXForm_1<1369, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSSFA : EVXForm_1<1139, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmiaa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwssfa $RT, $RA, $RB", IIC_VecComplex>; def EVMWSMIAN : EVXForm_1<1497, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSSFAA : EVXForm_1<1363, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwsmian $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwssfaa $RT, $RA, $RB", IIC_VecComplex>; def EVMWSSF : EVXForm_1<1107, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWSSFAN : EVXForm_1<1491, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwssf $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwssfan $RT, $RA, $RB", IIC_VecComplex>; def EVMWSSFA : EVXForm_1<1139, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWUMI : EVXForm_1<1112, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwssfa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwumi $RT, $RA, $RB", IIC_VecComplex>; def EVMWSSFAA : EVXForm_1<1363, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWUMIA : EVXForm_1<1144, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwssfaa $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwumia $RT, $RA, $RB", IIC_VecComplex>; def EVMWSSFAN : EVXForm_1<1491, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWUMIAA : EVXForm_1<1368, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwssfan $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwumiaa $RT, $RA, $RB", IIC_VecComplex>; def EVMWUMI : EVXForm_1<1112, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVMWUMIAN : EVXForm_1<1496, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwumi $RT, $RA, $RB", IIC_VecComplex, []>;
"evmwumian $RT, $RA, $RB", IIC_VecComplex>; def EVMWUMIA : EVXForm_1<1144, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwumia $RT, $RA, $RB", IIC_VecComplex, []>;
def EVMWUMIAA : EVXForm_1<1368, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVNAND : EVXForm_1<542, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evmwumiaa $RT, $RA, $RB", IIC_VecComplex, []>;
"evnand $RT, $RA, $RB", IIC_VecGeneral>; def EVMWUMIAN : EVXForm_1<1496, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmwumian $RT, $RA, $RB", IIC_VecComplex, []>;
def EVNEG : EVXForm_2<521, (outs gprc:$RT), (ins gprc:$RA),
"evneg $RT, $RA", IIC_VecGeneral>;
def EVNAND : EVXForm_1<542, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVNOR : EVXForm_1<536, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evnand $RT, $RA, $RB", IIC_VecGeneral,
"evnor $RT, $RA, $RB", IIC_VecGeneral>; []>;
def EVOR : EVXForm_1<535, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"evor $RT, $RA, $RB", IIC_VecGeneral>; def EVNEG : EVXForm_2<521, (outs sperc:$RT), (ins sperc:$RA),
def EVORC : EVXForm_1<539, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evneg $RT, $RA", IIC_VecGeneral,
"evorc $RT, $RA, $RB", IIC_VecGeneral>; []>;
def EVRLWI : EVXForm_1<554, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB), def EVNOR : EVXForm_1<536, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evrlwi $RT, $RA, $RB", IIC_VecGeneral>; "evnor $RT, $RA, $RB", IIC_VecGeneral,
def EVRLW : EVXForm_1<552, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"evrlw $RT, $RA, $RB", IIC_VecGeneral>; def EVOR : EVXForm_1<535, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evor $RT, $RA, $RB", IIC_VecGeneral,
def EVRNDW : EVXForm_2<524, (outs gprc:$RT), (ins gprc:$RA), []>;
"evrndw $RT, $RA", IIC_VecGeneral>; def EVORC : EVXForm_1<539, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evorc $RT, $RA, $RB", IIC_VecGeneral,
def EVSEL : EVXForm_4<79, (outs gprc:$RT), []>;
(ins gprc:$RA, gprc:$RB, crrc:$crD),
"evsel crD,$RT,$RA,$RB", IIC_VecGeneral>; def EVRLWI : EVXForm_1<554, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
"evrlwi $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVSLWI : EVXForm_1<550, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB), def EVRLW : EVXForm_1<552, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evslwi $RT, $RA, $RB", IIC_VecGeneral>; "evrlw $RT, $RA, $RB", IIC_VecGeneral,
def EVSLW : EVXForm_1<548, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), []>;
"evslw $RT, $RA, $RB", IIC_VecGeneral>;
def EVRNDW : EVXForm_2<524, (outs sperc:$RT), (ins sperc:$RA),
def EVSPLATFI : EVXForm_2<555, (outs gprc:$RT), (ins s5imm:$RA), "evrndw $RT, $RA", IIC_VecGeneral, []>;
"evsplatfi $RT, $RA", IIC_VecGeneral>;
def EVSPLATI : EVXForm_2<553, (outs gprc:$RT), (ins s5imm:$RA), def EVSEL : EVXForm_4<79, (outs sperc:$RT),
"evsplati $RT, $RA", IIC_VecGeneral>; (ins sperc:$RA, sperc:$RB, crrc:$crD),
"evsel crD,$RT,$RA,$RB", IIC_VecGeneral, []>;
def EVSRWIS : EVXForm_1<547, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB),
"evsrwis $RT, $RA, $RB", IIC_VecGeneral>; def EVSLWI : EVXForm_1<550, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
def EVSRWIU : EVXForm_1<546, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB), "evslwi $RT, $RA, $RB", IIC_VecGeneral, []>;
"evsrwiu $RT, $RA, $RB", IIC_VecGeneral>; def EVSLW : EVXForm_1<548, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVSRWS : EVXForm_1<545, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evslw $RT, $RA, $RB", IIC_VecGeneral,
"evsrws $RT, $RA, $RB", IIC_VecGeneral>; []>;
def EVSRWU : EVXForm_1<544, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"evsrwu $RT, $RA, $RB", IIC_VecGeneral>; def EVSPLATFI : EVXForm_2<555, (outs sperc:$RT), (ins s5imm:$RA),
"evsplatfi $RT, $RA", IIC_VecGeneral, []>;
def EVSTDD : EVXForm_D<801, (outs), (ins gprc:$RT, spe8dis:$dst), def EVSPLATI : EVXForm_2<553, (outs sperc:$RT), (ins s5imm:$RA),
"evstdd $RT, $dst", IIC_LdStStore>; "evsplati $RT, $RA", IIC_VecGeneral, []>;
def EVSTDDX : EVXForm_1<800, (outs), (ins gprc:$RT, memrr:$dst),
"evstddx $RT, $dst", IIC_LdStStore>; def EVSRWIS : EVXForm_1<547, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
def EVSTDH : EVXForm_D<805, (outs), (ins gprc:$RT, spe8dis:$dst), "evsrwis $RT, $RA, $RB", IIC_VecGeneral, []>;
"evstdh $RT, $dst", IIC_LdStStore>; def EVSRWIU : EVXForm_1<546, (outs sperc:$RT), (ins sperc:$RA, u5imm:$RB),
def EVSTDHX : EVXForm_1<804, (outs), (ins gprc:$RT, memrr:$dst), "evsrwiu $RT, $RA, $RB", IIC_VecGeneral, []>;
"evstdhx $RT, $dst", IIC_LdStStore>; def EVSRWS : EVXForm_1<545, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
def EVSTDW : EVXForm_D<803, (outs), (ins gprc:$RT, spe8dis:$dst), "evsrws $RT, $RA, $RB", IIC_VecGeneral,
"evstdw $RT, $dst", IIC_LdStStore>; []>;
def EVSTDWX : EVXForm_1<802, (outs), (ins gprc:$RT, memrr:$dst), def EVSRWU : EVXForm_1<544, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evstdwx $RT, $dst", IIC_LdStStore>; "evsrwu $RT, $RA, $RB", IIC_VecGeneral,
def EVSTWHE : EVXForm_D<817, (outs), (ins gprc:$RT, spe4dis:$dst), []>;
"evstwhe $RT, $dst", IIC_LdStStore>;
def EVSTWHEX : EVXForm_1<816, (outs), (ins gprc:$RT, memrr:$dst), def EVSTDD : EVXForm_D<801, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstwhex $RT, $dst", IIC_LdStStore>; "evstdd $RT, $dst", IIC_LdStStore,
def EVSTWHO : EVXForm_D<821, (outs), (ins gprc:$RT, spe4dis:$dst), [(store f64:$RT, iaddr:$dst)]>;
"evstwho $RT, $dst", IIC_LdStStore>; def EVSTDDX : EVXForm_1<800, (outs), (ins sperc:$RT, memrr:$dst),
def EVSTWHOX : EVXForm_1<820, (outs), (ins gprc:$RT, memrr:$dst), "evstddx $RT, $dst", IIC_LdStStore,
"evstwhox $RT, $dst", IIC_LdStStore>; [(store f64:$RT, xaddr:$dst)]>;
def EVSTWWE : EVXForm_D<825, (outs), (ins gprc:$RT, spe4dis:$dst), def EVSTDH : EVXForm_D<805, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstwwe $RT, $dst", IIC_LdStStore>; "evstdh $RT, $dst", IIC_LdStStore, []>;
def EVSTWWEX : EVXForm_1<824, (outs), (ins gprc:$RT, memrr:$dst), def EVSTDHX : EVXForm_1<804, (outs), (ins sperc:$RT, memrr:$dst),
"evstwwex $RT, $dst", IIC_LdStStore>; "evstdhx $RT, $dst", IIC_LdStStore, []>;
def EVSTWWO : EVXForm_D<829, (outs), (ins gprc:$RT, spe4dis:$dst), def EVSTDW : EVXForm_D<803, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstwwo $RT, $dst", IIC_LdStStore>; "evstdw $RT, $dst", IIC_LdStStore,
def EVSTWWOX : EVXForm_1<828, (outs), (ins gprc:$RT, memrr:$dst), []>;
"evstwwox $RT, $dst", IIC_LdStStore>; def EVSTDWX : EVXForm_1<802, (outs), (ins sperc:$RT, memrr:$dst),
"evstdwx $RT, $dst", IIC_LdStStore,
def EVSUBFSSIAAW : EVXForm_2<1219, (outs gprc:$RT), (ins gprc:$RA), []>;
"evsubfssiaaw $RT, $RA", IIC_VecComplex>; def EVSTWHE : EVXForm_D<817, (outs), (ins sperc:$RT, spe4dis:$dst),
def EVSUBFSMIAAW : EVXForm_2<1227, (outs gprc:$RT), (ins gprc:$RA), "evstwhe $RT, $dst", IIC_LdStStore, []>;
"evsubfsmiaaw $RT, $RA", IIC_VecComplex>; def EVSTWHEX : EVXForm_1<816, (outs), (ins sperc:$RT, memrr:$dst),
def EVSUBFUMIAAW : EVXForm_2<1226, (outs gprc:$RT), (ins gprc:$RA), "evstwhex $RT, $dst", IIC_LdStStore, []>;
"evsubfumiaaw $RT, $RA", IIC_VecComplex>; def EVSTWHO : EVXForm_D<821, (outs), (ins sperc:$RT, spe4dis:$dst),
def EVSUBFUSIAAW : EVXForm_2<1218, (outs gprc:$RT), (ins gprc:$RA), "evstwho $RT, $dst", IIC_LdStStore, []>;
"evsubfusiaaw $RT, $RA", IIC_VecComplex>; def EVSTWHOX : EVXForm_1<820, (outs), (ins sperc:$RT, memrr:$dst),
def EVSUBFW : EVXForm_1<516, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evstwhox $RT, $dst", IIC_LdStStore, []>;
"evsubfw $RT, $RA, $RB", IIC_VecGeneral>; def EVSTWWE : EVXForm_D<825, (outs), (ins sperc:$RT, spe4dis:$dst),
def EVSUBIFW : EVXForm_1<518, (outs gprc:$RT), (ins u5imm:$RA, gprc:$RB), "evstwwe $RT, $dst", IIC_LdStStore, []>;
"evsubifw $RT, $RA, $RB", IIC_VecGeneral>; def EVSTWWEX : EVXForm_1<824, (outs), (ins sperc:$RT, memrr:$dst),
def EVXOR : EVXForm_1<534, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), "evstwwex $RT, $dst", IIC_LdStStore, []>;
"evxor $RT, $RA, $RB", IIC_VecGeneral>; def EVSTWWO : EVXForm_D<829, (outs), (ins sperc:$RT, spe4dis:$dst),
"evstwwo $RT, $dst", IIC_LdStStore, []>;
def EVSTWWOX : EVXForm_1<828, (outs), (ins sperc:$RT, memrr:$dst),
"evstwwox $RT, $dst", IIC_LdStStore, []>;
def EVSUBFSSIAAW : EVXForm_2<1219, (outs sperc:$RT), (ins sperc:$RA),
"evsubfssiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFSMIAAW : EVXForm_2<1227, (outs sperc:$RT), (ins sperc:$RA),
"evsubfsmiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFUMIAAW : EVXForm_2<1226, (outs sperc:$RT), (ins sperc:$RA),
"evsubfumiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFUSIAAW : EVXForm_2<1218, (outs sperc:$RT), (ins sperc:$RA),
"evsubfusiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFW : EVXForm_1<516, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evsubfw $RT, $RA, $RB", IIC_VecGeneral,
[]>;
def EVSUBIFW : EVXForm_1<518, (outs sperc:$RT), (ins u5imm:$RA, sperc:$RB),
"evsubifw $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVXOR : EVXForm_1<534, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evxor $RT, $RA, $RB", IIC_VecGeneral,
[]>;
let isAsmParserOnly = 1 in {
// Identical to the integer Load/Stores, but to handle floats
def SPELWZ : DForm_1<32, (outs spe4rc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad,
[(set f32:$rD, (load iaddr:$src))]>;
def SPELWZX : XForm_1<31, 23, (outs spe4rc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad,
[(set f32:$rD, (load xaddr:$src))]>;
def SPESTW : DForm_1<36, (outs), (ins spe4rc:$rS, memri:$src),
"stw $rS, $src", IIC_LdStStore,
[(store f32:$rS, iaddr:$src)]>;
def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$rS, memrr:$dst),
"stwx $rS, $dst", IIC_LdStStore,
[(store f32:$rS, xaddr:$dst)]>;
}
} // HasSPE } // HasSPE
let Predicates = [HasSPE] in {
def : Pat<(f64 (extloadf32 iaddr:$src)),
(COPY_TO_REGCLASS (SPELWZ iaddr:$src), SPERC)>;
def : Pat<(f64 (extloadf32 xaddr:$src)),
(COPY_TO_REGCLASS (SPELWZX xaddr:$src), SPERC)>;
def : Pat<(f64 (fpextend f32:$src)),
(COPY_TO_REGCLASS $src, SPERC)>;
}
let Predicates = [HasSPE] in {
let usesCustomInserter = 1 in {
def SELECT_CC_SPE4 : Pseudo<(outs spe4rc:$dst),
(ins crrc:$cond, spe4rc:$T, spe4rc:$F,
i32imm:$BROPC), "#SELECT_CC_SPE4",
[]>;
def SELECT_CC_SPE : Pseudo<(outs sperc:$dst),
(ins crrc:$cond, sperc:$T, sperc:$F, i32imm:$BROPC),
"#SELECT_CC_SPE",
[]>;
def SELECT_SPE4 : Pseudo<(outs spe4rc:$dst), (ins crbitrc:$cond,
spe4rc:$T, spe4rc:$F), "#SELECT_SPE4",
[(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
def SELECT_SPE : Pseudo<(outs sperc:$dst), (ins crbitrc:$cond,
sperc:$T, sperc:$F), "#SELECT_SPE",
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
}
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
(SELECT_SPE4 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
(SELECT_SPE4 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
(SELECT_SPE4 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
(SELECT_SPE4 (CRORC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
(SELECT_SPE4 (CREQV $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
(SELECT_SPE4 (CRORC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
(SELECT_SPE4 (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
(SELECT_SPE4 (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
(SELECT_SPE4 (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
(SELECT_SPE4 (CRXOR $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
(SELECT_SPE (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
(SELECT_SPE (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
(SELECT_SPE (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
(SELECT_SPE (CRORC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
(SELECT_SPE (CREQV $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
(SELECT_SPE (CRORC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
(SELECT_SPE (CRORC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
(SELECT_SPE (CRANDC $rhs, $lhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
(SELECT_SPE (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
(SELECT_SPE (CRXOR $lhs, $rhs), $tval, $fval)>;
}

lib/Target/PowerPC/PPCRegisterInfo.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 LinesPPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
ImmToIdxMap[PPC::LXV] = PPC::LXVX; ImmToIdxMap[PPC::LXV] = PPC::LXVX;
ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
ImmToIdxMap[PPC::STXV] = PPC::STXVX; ImmToIdxMap[PPC::STXV] = PPC::STXVX;
ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
// SPE
ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
} }
/// getPointerRegClass - Return the register class to use to hold pointers. /// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes. /// This is used for addressing modes.
const TargetRegisterClass * const TargetRegisterClass *
PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
const { const {
// Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
Show All 25 Lines return TM.isPPC64()
? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
: CSR_Darwin64_SaveList) : CSR_Darwin64_SaveList)
: (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
: CSR_Darwin32_SaveList); : CSR_Darwin32_SaveList);
if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
return CSR_SRV464_TLS_PE_SaveList; return CSR_SRV464_TLS_PE_SaveList;
if (Subtarget.hasSPE())
nemanjaiUnsubmitted
Done
ReplyInline Actions

There is a note below describing the alternate allocation order of SPE registers for PPC64 SVR4 ABI. This somewhat implies that if R2 is allocatable (i.e. no TOC uses), that it needs to be saved/restored. Do we not want to make R2 a callee-saved register if it is allocatable?

nemanjai: There is a note below describing the alternate allocation order of SPE registers for PPC64 SVR4…
return CSR_SVR432_SPE_SaveList;
// On PPC64, we might need to save r2 (but only if it is not reserved). // On PPC64, we might need to save r2 (but only if it is not reserved).
bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
if (MF->getFunction().getCallingConv() == CallingConv::Cold) { if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
return TM.isPPC64() return TM.isPPC64()
? (Subtarget.hasAltivec() ? (Subtarget.hasAltivec()
? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
: CSR_SVR64_ColdCC_Altivec_SaveList) : CSR_SVR64_ColdCC_Altivec_SaveList)
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Linesunsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
const PPCFrameLowering *TFI = getFrameLowering(MF); const PPCFrameLowering *TFI = getFrameLowering(MF);
const unsigned DefaultSafety = 1; const unsigned DefaultSafety = 1;
switch (RC->getID()) { switch (RC->getID()) {
default: default:
return 0; return 0;
case PPC::G8RC_NOX0RegClassID: case PPC::G8RC_NOX0RegClassID:
case PPC::GPRC_NOR0RegClassID: case PPC::GPRC_NOR0RegClassID:
case PPC::SPERCRegClassID:
case PPC::SPE4RCRegClassID:
case PPC::G8RCRegClassID: case PPC::G8RCRegClassID:
case PPC::GPRCRegClassID: { case PPC::GPRCRegClassID: {
unsigned FP = TFI->hasFP(MF) ? 1 : 0; unsigned FP = TFI->hasFP(MF) ? 1 : 0;
return 32 - FP - DefaultSafety; return 32 - FP - DefaultSafety;
} }
case PPC::F8RCRegClassID: case PPC::F8RCRegClassID:
case PPC::F4RCRegClassID: case PPC::F4RCRegClassID:
case PPC::QFRCRegClassID: case PPC::QFRCRegClassID:
▲ Show 20 Lines • Show All 800 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCRegisterInfo.td

Show All 32 Lines
// GP8 - One of the 32 64-bit general-purpose registers // GP8 - One of the 32 64-bit general-purpose registers
class GP8<GPR SubReg, string n> : PPCReg<n> { class GP8<GPR SubReg, string n> : PPCReg<n> {
let HWEncoding = SubReg.HWEncoding; let HWEncoding = SubReg.HWEncoding;
let SubRegs = [SubReg]; let SubRegs = [SubReg];
let SubRegIndices = [sub_32]; let SubRegIndices = [sub_32];
} }
// SPE - One of the 32 64-bit general-purpose registers (SPE)
class SPE<GPR SubReg, string n> : PPCReg<n> {
let HWEncoding = SubReg.HWEncoding;
let SubRegs = [SubReg];
let SubRegIndices = [sub_32];
}
// SPR - One of the 32-bit special-purpose registers // SPR - One of the 32-bit special-purpose registers
class SPR<bits<10> num, string n> : PPCReg<n> { class SPR<bits<10> num, string n> : PPCReg<n> {
let HWEncoding{9-0} = num; let HWEncoding{9-0} = num;
} }
// FPR - One of the 32 64-bit floating-point registers // FPR - One of the 32 64-bit floating-point registers
class FPR<bits<5> num, string n> : PPCReg<n> { class FPR<bits<5> num, string n> : PPCReg<n> {
let HWEncoding{4-0} = num; let HWEncoding{4-0} = num;
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
} }
// 64-bit General-purpose registers // 64-bit General-purpose registers
foreach Index = 0-31 in { foreach Index = 0-31 in {
def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
DwarfRegNum<[Index, -2]>; DwarfRegNum<[Index, -2]>;
} }
// SPE registers
foreach Index = 0-31 in {
def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>,
DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
}
// Floating-point registers // Floating-point registers
foreach Index = 0-31 in { foreach Index = 0-31 in {
def F#Index : FPR<Index, "f"#Index>, def F#Index : FPR<Index, "f"#Index>,
DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
} }
// 64-bit Floating-point subregisters of Altivec registers // 64-bit Floating-point subregisters of Altivec registers
// Note: the register names are v0-v31 or vs32-vs63 depending on the use. // Note: the register names are v0-v31 or vs32-vs63 depending on the use.
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
// Count register // Count register
def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
// VRsave register // VRsave register
def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
// SPE extra registers
// SPE Accumulator for multiply-accumulate SPE operations. Never directly
// accessed, so there's no real encoding for it.
def SPEACC: DwarfRegNum<[99, 111]>;
def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
def XER: SPR<1, "xer">, DwarfRegNum<[76]>; def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
// Carry bit. In the architecture this is really bit 0 of the XER register // Carry bit. In the architecture this is really bit 0 of the XER register
// (which really is SPR register 1); this is the only bit interesting to a // (which really is SPR register 1); this is the only bit interesting to a
// compiler. // compiler.
def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> { def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
let Aliases = [XER]; let Aliases = [XER];
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesdef G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
// put it at the end of the list. // put it at the end of the list.
let AltOrders = [(add (sub G8RC_NOX0, X2), X2)]; let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
let AltOrderSelect = [{ let AltOrderSelect = [{
const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
return S.isPPC64() && S.isSVR4ABI(); return S.isPPC64() && S.isSVR4ABI();
}]; }];
} }
def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
(sequence "S%u", 30, 13),
S31, S0, S1)>;
def SPE4RC : RegisterClass<"PPC", [f32], 32, (add GPRC)>;
// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
// ABI the size of the Floating-point register save area is determined by the // ABI the size of the Floating-point register save area is determined by the
// allocated non-volatile register with the lowest register number, as FP // allocated non-volatile register with the lowest register number, as FP
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

I may have mixed things up here, but for some reason I was under the impression that SPE isn't available on 64-bit PPC targets.

nemanjai: I may have mixed things up here, but for some reason I was under the impression that SPE isn't…
jhibbitsAuthorUnsubmitted
Not Done
ReplyInline Actions

Yeah, this was a copy&paste. Doesn't make sense to have the body.

jhibbits: Yeah, this was a copy&paste. Doesn't make sense to have the body.
// register N is spilled to offset 8 * (32 - N) below the back chain word of the // register N is spilled to offset 8 * (32 - N) below the back chain word of the
// previous stack frame. By allocating non-volatiles in reverse order we make // previous stack frame. By allocating non-volatiles in reverse order we make
// sure that the Floating-point register save area is always as small as // sure that the Floating-point register save area is always as small as
// possible because there aren't any unused spill slots. // possible because there aren't any unused spill slots.
def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
(sequence "F%u", 31, 14))>; (sequence "F%u", 31, 14))>;
def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCSubtarget.h

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Linesprotected:
/// Used by the ISel to turn in optimizations for POWER4-derived architectures /// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool HasMFOCRF; bool HasMFOCRF;
bool Has64BitSupport; bool Has64BitSupport;
bool Use64BitRegs; bool Use64BitRegs;
bool UseCRBits; bool UseCRBits;
bool HasHardFloat; bool HasHardFloat;
bool IsPPC64; bool IsPPC64;
bool HasAltivec; bool HasAltivec;
bool HasFPU;
bool HasSPE; bool HasSPE;
bool HasQPX; bool HasQPX;
bool HasVSX; bool HasVSX;
bool HasP8Vector; bool HasP8Vector;
bool HasP8Altivec; bool HasP8Altivec;
bool HasP8Crypto; bool HasP8Crypto;
bool HasP9Vector; bool HasP9Vector;
bool HasP9Altivec; bool HasP9Altivec;
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Linespublic:
bool hasFRSQRTES() const { return HasFRSQRTES; } bool hasFRSQRTES() const { return HasFRSQRTES; }
bool hasRecipPrec() const { return HasRecipPrec; } bool hasRecipPrec() const { return HasRecipPrec; }
bool hasSTFIWX() const { return HasSTFIWX; } bool hasSTFIWX() const { return HasSTFIWX; }
bool hasLFIWAX() const { return HasLFIWAX; } bool hasLFIWAX() const { return HasLFIWAX; }
bool hasFPRND() const { return HasFPRND; } bool hasFPRND() const { return HasFPRND; }
bool hasFPCVT() const { return HasFPCVT; } bool hasFPCVT() const { return HasFPCVT; }
bool hasAltivec() const { return HasAltivec; } bool hasAltivec() const { return HasAltivec; }
bool hasSPE() const { return HasSPE; } bool hasSPE() const { return HasSPE; }
bool hasFPU() const { return HasFPU; }
bool hasQPX() const { return HasQPX; } bool hasQPX() const { return HasQPX; }
bool hasVSX() const { return HasVSX; } bool hasVSX() const { return HasVSX; }
bool hasP8Vector() const { return HasP8Vector; } bool hasP8Vector() const { return HasP8Vector; }
bool hasP8Altivec() const { return HasP8Altivec; } bool hasP8Altivec() const { return HasP8Altivec; }
bool hasP8Crypto() const { return HasP8Crypto; } bool hasP8Crypto() const { return HasP8Crypto; }
bool hasP9Vector() const { return HasP9Vector; } bool hasP9Vector() const { return HasP9Vector; }
bool hasP9Altivec() const { return HasP9Altivec; } bool hasP9Altivec() const { return HasP9Altivec; }
bool hasMFOCRF() const { return HasMFOCRF; } bool hasMFOCRF() const { return HasMFOCRF; }
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCSubtarget.cpp

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Linesvoid PPCSubtarget::initializeEnvironment() {
DarwinDirective = PPC::DIR_NONE; DarwinDirective = PPC::DIR_NONE;
HasMFOCRF = false; HasMFOCRF = false;
Has64BitSupport = false; Has64BitSupport = false;
Use64BitRegs = false; Use64BitRegs = false;
UseCRBits = false; UseCRBits = false;
HasHardFloat = false; HasHardFloat = false;
HasAltivec = false; HasAltivec = false;
HasSPE = false; HasSPE = false;
HasFPU = false;
HasQPX = false; HasQPX = false;
HasVSX = false; HasVSX = false;
HasP8Vector = false; HasP8Vector = false;
HasP8Altivec = false; HasP8Altivec = false;
HasP8Crypto = false; HasP8Crypto = false;
HasP9Vector = false; HasP9Vector = false;
HasP9Altivec = false; HasP9Altivec = false;
HasFCPSGN = false; HasFCPSGN = false;
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesvoid PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
// support it, ignore. // support it, ignore.
if (IsPPC64 && has64BitSupport()) if (IsPPC64 && has64BitSupport())
Use64BitRegs = true; Use64BitRegs = true;
// Set up darwin-specific properties. // Set up darwin-specific properties.
if (isDarwin()) if (isDarwin())
HasLazyResolverStubs = true; HasLazyResolverStubs = true;
if (HasSPE && IsPPC64)
report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
report_fatal_error(
"SPE and traditional floating point cannot both be enabled.\n", false);
// If not SPE, set standard FPU
if (!HasSPE)
HasFPU = true;
// QPX requires a 32-byte aligned stack. Note that we need to do this if // QPX requires a 32-byte aligned stack. Note that we need to do this if
// we're compiling for a BG/Q system regardless of whether or not QPX // we're compiling for a BG/Q system regardless of whether or not QPX
// is enabled because external functions will assume this alignment. // is enabled because external functions will assume this alignment.
IsQPXStackUnaligned = QPXStackUnaligned; IsQPXStackUnaligned = QPXStackUnaligned;
StackAlignment = getPlatformStackAlignment(); StackAlignment = getPlatformStackAlignment();
// Determine endianness. // Determine endianness.
// FIXME: Part of the TargetMachine. // FIXME: Part of the TargetMachine.
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test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-LABEL: __fixunstfdi: ; CHECK-LABEL: __fixunstfdi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1) ; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -464(1) ; CHECK-NEXT: stwu 1, -464(1)
; CHECK-NEXT: lis 3, .LCPI0_0@ha
; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
; CHECK-NEXT: mfcr 12 ; CHECK-NEXT: mfcr 12
; CHECK-NEXT: lfs 27, .LCPI0_0@l(3) ; CHECK-NEXT: lis 3, .LCPI0_0@ha
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
; CHECK-NEXT: stw 12, 408(1)
; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
; CHECK-NEXT: fcmpu 0, 2, 27 ; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
; CHECK-NEXT: stw 12, 408(1)
; CHECK-NEXT: fcmpu 1, 1, 27
; CHECK-NEXT: stfd 2, 376(1) ; CHECK-NEXT: stfd 2, 376(1)
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: stfd 1, 384(1) ; CHECK-NEXT: stfd 1, 384(1)
; CHECK-NEXT: cror 20, 4, 20 ; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: lwz 3, 380(1) ; CHECK-NEXT: lwz 3, 380(1)
; CHECK-NEXT: lwz 4, 376(1) ; CHECK-NEXT: lwz 4, 376(1)
; CHECK-NEXT: lwz 5, 388(1) ; CHECK-NEXT: lwz 5, 388(1)
; CHECK-NEXT: lwz 6, 384(1) ; CHECK-NEXT: lwz 6, 384(1)
; CHECK-NEXT: fcmpu 1, 1, 27
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: stw 3, 396(1) ; CHECK-NEXT: stw 3, 396(1)
; CHECK-NEXT: stw 4, 392(1) ; CHECK-NEXT: stw 4, 392(1)
; CHECK-NEXT: stw 5, 404(1) ; CHECK-NEXT: stw 5, 404(1)
; CHECK-NEXT: stw 6, 400(1) ; CHECK-NEXT: stw 6, 400(1)
; CHECK-NEXT: bc 4, 20, .LBB0_2 ; CHECK-NEXT: bc 4, 20, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb5 ; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: addis 3, 3, -32768 ; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_14 ; CHECK-NEXT: bc 12, 20, .LBB0_14
; CHECK-NEXT: b .LBB0_15 ; CHECK-NEXT: b .LBB0_15
; CHECK-NEXT: .LBB0_14: # %bb3 ; CHECK-NEXT: .LBB0_14: # %bb3
; CHECK-NEXT: addi 4, 3, 0 ; CHECK-NEXT: addi 4, 3, 0
; CHECK-NEXT: .LBB0_15: # %bb3 ; CHECK-NEXT: .LBB0_15: # %bb3
; CHECK-NEXT: mr 3, 30 ; CHECK-NEXT: mr 3, 30
; CHECK-NEXT: .LBB0_16: # %bb5 ; CHECK-NEXT: .LBB0_16: # %bb5
; CHECK-NEXT: lwz 12, 408(1)
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
; CHECK-NEXT: mtcrf 32, 12 # cr2
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 12, 408(1)
; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload
; CHECK-NEXT: mtcrf 32, 12 # cr2
; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload
; CHECK-NEXT: lwz 0, 468(1) ; CHECK-NEXT: lwz 0, 468(1)
; CHECK-NEXT: addi 1, 1, 464 ; CHECK-NEXT: addi 1, 1, 464
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1] %0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb1 br i1 %0, label %bb5, label %bb1
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test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
define void @t1a(float %a) nounwind { define void @t1a(float %a) nounwind {
entry: entry:
; ELF64: t1a ; ELF64: t1a
; SPE: t1a
%cmp = fcmp oeq float %a, 0.000000e+00 %cmp = fcmp oeq float %a, 0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfs ; ELF64: lfs
; ELF64: fcmpu ; ELF64: fcmpu
; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
call void @foo() call void @foo()
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
} }
declare void @foo() declare void @foo()
define void @t1b(float %a) nounwind { define void @t1b(float %a) nounwind {
entry: entry:
; ELF64: t1b ; ELF64: t1b
; SPE: t1b
%cmp = fcmp oeq float %a, -0.000000e+00 %cmp = fcmp oeq float %a, -0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfs ; ELF64: lfs
; ELF64: fcmpu ; ELF64: fcmpu
; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
call void @foo() call void @foo()
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
} }
define void @t2a(double %a) nounwind { define void @t2a(double %a) nounwind {
entry: entry:
; ELF64: t2a ; ELF64: t2a
; SPE: t2a
%cmp = fcmp oeq double %a, 0.000000e+00 %cmp = fcmp oeq double %a, 0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfd ; ELF64: lfd
; ELF64: fcmpu ; ELF64: fcmpu
; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
call void @foo() call void @foo()
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
} }
define void @t2b(double %a) nounwind { define void @t2b(double %a) nounwind {
entry: entry:
; ELF64: t2b ; ELF64: t2b
; SPE: t2b
%cmp = fcmp oeq double %a, -0.000000e+00 %cmp = fcmp oeq double %a, -0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfd ; ELF64: lfd
; ELF64: fcmpu ; ELF64: fcmpu
; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
call void @foo() call void @foo()
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
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test/CodeGen/PowerPC/fast-isel-conversion.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s
; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
;; to SelectionDAG in some cases. ;; to SelectionDAG in some cases.
; Test sitofp ; Test sitofp
define void @sitofp_single_i64(i64 %a, float %b) nounwind { define void @sitofp_single_i64(i64 %a, float %b) nounwind {
entry: entry:
Show All 21 Lines
; CHECK: std ; CHECK: std
; CHECK-NEXT: li ; CHECK-NEXT: li
; CHECK-NEXT: lfiwax ; CHECK-NEXT: lfiwax
; CHECK-NEXT: fcfids ; CHECK-NEXT: fcfids
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; PPC970: frsp ; PPC970: frsp
; SPE: efscfsi
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @sitofp_single_i16(i16 %a, float %b) nounwind { define void @sitofp_single_i16(i16 %a, float %b) nounwind {
entry: entry:
; CHECK: sitofp_single_i16 ; CHECK: sitofp_single_i16
; PPC970: sitofp_single_i16 ; PPC970: sitofp_single_i16
%b.addr = alloca float, align 4 %b.addr = alloca float, align 4
%conv = sitofp i16 %a to float %conv = sitofp i16 %a to float
; CHECK: extsh ; CHECK: extsh
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfids ; CHECK: fcfids
; PPC970: extsh ; PPC970: extsh
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; PPC970: frsp ; PPC970: frsp
; SPE: extsh
; SPE: efscfsi
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @sitofp_single_i8(i8 %a) nounwind { define void @sitofp_single_i8(i8 %a) nounwind {
entry: entry:
; CHECK: sitofp_single_i8 ; CHECK: sitofp_single_i8
; PPC970: sitofp_single_i8 ; PPC970: sitofp_single_i8
%b.addr = alloca float, align 4 %b.addr = alloca float, align 4
%conv = sitofp i8 %a to float %conv = sitofp i8 %a to float
; CHECK: extsb ; CHECK: extsb
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfids ; CHECK: fcfids
; PPC970: extsb ; PPC970: extsb
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; PPC970: frsp ; PPC970: frsp
; SPE: extsb
; SPE: efscfsi
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @sitofp_double_i32(i32 %a, double %b) nounwind { define void @sitofp_double_i32(i32 %a, double %b) nounwind {
entry: entry:
; CHECK: sitofp_double_i32 ; CHECK: sitofp_double_i32
; PPC970: sitofp_double_i32 ; PPC970: sitofp_double_i32
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = sitofp i32 %a to double %conv = sitofp i32 %a to double
; CHECK: std ; CHECK: std
; CHECK-NOT: ori ; CHECK-NOT: ori
; CHECK: li ; CHECK: li
; CHECK-NOT: ori ; CHECK-NOT: ori
; CHECK: lfiwax ; CHECK: lfiwax
; CHECK: fcfid ; CHECK: fcfid
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; SPE: efdcfsi
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
define void @sitofp_double_i64(i64 %a, double %b) nounwind { define void @sitofp_double_i64(i64 %a, double %b) nounwind {
entry: entry:
; CHECK: sitofp_double_i64 ; CHECK: sitofp_double_i64
; PPC970: sitofp_double_i64 ; PPC970: sitofp_double_i64
Show All 18 Lines
; CHECK: extsh ; CHECK: extsh
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfid ; CHECK: fcfid
; PPC970: extsh ; PPC970: extsh
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; SPE: extsh
; SPE: efdcfsi
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
define void @sitofp_double_i8(i8 %a, double %b) nounwind { define void @sitofp_double_i8(i8 %a, double %b) nounwind {
entry: entry:
; CHECK: sitofp_double_i8 ; CHECK: sitofp_double_i8
; PPC970: sitofp_double_i8 ; PPC970: sitofp_double_i8
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = sitofp i8 %a to double %conv = sitofp i8 %a to double
; CHECK: extsb ; CHECK: extsb
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfid ; CHECK: fcfid
; PPC970: extsb ; PPC970: extsb
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; SPE: extsb
; SPE: efdcfsi
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
; Test uitofp ; Test uitofp
define void @uitofp_single_i64(i64 %a, float %b) nounwind { define void @uitofp_single_i64(i64 %a, float %b) nounwind {
entry: entry:
Show All 18 Lines
; CHECK: std ; CHECK: std
; CHECK-NOT: ori ; CHECK-NOT: ori
; CHECK: li ; CHECK: li
; CHECK-NOT: ori ; CHECK-NOT: ori
; CHECK: lfiwzx ; CHECK: lfiwzx
; CHECK: fcfidus ; CHECK: fcfidus
; PPC970-NOT: lfiwzx ; PPC970-NOT: lfiwzx
; PPC970-NOT: fcfidus ; PPC970-NOT: fcfidus
; SPE: efscfui
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @uitofp_single_i16(i16 %a, float %b) nounwind { define void @uitofp_single_i16(i16 %a, float %b) nounwind {
entry: entry:
; CHECK: uitofp_single_i16 ; CHECK: uitofp_single_i16
; PPC970: uitofp_single_i16 ; PPC970: uitofp_single_i16
%b.addr = alloca float, align 4 %b.addr = alloca float, align 4
%conv = uitofp i16 %a to float %conv = uitofp i16 %a to float
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfidus ; CHECK: fcfidus
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; PPC970: frsp ; PPC970: frsp
; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; SPE: efscfui
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @uitofp_single_i8(i8 %a) nounwind { define void @uitofp_single_i8(i8 %a) nounwind {
entry: entry:
; CHECK: uitofp_single_i8 ; CHECK: uitofp_single_i8
; PPC970: uitofp_single_i8 ; PPC970: uitofp_single_i8
%b.addr = alloca float, align 4 %b.addr = alloca float, align 4
%conv = uitofp i8 %a to float %conv = uitofp i8 %a to float
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfidus ; CHECK: fcfidus
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; PPC970: frsp ; PPC970: frsp
; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; SPE: efscfui
store float %conv, float* %b.addr, align 4 store float %conv, float* %b.addr, align 4
ret void ret void
} }
define void @uitofp_double_i64(i64 %a, double %b) nounwind { define void @uitofp_double_i64(i64 %a, double %b) nounwind {
entry: entry:
; CHECK: uitofp_double_i64 ; CHECK: uitofp_double_i64
; PPC970: uitofp_double_i64 ; PPC970: uitofp_double_i64
Show All 15 Lines; PPC970: uitofp_double_i32
%conv = uitofp i32 %a to double %conv = uitofp i32 %a to double
; CHECK: std ; CHECK: std
; CHECK-NEXT: li ; CHECK-NEXT: li
; CHECK-NEXT: lfiwzx ; CHECK-NEXT: lfiwzx
; CHECK-NEXT: fcfidu ; CHECK-NEXT: fcfidu
; CHECKLE: fcfidu ; CHECKLE: fcfidu
; PPC970-NOT: lfiwzx ; PPC970-NOT: lfiwzx
; PPC970-NOT: fcfidu ; PPC970-NOT: fcfidu
; SPE: efdcfui
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
define void @uitofp_double_i16(i16 %a, double %b) nounwind { define void @uitofp_double_i16(i16 %a, double %b) nounwind {
entry: entry:
; CHECK: uitofp_double_i16 ; CHECK: uitofp_double_i16
; PPC970: uitofp_double_i16 ; PPC970: uitofp_double_i16
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = uitofp i16 %a to double %conv = uitofp i16 %a to double
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfidu ; CHECK: fcfidu
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; SPE: efdcfui
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
define void @uitofp_double_i8(i8 %a, double %b) nounwind { define void @uitofp_double_i8(i8 %a, double %b) nounwind {
entry: entry:
; CHECK: uitofp_double_i8 ; CHECK: uitofp_double_i8
; PPC970: uitofp_double_i8 ; PPC970: uitofp_double_i8
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = uitofp i8 %a to double %conv = uitofp i8 %a to double
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
; CHECK: std ; CHECK: std
; CHECK: lfd ; CHECK: lfd
; CHECK: fcfidu ; CHECK: fcfidu
; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; PPC970: std ; PPC970: std
; PPC970: lfd ; PPC970: lfd
; PPC970: fcfid ; PPC970: fcfid
; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; SPE: efdcfui
store double %conv, double* %b.addr, align 8 store double %conv, double* %b.addr, align 8
ret void ret void
} }
; Test fptosi ; Test fptosi
define void @fptosi_float_i32(float %a) nounwind { define void @fptosi_float_i32(float %a) nounwind {
entry: entry:
; CHECK: fptosi_float_i32 ; CHECK: fptosi_float_i32
; PPC970: fptosi_float_i32 ; PPC970: fptosi_float_i32
%b.addr = alloca i32, align 4 %b.addr = alloca i32, align 4
%conv = fptosi float %a to i32 %conv = fptosi float %a to i32
; CHECK: fctiwz ; CHECK: fctiwz
; CHECK: stfd ; CHECK: stfd
; CHECK: lwa ; CHECK: lwa
; PPC970: fctiwz ; PPC970: fctiwz
; PPC970: stfd ; PPC970: stfd
; PPC970: lwa ; PPC970: lwa
; SPE: efsctsi
store i32 %conv, i32* %b.addr, align 4 store i32 %conv, i32* %b.addr, align 4
ret void ret void
} }
define void @fptosi_float_i64(float %a) nounwind { define void @fptosi_float_i64(float %a) nounwind {
entry: entry:
; CHECK: fptosi_float_i64 ; CHECK: fptosi_float_i64
; PPC970: fptosi_float_i64 ; PPC970: fptosi_float_i64
Show All 16 Lines; PPC970: fptosi_double_i32
%b.addr = alloca i32, align 8 %b.addr = alloca i32, align 8
%conv = fptosi double %a to i32 %conv = fptosi double %a to i32
; CHECK: fctiwz ; CHECK: fctiwz
; CHECK: stfd ; CHECK: stfd
; CHECK: lwa ; CHECK: lwa
; PPC970: fctiwz ; PPC970: fctiwz
; PPC970: stfd ; PPC970: stfd
; PPC970: lwa ; PPC970: lwa
; SPE: efdctsi
store i32 %conv, i32* %b.addr, align 8 store i32 %conv, i32* %b.addr, align 8
ret void ret void
} }
define void @fptosi_double_i64(double %a) nounwind { define void @fptosi_double_i64(double %a) nounwind {
entry: entry:
; CHECK: fptosi_double_i64 ; CHECK: fptosi_double_i64
; PPC970: fptosi_double_i64 ; PPC970: fptosi_double_i64
Show All 18 Lines; PPC970: fptoui_float_i32
%b.addr = alloca i32, align 4 %b.addr = alloca i32, align 4
%conv = fptoui float %a to i32 %conv = fptoui float %a to i32
; CHECK: fctiwuz ; CHECK: fctiwuz
; CHECK: stfd ; CHECK: stfd
; CHECK: lwz ; CHECK: lwz
; PPC970: fctidz ; PPC970: fctidz
; PPC970: stfd ; PPC970: stfd
; PPC970: lwz ; PPC970: lwz
; SPE: efsctui
store i32 %conv, i32* %b.addr, align 4 store i32 %conv, i32* %b.addr, align 4
ret void ret void
} }
define void @fptoui_float_i64(float %a) nounwind { define void @fptoui_float_i64(float %a) nounwind {
entry: entry:
; CHECK: fptoui_float_i64 ; CHECK: fptoui_float_i64
; PPC970: fptoui_float_i64 ; PPC970: fptoui_float_i64
Show All 14 Lines; PPC970: fptoui_double_i32
%b.addr = alloca i32, align 8 %b.addr = alloca i32, align 8
%conv = fptoui double %a to i32 %conv = fptoui double %a to i32
; CHECK: fctiwuz ; CHECK: fctiwuz
; CHECK: stfd ; CHECK: stfd
; CHECK: lwz ; CHECK: lwz
; PPC970: fctidz ; PPC970: fctidz
; PPC970: stfd ; PPC970: stfd
; PPC970: lwz ; PPC970: lwz
; SPE: efdctui
store i32 %conv, i32* %b.addr, align 8 store i32 %conv, i32* %b.addr, align 8
ret void ret void
} }
define void @fptoui_double_i64(double %a) nounwind { define void @fptoui_double_i64(double %a) nounwind {
entry: entry:
; CHECK: fptoui_double_i64 ; CHECK: fptoui_double_i64
; PPC970: fptoui_double_i64 ; PPC970: fptoui_double_i64
Show All 9 Lines

test/CodeGen/PowerPC/fast-isel-load-store.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=spe -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=SPE
; This test verifies that load/store instructions are properly generated, ; This test verifies that load/store instructions are properly generated,
; and that they pass MI verification. ; and that they pass MI verification.
@a = global i8 1, align 1 @a = global i8 1, align 1
@b = global i16 2, align 2 @b = global i16 2, align 2
@c = global i32 4, align 4 @c = global i32 4, align 4
@d = global i64 8, align 8 @d = global i64 8, align 8
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; ELF64: ld ; ELF64: ld
%2 = add nsw i64 %1, 1 %2 = add nsw i64 %1, 1
; ELF64: addi ; ELF64: addi
ret i64 %2 ret i64 %2
} }
define float @t5() nounwind { define float @t5() nounwind {
; ELF64: t5 ; ELF64: t5
; SPE: t5
%1 = load float, float* @e, align 4 %1 = load float, float* @e, align 4
; ELF64: lfs ; ELF64: lfs
; SPE: lwz
%2 = fadd float %1, 1.0 %2 = fadd float %1, 1.0
; ELF64: fadds ; ELF64: fadds
; SPE: efsadd
ret float %2 ret float %2
} }
define double @t6() nounwind { define double @t6() nounwind {
; ELF64: t6 ; ELF64: t6
; SPE: t6
%1 = load double, double* @f, align 8 %1 = load double, double* @f, align 8
; ELF64: lfd ; ELF64: lfd
; SPE: evldd
%2 = fadd double %1, 1.0 %2 = fadd double %1, 1.0
; ELF64: fadd ; ELF64: fadd
; SPE: efdadd
ret double %2 ret double %2
} }
; store ; store
define void @t7(i8 %v) nounwind { define void @t7(i8 %v) nounwind {
; ELF64: t7 ; ELF64: t7
%1 = add nsw i8 %v, 1 %1 = add nsw i8 %v, 1
Show All 35 Lines
; ELF64: addi ; ELF64: addi
; ELF64: addi ; ELF64: addi
; ELF64: std ; ELF64: std
ret void ret void
} }
define void @t11(float %v) nounwind { define void @t11(float %v) nounwind {
; ELF64: t11 ; ELF64: t11
; SPE: t11
%1 = fadd float %v, 1.0 %1 = fadd float %v, 1.0
store float %1, float* @e, align 4 store float %1, float* @e, align 4
; ELF64: fadds ; ELF64: fadds
; ELF64: stfs ; ELF64: stfs
; SPE: efsadd
; SPE: stw
ret void ret void
} }
define void @t12(double %v) nounwind { define void @t12(double %v) nounwind {
; ELF64: t12 ; ELF64: t12
; SPE: t12
%1 = fadd double %v, 1.0 %1 = fadd double %v, 1.0
store double %1, double* @f, align 8 store double %1, double* @f, align 8
; ELF64: fadd ; ELF64: fadd
; ELF64: stfd ; ELF64: stfd
; SPE: efdadd
; SPE: evstdd
ret void ret void
} }
;; lwa requires an offset divisible by 4, so we need lwax here. ;; lwa requires an offset divisible by 4, so we need lwax here.
define i64 @t13() nounwind { define i64 @t13() nounwind {
; ELF64: t13 ; ELF64: t13
%1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1 %1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1
%2 = sext i32 %1 to i64 %2 = sext i32 %1 to i64
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/spe.ll

  • This file was added.
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+spe | FileCheck %s
declare float @llvm.fabs.float(float)
define float @test_float_abs(float %a) #0 {
entry:
%0 = tail call float @llvm.fabs.float(float %a)
ret float %0
; CHECK-LABEL: test_float_abs
; CHECK: efsabs 3, 3
; CHECK: blr
}
define float @test_fnabs(float %a) #0 {
entry:
%0 = tail call float @llvm.fabs.float(float %a)
%sub = fsub float -0.000000e+00, %0
ret float %sub
; CHECK-LABEL: @test_fnabs
; CHECK: efsnabs
; CHECK: blr
}
define float @test_fdiv(float %a, float %b) {
entry:
%v = fdiv float %a, %b
ret float %v
; CHECK-LABEL: test_fdiv
; CHECK: efsdiv
; CHECK: blr
}
define float @test_fmul(float %a, float %b) {
entry:
%v = fmul float %a, %b
ret float %v
; CHECK-LABEL @test_fmul
; CHECK: efsmul
; CHECK: blr
}
define float @test_fadd(float %a, float %b) {
entry:
%v = fadd float %a, %b
ret float %v
; CHECK-LABEL @test_fadd
; CHECK: efsadd
; CHECK: blr
}
define float @test_fsub(float %a, float %b) {
entry:
%v = fsub float %a, %b
ret float %v
; CHECK-LABEL @test_fsub
; CHECK: efssub
; CHECK: blr
}
define float @test_fneg(float %a) {
entry:
%v = fsub float -0.0, %a
ret float %v
; CHECK-LABEL @test_fneg
; CHECK: efsneg
; CHECK: blr
}
define float @test_dtos(double %a) {
entry:
%v = fptrunc double %a to float
ret float %v
; CHECK-LABEL: test_dtos
; CHECK: efscfd
; CHECK: blr
}
define i1 @test_fcmpgt(float %a, float %b) {
entry:
%r = fcmp ogt float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpgt
; CHECK: efscmpgt
; CHECK: blr
}
define i1 @test_fcmpugt(float %a, float %b) {
entry:
%r = fcmp ugt float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpugt
; CHECK: efscmpgt
; CHECK: blr
}
define i1 @test_fcmple(float %a, float %b) {
entry:
%r = fcmp ole float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmple
; CHECK: efscmpgt
; CHECK: blr
}
define i1 @test_fcmpule(float %a, float %b) {
entry:
%r = fcmp ule float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpule
; CHECK: efscmpgt
; CHECK: blr
}
define i1 @test_fcmpeq(float %a, float %b) {
entry:
%r = fcmp oeq float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpeq
; CHECK: efscmpeq
; CHECK: blr
}
; (un)ordered tests are expanded to une and oeq so verify
define i1 @test_fcmpuno(float %a, float %b) {
entry:
%r = fcmp uno float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpuno
; CHECK: efscmpeq
; CHECK: efscmpeq
; CHECK: crand
; CHECK: blr
}
define i1 @test_fcmpord(float %a, float %b) {
entry:
%r = fcmp ord float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpord
; CHECK: efscmpeq
; CHECK: efscmpeq
; CHECK: crnand
; CHECK: blr
}
define i1 @test_fcmpueq(float %a, float %b) {
entry:
%r = fcmp ueq float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpueq
; CHECK: efscmpeq
; CHECK: blr
}
define i1 @test_fcmpne(float %a, float %b) {
entry:
%r = fcmp one float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpne
; CHECK: efscmpeq
; CHECK: blr
}
define i1 @test_fcmpune(float %a, float %b) {
entry:
%r = fcmp une float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpune
; CHECK: efscmpeq
; CHECK: blr
}
define i1 @test_fcmplt(float %a, float %b) {
entry:
%r = fcmp olt float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmplt
; CHECK: efscmplt
; CHECK: blr
}
define i1 @test_fcmpult(float %a, float %b) {
entry:
%r = fcmp ult float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpult
; CHECK: efscmplt
; CHECK: blr
}
define i1 @test_fcmpge(float %a, float %b) {
entry:
%r = fcmp oge float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpge
; CHECK: efscmplt
; CHECK: blr
}
define i1 @test_fcmpuge(float %a, float %b) {
entry:
%r = fcmp uge float %a, %b
ret i1 %r
; CHECK-LABEL: test_fcmpuge
; CHECK: efscmplt
; CHECK: blr
}
define i32 @test_ftoui(float %a) {
%v = fptoui float %a to i32
ret i32 %v
; CHECK-LABEL: test_ftoui
; CHECK: efsctuiz
}
define i32 @test_ftosi(float %a) {
%v = fptosi float %a to i32
ret i32 %v
; CHECK-LABEL: test_ftosi
; CHECK: efsctsiz
}
define float @test_ffromui(i32 %a) {
%v = uitofp i32 %a to float
ret float %v
; CHECK-LABEL: test_ffromui
; CHECK: efscfui
}
define float @test_ffromsi(i32 %a) {
%v = sitofp i32 %a to float
ret float %v
; CHECK-LABEL: test_ffromsi
; CHECK: efscfsi
}
define i32 @test_fasmconst(float %x) {
entry:
%x.addr = alloca float, align 8
store float %x, float* %x.addr, align 8
%0 = load float, float* %x.addr, align 8
%1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
ret i32 %1
; CHECK-LABEL: test_fasmconst
; Check that it's not loading a double
; CHECK-NOT: evldd
; CHECK: #APP
; CHECK: efsctsi
; CHECK: #NO_APP
}
; Double tests
define void @test_double_abs(double * %aa) #0 {
entry:
%0 = load double, double * %aa
%1 = tail call double @llvm.fabs.f64(double %0) #2
store double %1, double * %aa
ret void
; CHECK-LABEL: test_double_abs
; CHECK: efdabs
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare double @llvm.fabs.f64(double) #1
define void @test_dnabs(double * %aa) #0 {
entry:
%0 = load double, double * %aa
%1 = tail call double @llvm.fabs.f64(double %0) #2
%sub = fsub double -0.000000e+00, %1
store double %sub, double * %aa
ret void
}
; CHECK-LABEL: @test_dnabs
; CHECK: efdnabs
; CHECK: blr
define double @test_ddiv(double %a, double %b) {
entry:
%v = fdiv double %a, %b
ret double %v
; CHECK-LABEL: test_ddiv
; CHECK: efddiv
; CHECK: blr
}
define double @test_dmul(double %a, double %b) {
entry:
%v = fmul double %a, %b
ret double %v
; CHECK-LABEL @test_dmul
; CHECK: efdmul
; CHECK: blr
}
define double @test_dadd(double %a, double %b) {
entry:
%v = fadd double %a, %b
ret double %v
; CHECK-LABEL @test_dadd
; CHECK: efdadd
; CHECK: blr
}
define double @test_dsub(double %a, double %b) {
entry:
%v = fsub double %a, %b
ret double %v
; CHECK-LABEL @test_dsub
; CHECK: efdsub
; CHECK: blr
}
define double @test_dneg(double %a) {
entry:
%v = fsub double -0.0, %a
ret double %v
; CHECK-LABEL @test_dneg
; CHECK: blr
}
define double @test_stod(float %a) {
entry:
%v = fpext float %a to double
ret double %v
; CHECK-LABEL: test_stod
; CHECK: efdcfs
; CHECK: blr
}
; (un)ordered tests are expanded to une and oeq so verify
define i1 @test_dcmpuno(double %a, double %b) {
entry:
%r = fcmp uno double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpuno
; CHECK: efdcmpeq
; CHECK: efdcmpeq
; CHECK: crand
; CHECK: blr
}
define i1 @test_dcmpord(double %a, double %b) {
entry:
%r = fcmp ord double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpord
; CHECK: efdcmpeq
; CHECK: efdcmpeq
; CHECK: crnand
; CHECK: blr
}
define i1 @test_dcmpgt(double %a, double %b) {
entry:
%r = fcmp ogt double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpgt
; CHECK: efdcmpgt
; CHECK: blr
}
define i1 @test_dcmpugt(double %a, double %b) {
entry:
%r = fcmp ugt double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpugt
; CHECK: efdcmpgt
; CHECK: blr
}
define i1 @test_dcmple(double %a, double %b) {
entry:
%r = fcmp ole double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmple
; CHECK: efdcmpgt
; CHECK: blr
}
define i1 @test_dcmpule(double %a, double %b) {
entry:
%r = fcmp ule double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpule
; CHECK: efdcmpgt
; CHECK: blr
}
define i1 @test_dcmpeq(double %a, double %b) {
entry:
%r = fcmp oeq double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpeq
; CHECK: efdcmpeq
; CHECK: blr
}
define i1 @test_dcmpueq(double %a, double %b) {
entry:
%r = fcmp ueq double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpueq
; CHECK: efdcmpeq
; CHECK: blr
}
define i1 @test_dcmpne(double %a, double %b) {
entry:
%r = fcmp one double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpne
; CHECK: efdcmpeq
; CHECK: blr
}
define i1 @test_dcmpune(double %a, double %b) {
entry:
%r = fcmp une double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpune
; CHECK: efdcmpeq
; CHECK: blr
}
define i1 @test_dcmplt(double %a, double %b) {
entry:
%r = fcmp olt double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmplt
; CHECK: efdcmplt
; CHECK: blr
}
define i1 @test_dcmpult(double %a, double %b) {
entry:
%r = fcmp ult double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpult
; CHECK: efdcmplt
; CHECK: blr
}
define i1 @test_dcmpge(double %a, double %b) {
entry:
%r = fcmp oge double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpge
; CHECK: efdcmplt
; CHECK: blr
}
define i1 @test_dcmpuge(double %a, double %b) {
entry:
%r = fcmp uge double %a, %b
ret i1 %r
; CHECK-LABEL: test_dcmpuge
; CHECK: efdcmplt
; CHECK: blr
}
define double @test_dselect(double %a, double %b, i1 %c) {
entry:
%r = select i1 %c, double %a, double %b
ret double %r
; CHECK-LABEL: test_dselect
; CHECK: andi.
; CHECK: bc
; CHECK: evldd
; CHECK: b
; CHECK: evldd
; CHECK: evstdd
; CHECK: blr
}
define i32 @test_dtoui(double %a) {
entry:
%v = fptoui double %a to i32
ret i32 %v
; CHECK-LABEL: test_dtoui
; CHECK: efdctuiz
}
define i32 @test_dtosi(double %a) {
entry:
%v = fptosi double %a to i32
ret i32 %v
; CHECK-LABEL: test_dtosi
; CHECK: efdctsiz
}
define double @test_dfromui(i32 %a) {
entry:
%v = uitofp i32 %a to double
ret double %v
; CHECK-LABEL: test_dfromui
; CHECK: efdcfui
}
define double @test_dfromsi(i32 %a) {
entry:
%v = sitofp i32 %a to double
ret double %v
; CHECK-LABEL: test_dfromsi
; CHECK: efdcfsi
}
define i32 @test_dasmconst(double %x) {
entry:
%x.addr = alloca double, align 8
store double %x, double* %x.addr, align 8
%0 = load double, double* %x.addr, align 8
%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
ret i32 %1
; CHECK-LABEL: test_dasmconst
; CHECK: evldd
; CHECK: #APP
; CHECK: efdctsi
; CHECK: #NO_APP
}
define double @test_spill(double %a) nounwind {
entry:
%0 = fadd double %a, %a
call void asm sideeffect "","~{r0},~{r3},~{s4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
%1 = fadd double %0, 3.14159
br label %return
return:
ret double %1
; CHECK-LABEL: test_spill
; CHECK: efdadd
; CHECK: evstdd
; CHECK: evldd
}