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Introduce codegen for the Signal Processing Engine

Description

Introduce codegen for the Signal Processing Engine

Summary:
The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,
e500v2, and several e200 cores. This adds support targeting the e500v2,
as this is more common than the e500v1, and is in SoCs still on the
market.

This patch is very intrusive because the SPE is binary incompatible with
the traditional FPU. After discussing with others, the cleanest
solution was to make both SPE and FPU features on top of a base PowerPC
subset, so all FPU instructions are now wrapped with HasFPU predicates.

Supported by this are:

  • Code generation following the SPE ABI at the LLVM IR level (calling

conventions)

  • Single- and Double-precision math at the level supported by the APU.

Still to do:

  • Vector operations
  • SPE intrinsics

As this changes the Callee-saved register list order, one test, which
tests the precise generated code, was updated to account for the new
register order.

Reviewed by: nemanjai
Differential Revision: https://reviews.llvm.org/D44830

Details

Committed
jhibbitsJul 17 2018, 9:25 PM
Reviewer
nemanjai
Differential Revision
D44830: Introduce codegen for the Signal Processing Engine
Parents
rL337346: Complete the SPE instruction set patterns
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