[ARM] Add 'fillValidCPUArchList' to ARM targets

[erichkeane]

Summary

This is a support change for a CFE change (https://reviews.llvm.org/D42978)
that allows march and -target-cpu to list the valid targets in a note. The changes
are limited to the ARM/AArch64, since this is the only target that gets the CPU
list from LLVM.

[samparker]

lib/Support/TargetParser.cpp

692

Could you not just copy the values from CPUNames and AArch64CPUNames?

[fhahn]

Thanks for the patch, I think this would be a nice UI improvement. I agree with Sam, please use CPUNames and AArch64CPUNames. Also there are unit tests for the target parser in unittests/Support/TargetParserTest.cpp. Could you add some for the new functions?

[erichkeane]

Changed to using the CPUNames lists.

[erichkeane]

Just realized I forgot the unittest, i'll toss a couple in, sorry about that!

[erichkeane]

Added tests as requested. Should cover all current comments.

[samparker]

Thanks. LGTM to me with two small nits.

lib/Support/TargetParser.cpp

702

CpuNames has the getName helper for just this.

unittests/Support/TargetParserTest.cpp

285

Why create a SmallVector with fewer elements than you know will be required?

include/llvm/Support/TargetParser.h

 StringRef getDefaultCPU(StringRef Arch);
 
 // Parser
 unsigned parseHWDiv(StringRef HWDiv);
 unsigned parseFPU(StringRef FPU);
 ArchKind parseArch(StringRef Arch);
 unsigned parseArchExt(StringRef ArchExt);
 ArchKind parseCPUArch(StringRef CPU);
+void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
 ISAKind parseArchISA(StringRef Arch);
 EndianKind parseArchEndian(StringRef Arch);
 ProfileKind parseArchProfile(StringRef Arch);
 unsigned parseArchVersion(StringRef Arch);
 
 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
 
 } // namespace ARM

 unsigned  getDefaultExtensions(StringRef CPU, ArchKind AK);
 StringRef getDefaultCPU(StringRef Arch);
 
 // Parser
 unsigned parseFPU(StringRef FPU);
 AArch64::ArchKind parseArch(StringRef Arch);
 ArchExtKind parseArchExt(StringRef ArchExt);
 ArchKind parseCPUArch(StringRef CPU);
+void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
 ARM::ISAKind parseArchISA(StringRef Arch);
 ARM::EndianKind parseArchEndian(StringRef Arch);
 ARM::ProfileKind parseArchProfile(StringRef Arch);
 unsigned parseArchVersion(StringRef Arch);
 
 } // namespace AArch64
 
 namespace X86 {

lib/Support/TargetParser.cpp

 ARM::ArchKind llvm::ARM::parseCPUArch(StringRef CPU) {
   for (const auto C : CPUNames) {
     if (CPU == C.getName())
       return C.ArchID;
   }
   return ARM::ArchKind::INVALID;
 }
 
+void llvm::ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
+  for (const CpuNames<ARM::ArchKind> &Arch : CPUNames) {
+    if (Arch.ArchID != ARM::ArchKind::INVALID)
+      Values.emplace_back(Arch.NameCStr, Arch.NameLength);
+  }
+}
+
+void llvm::AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
+  for (const CpuNames<AArch64::ArchKind> &Arch : AArch64CPUNames) {
+    if (Arch.ArchID != AArch64::ArchKind::INVALID)
+      Values.emplace_back(Arch.NameCStr, Arch.NameLength);
+  }
+}
+
 // ARM, Thumb, AArch64
 ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
   return StringSwitch<ARM::ISAKind>(Arch)
       .StartsWith("aarch64", ARM::ISAKind::AARCH64)
       .StartsWith("arm64", ARM::ISAKind::AARCH64)
       .StartsWith("thumb", ARM::ISAKind::THUMB)
       .StartsWith("arm", ARM::ISAKind::ARM)
       .Default(ARM::ISAKind::INVALID);

unittests/Support/TargetParserTest.cpp

EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
                          ARM::AEK_NONE, "iwmmxt"));
   EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
                          ARM::AEK_NONE, "xscale"));
   EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                          "7-S"));
 }
 
+static const int NumARMCPUArchs = 82;
+
+TEST(TargetParserTest, testARMCPUArchList) {
+  SmallVector<StringRef, 32> List;
+  ARM::fillValidCPUArchList(List);
+
+  // No list exists for these in this test suite, so ensure all are
+  // valid, and match the expected 'magic' count.
+  EXPECT_EQ(List.size(), NumARMCPUArchs);
+  for(StringRef CPU : List) {
+    EXPECT_NE(ARM::parseCPUArch(CPU), ARM::ArchKind::INVALID);
+  }
+}
+
 TEST(TargetParserTest, testInvalidARMArch) {
   auto InvalidArchStrings = {"armv", "armv99", "noarm"};
   for (const char* InvalidArch : InvalidArchStrings)
     EXPECT_EQ(ARM::parseArch(InvalidArch), ARM::ArchKind::INVALID);
 }
 
 bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
                  unsigned ArchAttr) {
EXPECT_TRUE(testAArch64CPU(
       "8-A"));
   EXPECT_TRUE(testAArch64CPU(
       "thunderxt88", "armv8-a", "crypto-neon-fp-armv8",
       AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
       AArch64::AEK_FP | AArch64::AEK_PROFILE,
       "8-A"));
 }
 
+static const int NumAArch64CPUArchs = 19;
+
+TEST(TargetParserTest, testAArch64CPUArchList) {
+  SmallVector<StringRef, 32> List;
+  AArch64::fillValidCPUArchList(List);
+
+  // No list exists for these in this test suite, so ensure all are
+  // valid, and match the expected 'magic' count.
+  EXPECT_EQ(List.size(), NumAArch64CPUArchs);
+  for(StringRef CPU : List) {
+    EXPECT_NE(AArch64::parseCPUArch(CPU), AArch64::ArchKind::INVALID);
+  }
+}
+
 bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
                      unsigned ArchAttr) {
   AArch64::ArchKind AK = AArch64::parseArch(Arch);
   return (AK != AArch64::ArchKind::INVALID) &
          AArch64::getDefaultCPU(Arch).equals(DefaultCPU) &
          AArch64::getSubArch(AK).equals(SubArch) &
          (AArch64::getArchAttr(AK) == ArchAttr);
 }