[AArch64][SVE] Asm: Add AND_ZI instructions and aliases

[sdesmalen]

Summary

Adds support for the SVE AND instruction with vector and logical-immediate operands, and their corresponding aliases.

[fhahn]

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1666

Is this exactly the same as above?

lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h

769

I think the logic here could be made slightly clearer using std::all_of

[sdesmalen]

• Use 'all_of' instead of a loop to check that all elements in an array are the same.

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1666

The same (tied) operand is added twice to the instruction, see line 470.

[fhahn]

LGTM

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1666

Ah thanks. That might be worth a comment.

lib/Target/AArch64/AArch64SVEInstrInfo.td

 // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE] in {
   defm ADD_ZZZ   : sve_int_bin_cons_arit_0<0b000, "add">;
   defm SUB_ZZZ   : sve_int_bin_cons_arit_0<0b001, "sub">;
 
+  defm AND_ZI    : sve_int_log_imm<0b10, "and", "bic">;
+
   defm ADD_ZPmZ  : sve_int_bin_pred_arit_0<0b000, "add">;
   defm SUB_ZPmZ  : sve_int_bin_pred_arit_0<0b001, "sub">;
 
   defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
   defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
 
   defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
   defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
 
   defm DUP_ZR  : sve_int_perm_dup_r<"dup">;
 }

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
                                                       unsigned RegNo,
                                                       uint64_t Addr,
                                                       const void *Decoder);
 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
                                                       unsigned RegNo,
                                                       uint64_t Addr,
                                                       const void *Decoder);
+static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
+                                                   uint32_t insn,
+                                                   uint64_t Address,
+                                                   const void *Decoder);
 template<int Bits>
 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
                                uint64_t Address, const void *Decoder);
 
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
     case MCDisassembler::Success:
       // Out stays the same.
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
                                                       unsigned RegNo,
                                                       uint64_t Addr,
                                                       const void *Decoder) {
   return DecodeGPRSeqPairsClassRegisterClass(Inst,
                                              AArch64::XSeqPairsClassRegClassID,
                                              RegNo, Addr, Decoder);
 }
 
+static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
+                                                   uint32_t insn,
+                                                   uint64_t Addr,
+                                                   const void *Decoder) {
+  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
+  unsigned imm = fieldFromInstruction(insn, 5, 13);
+  if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
+    return Fail;
+
+  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
+  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
+  Inst.addOperand(MCOperand::createImm(imm));
+  return Success;
+}
+
 template<int Bits>
 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
                                uint64_t Address, const void *Decoder) {
   if (Imm & ~((1LL << Bits) - 1))
       return Fail;
 
   // Imm is a signed immediate, so sign extend it.
   if (Imm & (1 << (Bits - 1)))
     Imm |= ~((1LL << Bits) - 1);
 
   Inst.addOperand(MCOperand::createImm(Imm));
   return Success;
 }
 

lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h

static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
   if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
   if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
   if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
   if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
   if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
   return (EncVal << 32) | EncVal;
 }
 
+/// Returns true if Imm is the concatenation of a repeating pattern of type T.
+template <typename T>
+static inline bool isSVEMaskOfIdenticalElements(int64_t Imm) {
+  union {
+    int64_t Whole;
+    T Parts[sizeof(int64_t)/sizeof(T)];
+  } Vec { Imm };
+
+  return all_of(Vec.Parts, [Vec](T Elem) { return Elem == Vec.Parts[0]; });
+}
+
 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) {
   for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
     if ((Value & ~(0xffffULL << Shift)) == 0)
       return true;
 
   return false;
 }
 
 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) {
   if (RegWidth == 32)

lib/Target/AArch64/SVEInstrFormats.td

 //=-- SVEInstrFormats.td -  AArch64 SVE Instruction classes -*- tablegen -*--=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
 //
 //===----------------------------------------------------------------------===//
 
+class SVELogicalImmOperand<int Width> : AsmOperandClass {
+  let Name = "SVELogicalImm" # Width;
+  let DiagnosticType = "LogicalSecondSource";
+  let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
+  let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
+}
+
+def sve_logical_imm8 : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmOperand<8>;
+  let PrintMethod = "printLogicalImm<int8_t>";
+
+  let MCOperandPredicate = [{
+    if (!MCOp.isImm())
+      return false;
+    int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
+    return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
+  }];
+}
+
+def sve_logical_imm16 : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmOperand<16>;
+  let PrintMethod = "printLogicalImm<int16_t>";
+
+  let MCOperandPredicate = [{
+    if (!MCOp.isImm())
+      return false;
+    int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
+    return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
+  }];
+}
+
+def sve_logical_imm32 : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmOperand<32>;
+  let PrintMethod = "printLogicalImm<int32_t>";
+
+  let MCOperandPredicate = [{
+    if (!MCOp.isImm())
+      return false;
+    int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
+    return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+class SVELogicalImmNotOperand<int Width> : AsmOperandClass {
+  let Name = "SVELogicalImm" # Width # "Not";
+  let DiagnosticType = "LogicalSecondSource";
+  let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
+  let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>";
+}
+
+def sve_logical_imm8_not : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmNotOperand<8>;
+}
+
+def sve_logical_imm16_not : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmNotOperand<16>;
+}
+
+def sve_logical_imm32_not : Operand<i64> {
+  let ParserMatchClass = SVELogicalImmNotOperand<32>;
+}
+
 //===----------------------------------------------------------------------===//
 // SVE Permute - Cross Lane Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
                          RegisterClass srcRegType>
 : I<(outs zprty:$Zd), (ins srcRegType:$Rn),
   asm, "\t$Zd, $Rn",
def : InstAlias<"mov $Zd, $Rn",
                   (!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Rn",
                   (!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Rn",
                   (!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
 }
 
 //===----------------------------------------------------------------------===//
+// SVE Logical Mask Immediate Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_log_imm<bits<2> opc, string asm>
+: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
+  asm, "\t$Zdn, $_Zdn, $imms13",
+  "", []>, Sched<[]> {
+  bits<5> Zdn;
+  bits<13> imms13;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = opc;
+  let Inst{21-18} = 0b0000;
+  let Inst{17-5}  = imms13;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+  let DecoderMethod = "DecodeSVELogicalImmInstruction";
+}
+
+multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
+  def NAME : sve_int_log_imm<opc, asm>;
+
+  def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
+  def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>;
+  def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>;
+
+  def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>;
+  def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>;
+  def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>;
+  def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
+                  (!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>;
+}
+
+//===----------------------------------------------------------------------===//
 // SVE Integer Arithmetic -  Unpredicated Group.
 //===----------------------------------------------------------------------===//
 
 class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
                               ZPRRegOp zprty>
 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
   asm, "\t$Zd, $Zn, $Zm",
   "", []>, Sched<[]> {
: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
   let Inst{3-0}   = Pd;
 }
 
 multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
   def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
   def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
   def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
   def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
-}
+}
 

test/MC/AArch64/SVE/and-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+and z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+and z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: and z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+and z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: and z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: bic z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/and.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+and     z5.b, z5.b, #0xf9
+// CHECK-INST: and     z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
+
+bic     z5.b, z5.b, #0x06
+// CHECK-INST: and     z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
+
+and     z23.h, z23.h, #0xfff9
+// CHECK-INST: and     z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
+
+bic     z23.h, z23.h, #0x0006
+// CHECK-INST: and     z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
+
+and     z0.s, z0.s, #0xfffffff9
+// CHECK-INST: and     z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
+
+bic     z0.s, z0.s, #0x00000006
+// CHECK-INST: and     z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
+
+and     z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: and     z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+
+bic     z0.d, z0.d, #0x0000000000000006
+// CHECK-INST: and     z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 83 05 <unknown>