[RISCV] Initial Machine Scheduler

[xiangzhai]

Summary

Hi LLVM developers,

Motivation:

I am reviewing Compiler Principle about ILP and learning Slides about Machine Scheduler.

So I just initial Machine scheduling model for RISCV Target, but I have no idea where to find scheduling information derived from "Which RV32 or RV64 Technical Reference Manual".

And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf what about PULP? is it in-order or out-of-order?

Please give me some directions, thanks a lot!

PS: I will rebase this patch based on D41700 and D41653 for porting GlobalISel to RISCV Target.

Regards,
Leslie Zhai

[javed.absar]

lib/Target/RISCV/RISCVSchedule.td

18

These definitions may be ok for a start, but you would need to decide what best fits your purpose (maybe fewer SchedWriteTypes to begin with ?)

lib/Target/RISCV/RISCVScheduleGRV32.td

25

Why not ProcResource?

[xiangzhai]

lib/Target/RISCV/RISCVScheduleGRV32.td

25

Hi Javed,

Thanks for your review and great tutorial about Writing Great Machine Schedulers !

As my comment FIXME mentioned:

I have no idea how to find scheduling information, perhaps some RV32 Technical Reference Manual provided?

So I am reading gcc riscv Target's Generic DFA-based pipeline without manual, it is like AVR Target migate to LLD, there is no ABI manual either, so I have to borrow code from binutils in D37615 .

I want to learn and practice, please leading me, thanks a lot!

Regards,
Leslie Zhai

[xiangzhai]

lib/Target/RISCV/RISCVSchedule.td

18

My sincere thanks still need to goto you for reviewing D39712 even it is not LGTM :)

[asb]

Leslie - there's a huge amount here that's copied and pasted from ARMScheduleA9.td, much of it really isn't relevant to any current RISC-V implementation, such as load-multiple/store-multiple and vector operations. Additionally, the A9 is an out-of-order superscalar core. The majority of the RISC-V community are targeting in-order cores (Rocket, PULP, other microcontroller class cores). If you're keen to explore scheduling models for out-of-order cores then BOOM is of course the obvious target.

This patch is intermingled with other changes that you have for review (e.g. calling convention implementation changes, globalisel) - it's always best to post a diff that only contains the changes needed for this particular review.

What you've done here is a good start for getting a better understanding of how machine scheduling works. What I think you need to do now is figure out what sort of scheduling model you want to write (e.g. for the default configuration of Rocket), and how you can write tests that demonstrate the model is doing what it is meant to do, then you can try to produce something that's a little more minimal than what you have here. I don't have enough experience with LLVM scheduling models to predict how much there might be to gain for a pipeline as simple as Rocket. It's single-issue in-order, but does have a non-blocking L1 cache which allows the pipeline to continue under a cache miss until there is a dependency on the result.

[xiangzhai]

Hi Alex,

Thanks for your response! Sorry that I borrow code from ARMScheduleA9.td which is of course not suitable for RISCV Target, and I only find some product introduction PDFs:

And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf

But where could I find the scheduling information providing "RV32 or RV64 Technical Reference Manual"? I am reading GCC riscv Target Generic DFA-based pipeline but its comment indicated that:

Based on MIPS target for GNU compiler.

So perhaps I can "migrate" GCC pipeline to LLVM by reading GCC source code, if there is no manual?

Regards,
Leslie Zhai

lib/Target/RISCV/RISCV.td

 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<"Feature64Bit">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<"!Feature64Bit">;
 
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;
 
+// Use the MachineScheduler for instruction scheduling for the subtarget.
+def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
+                                        "Use the MachineScheduler">;
+
+// Pre-RA -> RA -> Post-RA
+def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
+    "DisablePostRAScheduler", "false",
+    "Why not schedule again after register allocation?">;
+
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.
 //===----------------------------------------------------------------------===//
 
 include "RISCVRegisterInfo.td"
+include "RISCVRegisterBanks.td"
 include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 
+
+//===----------------------------------------------------------------------===//
+// RISCV schedules.
+//===----------------------------------------------------------------------===//
+//
+include "RISCVSchedule.td"
+
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
+def : ProcessorModel<"generic-rv32", GRV32Model, [FeatureUseMISched,
+                                                  FeatureNoPostRASched]>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {

lib/Target/RISCV/RISCVISelLowering.h

 // selection DAG.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 
 #include "RISCV.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
 class RISCVSubtarget;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
public:
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
+  CCAssignFn *CCAssignFnForCall(const DataLayout &DL, bool IsFixed = false,
+                                Type *OrigTy = nullptr) const;
+  CCAssignFn *CCAssignFnForReturn(const DataLayout &DL, bool IsFixed = false,
+                                  Type *OrigTy = nullptr) const;
+
+  Sched::Preference getSchedulingPreference(SDNode *N) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
                         bool IsRet) const;
   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
                          const SmallVectorImpl<ISD::OutputArg> &Outs,
                          bool IsRet, CallLoweringInfo *CLI) const;
   // Lower incoming arguments, copy physregs into vregs

lib/Target/RISCV/RISCVISelLowering.cpp

if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
     State.addLoc(CCValAssign::getMem(
         ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
         CCValAssign::Full));
   }
 
   return false;
 }
 
-// Implements the RISC-V calling convention. Returns true upon failure.
-static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
-                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
-                     CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
-  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
-  assert(XLen == 32 || XLen == 64);
-  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
-  assert(ValVT == XLenVT && "Unexpected ValVT");
-  assert(LocVT == XLenVT && "Unexpected LocVT");
-
-  // Any return value split in to more than two values can't be returned
-  // directly.
-  if (IsRet && ValNo > 1)
-    return true;
+static bool CC_RISCVFn(unsigned XLen, MVT XLenVT, unsigned ValNo, MVT ValVT,
+                       MVT LocVT, CCValAssign::LocInfo LocInfo,
+                       ISD::ArgFlagsTy ArgFlags, CCState &State,
+                       bool IsFixed = false, Type *OrigTy = nullptr) {
+  const DataLayout &DL = State.getMachineFunction().getDataLayout();
 
   // If this is a variadic argument, the RISC-V calling convention requires
   // that it is assigned an 'even' or 'aligned' register if it has 8-byte
   // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
   // be used regardless of whether the original argument was split during
   // legalisation or not. The argument will not be passed by registers if the
   // original type is larger than 2*XLEN, so the register alignment rule does
   // not apply.
if (Reg) {
     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
   } else {
     State.addLoc(
         CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
   }
   return false;
 }
 
+static bool CC_RISCV32Fn(unsigned ValNo, MVT ValVT, MVT LocVT,
+                         CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+                         CCState &State) {
+  unsigned XLen = 32;
+  MVT XLenVT = MVT::i32;
+
+  return CC_RISCVFn(XLen, XLenVT, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
+                    State);
+}
+
+static bool CC_RISCV64Fn(unsigned ValNo, MVT ValVT, MVT LocVT,
+                         CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+                         CCState &State) {
+  unsigned XLen = 64;
+  MVT XLenVT = MVT::i64;
+
+  return CC_RISCVFn(XLen, XLenVT, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
+                    State);
+}
+
+static bool RetCC_RISCV32Fn(unsigned ValNo, MVT ValVT, MVT LocVT,
+                          CCValAssign::LocInfo LocInfo,
+                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
+  unsigned XLen = 32;
+  MVT XLenVT = MVT::i32;
+
+  if (ValNo > 1)
+    return true;
+
+  return CC_RISCVFn(XLen, XLenVT, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
+                    State);
+}
+
+static bool RetCC_RISCV64Fn(unsigned ValNo, MVT ValVT, MVT LocVT,
+                          CCValAssign::LocInfo LocInfo,
+                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
+  unsigned XLen = 64;
+  MVT XLenVT = MVT::i64;
+
+  if (ValNo > 1)
+    return true;
+
+  return CC_RISCVFn(XLen, XLenVT, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
+                    State);
+}
+
+CCAssignFn *RISCVTargetLowering::CCAssignFnForCall(const DataLayout &DL,
+                                                   bool IsFixed,
+                                                   Type *OrigTy) const {
+  assert(IsFixed && "IsFixed support not yet implemented");
+  assert(OrigTy && "OrigTy support not yet implemented");
+  if (DL.getLargestLegalIntTypeSizeInBits() == 32)
+    return CC_RISCV32Fn;
+
+  return CC_RISCV64Fn;
+}
+
+CCAssignFn *RISCVTargetLowering::CCAssignFnForReturn(const DataLayout &DL,
+                                                     bool IsFixed,
+                                                     Type *OrigTy) const {
+  assert(IsFixed && "IsFixed support not yet implemented");
+  assert(OrigTy && "OrigTy support not yet implemented");
+  if (DL.getLargestLegalIntTypeSizeInBits() == 32)
+    return RetCC_RISCV32Fn;
+
+  return RetCC_RISCV64Fn;
+}
+
+// Implements the RISC-V calling convention. Returns true upon failure.
+static bool CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
+                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+                     CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
+  const DataLayout &DL = State.getMachineFunction().getDataLayout();
+  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
+  assert(XLen == 32 || XLen == 64);
+  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
+  assert(ValVT == XLenVT && "Unexpected ValVT");
+  assert(LocVT == XLenVT && "Unexpected LocVT");
+
+  // Any return value split in to more than two values can't be returned
+  // directly.
+  if (IsRet && ValNo > 1)
+    return true;
+
+  return CC_RISCVFn(XLen, XLenVT, ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
+                    IsFixed, OrigTy);
+}
+
 void RISCVTargetLowering::analyzeInputArgs(
     MachineFunction &MF, CCState &CCInfo,
     const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
   unsigned NumArgs = Ins.size();
   FunctionType *FType = MF.getFunction().getFunctionType();
 
   for (unsigned i = 0; i != NumArgs; ++i) {
     MVT ArgVT = Ins[i].VT;
     ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
 
     Type *ArgTy = nullptr;
     if (IsRet)
       ArgTy = FType->getReturnType();
     else if (Ins[i].isOrigArg())
       ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
 
-    if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
-                 ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
+    if (CC_RISCV(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+                 /*IsFixed=*/true, IsRet, ArgTy)) {
       DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
                    << EVT(ArgVT).getEVTString() << '\n');
       llvm_unreachable(nullptr);
     }
   }
 }
 
 void RISCVTargetLowering::analyzeOutputArgs(
     MachineFunction &MF, CCState &CCInfo,
     const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
     CallLoweringInfo *CLI) const {
   unsigned NumArgs = Outs.size();
 
   for (unsigned i = 0; i != NumArgs; i++) {
     MVT ArgVT = Outs[i].VT;
     ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
     Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
 
-    if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
-                 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
+    if (CC_RISCV(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+                 Outs[i].IsFixed, IsRet, OrigTy)) {
       DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
                    << EVT(ArgVT).getEVTString() << "\n");
       llvm_unreachable(nullptr);
     }
   }
 }
 
 // The caller is responsible for loading the full value if the argument is

 bool RISCVTargetLowering::CanLowerReturn(
     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
     MVT VT = Outs[i].VT;
     ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
-    if (CC_RISCV(MF.getDataLayout(), i, VT, VT, CCValAssign::Full, ArgFlags,
-                 CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
+    if (CC_RISCV(i, VT, VT, CCValAssign::Full, ArgFlags, CCInfo,
+                 /*IsFixed=*/true, /*IsRet=*/true, nullptr))
       return false;
   }
   return true;
 }
 
 SDValue
 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,
case 'r':
       return std::make_pair(0U, &RISCV::GPRRegClass);
     default:
       break;
     }
   }
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
+
+Sched::Preference RISCVTargetLowering::getSchedulingPreference(
+        SDNode *N) const {
+  unsigned NumVals = N->getNumValues();
+  if (!NumVals)
+    return Sched::RegPressure;
+
+  for (unsigned i = 0; i != NumVals; ++i) {
+    EVT VT = N->getValueType(i);
+    if (VT == MVT::Glue || VT == MVT::Other)
+      continue;
+    if (VT.isFloatingPoint() || VT.isVector())
+      return Sched::ILP;
+  }
+
+  if (!N->isMachineOpcode())
+    return Sched::RegPressure;
+
+  // Load are scheduled for latency even if there instruction itinerary
+  // is not available.
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
+
+  if (MCID.getNumDefs() == 0)
+    return Sched::RegPressure;
+
+  return Sched::RegPressure;
+}

lib/Target/RISCV/RISCVSchedule.td

+//===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Sched definitions for integer pipeline instructions
+//
+// Basic ALU operation.
+def WriteALU : SchedWrite;
+def ReadALU : SchedRead;
+
+// Basic ALU with shifts.
+def WriteALUsi : SchedWrite; // Shift by immediate.
+def WriteALUsr : SchedWrite; // Shift by register.
+def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
+def ReadALUsr : SchedRead; // Some operands are read later.
+
+// Compares.
+def WriteCMP : SchedWrite;
+def WriteCMPsi : SchedWrite;
+def WriteCMPsr : SchedWrite;
+
+// Multiplys.
+def WriteMUL16   : SchedWrite; // 16-bit multiply.
+def WriteMUL32   : SchedWrite; // 32-bit multiply.
+def WriteMUL64Lo : SchedWrite; // 64-bit result. Low reg.
+def WriteMUL64Hi : SchedWrite; // 64-bit result. High reg.
+def ReadMUL  : SchedRead;
+
+// Multiply-accumulates.
+def WriteMAC16   : SchedWrite; // 16-bit mac.
+def WriteMAC32   : SchedWrite; // 32-bit mac.
+def WriteMAC64Lo : SchedWrite; // 64-bit mac. Low reg.
+def WriteMAC64Hi : SchedWrite; // 64-bit mac. High reg.
+def ReadMAC : SchedRead;
+
+// Divisions.
+def WriteDIV : SchedWrite;
+
+// Loads/Stores.
+def WriteLd : SchedWrite;
+def WritePreLd : SchedWrite;
+def WriteST : SchedWrite;
+
+// Branches.
+def WriteBr : SchedWrite;
+def WriteBrL : SchedWrite;
+def WriteBrTbl : SchedWrite;
+
+// Noop.
+def WriteNoop : SchedWrite;
+
+//===----------------------------------------------------------------------===//
+// Sched definitions for floating-point and neon instructions
+//
+// Floating point conversions
+def WriteFPCVT : SchedWrite;
+def WriteFPMOV : SchedWrite; // FP -> GPR and vice-versa
+
+// ALU operations (32/64-bit)
+def WriteFPALU32 : SchedWrite;
+def WriteFPALU64 : SchedWrite;
+
+// Multiplication
+def WriteFPMUL32 : SchedWrite;
+def WriteFPMUL64 : SchedWrite;
+def ReadFPMUL    : SchedRead; // multiplier read
+def ReadFPMAC    : SchedRead; // accumulator read
+
+// Multiply-accumulate
+def WriteFPMAC32 : SchedWrite;
+def WriteFPMAC64 : SchedWrite;
+
+// Division
+def WriteFPDIV32 : SchedWrite;
+def WriteFPDIV64 : SchedWrite;
+
+// Square-root
+def WriteFPSQRT32 : SchedWrite;
+def WriteFPSQRT64 : SchedWrite;
+
+// Vector load and stores
+def WriteVLD1 : SchedWrite;
+def WriteVST1 : SchedWrite;
+
+//===----------------------------------------------------------------------===//
+// Processor instruction itineraries.
+
+include "RISCVScheduleGRV32.td"

lib/Target/RISCV/RISCVScheduleGRV32.td

+//=- RISCVScheduleGRV32.td - RISCV Generic RV32 Scheduling ---*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the itinerary class data for the RISCV Generice RV32
+// processors.
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// This section contains legacy support for itineraries. This is
+// required until SD and PostRA schedulers are replaced by MachineScheduler.
+
+//
+// FIXME: Where can find scheduling information derived from "WHICH RV32
+// Technical Reference Manual"? only reviewed Compiler Principle's ILP is not
+// enough!
+//
+// Functional units
+def GRV32_Issue0  : FuncUnit; // Issue 0
+def GRV32_Issue1  : FuncUnit; // Issue 1
+def GRV32_Branch  : FuncUnit; // Branch
+def GRV32_ALU0    : FuncUnit; // ALU / MUL pipeline 0
+def GRV32_ALU1    : FuncUnit; // ALU pipeline 1
+def GRV32_AGU     : FuncUnit; // Address generation unit for ld / st
+def GRV32_WPipe   : FuncUnit; // WHICH pipeline
+def GRV32_DRegsVFP: FuncUnit; // FP register set, VFP side
+
+// Bypasses
+def GRV32_LdBypass : Bypass;
+
+def GRV32Itineraries : ProcessorItineraries<
+  [GRV32_Issue0, GRV32_Issue1, GRV32_Branch, GRV32_ALU0, GRV32_ALU1, GRV32_AGU,
+   GRV32_WPipe, GRV32_DRegsVFP],
+  [GRV32_LdBypass], [
+]>;
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the simpler per-operand machine model.
+// This works with MachineScheduler and will eventually replace itineraries.
+
+class GRV32WriteLMOpsListType<list<WriteSequence> writes> {
+  list <WriteSequence> Writes = writes;
+  SchedMachineModel SchedModel = ?;
+}
+
+// Generice RV32 machine model for scheduling and other instruction cost heuristics.
+def GRV32Model : SchedMachineModel {
+  let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
+  let MicroOpBufferSize = 56; // Based on available renamed registers.
+  let LoadLatency = 2; // Optimistic load latency assuming bypass.
+                       // This is overriden by OperandCycles if the
+                       // Itineraries are queried instead.
+  let MispredictPenalty = 8; // Based on estimate of pipeline depth.
+
+  let Itineraries = GRV32Itineraries;
+
+  // FIXME: Many vector operations were never given an itinerary. We
+  // haven't mapped these to the new model either.
+  let CompleteModel = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available.
+//
+// The AGU unit has BufferSize=1 so that the latency between operations
+// that use it are considered to stall other operations.
+//
+// The FP unit has BufferSize=0 so that it is a hard dispatch
+// hazard. No instruction may be dispatched while the unit is reserved.
+
+let SchedModel = GRV32Model in {
+
+def GRV32UnitALU : ProcResource<2>;
+def GRV32UnitMul : ProcResource<1> { let Super = GRV32UnitALU; }
+def GRV32UnitAGU : ProcResource<1> { let BufferSize = 1; }
+def GRV32UnitLS  : ProcResource<1>;
+def GRV32UnitFP  : ProcResource<1> { let BufferSize = 0; }
+def GRV32UnitB   : ProcResource<1>;
+
+//===----------------------------------------------------------------------===//
+// Define scheduler read/write types with their resources and latency on GRV32.
+
+// Consume an issue slot, but no processor resources. This is useful when all
+// other writes associated with the operand have NumMicroOps = 0.
+def GRV32WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
+
+// Write an integer register.
+def GRV32WriteI : SchedWriteRes<[GRV32UnitALU]>;
+// Write an integer shifted-by register
+def GRV32WriteIsr : SchedWriteRes<[GRV32UnitALU]> { let Latency = 2; }
+
+// Basic ALU.
+def GRV32WriteALU : SchedWriteRes<[GRV32UnitALU]>;
+// ALU with operand shifted by immediate.
+def : WriteRes<WriteALUsi, [GRV32UnitALU]> { let Latency = 2; }
+// ALU with operand shifted by register.
+def GRV32WriteALUsr : SchedWriteRes<[GRV32UnitALU]> { let Latency = 3; }
+
+// Multiplication
+def GRV32WriteM   : SchedWriteRes<[GRV32UnitMul, GRV32UnitMul]> { let Latency = 4; }
+def GRV32WriteMHi : SchedWriteRes<[GRV32UnitMul]> { let Latency = 5;
+                                              let NumMicroOps = 0; }
+def GRV32WriteM16   : SchedWriteRes<[GRV32UnitMul]> { let Latency = 3; }
+def GRV32WriteM16Hi : SchedWriteRes<[GRV32UnitMul]> { let Latency = 4;
+                                                let NumMicroOps = 0; }
+def : SchedAlias<WriteMUL16, GRV32WriteM16>;
+def : SchedAlias<WriteMUL32, GRV32WriteM>;
+def : SchedAlias<WriteMUL64Lo, GRV32WriteM>;
+def : SchedAlias<WriteMUL64Hi, GRV32WriteMHi>;
+def : SchedAlias<WriteMAC16, GRV32WriteM16>;
+def : SchedAlias<WriteMAC32, GRV32WriteM>;
+def : SchedAlias<WriteMAC64Lo, GRV32WriteM>;
+def : SchedAlias<WriteMAC64Hi, GRV32WriteMHi>;
+def : ReadAdvance<ReadMUL, 0>;
+def : ReadAdvance<ReadMAC, 0>;
+
+// Floating-point
+// Only one FP or AGU instruction may issue per cycle. We model this
+// by having FP instructions consume the AGU resource.
+def GRV32WriteF      : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 4; }
+def GRV32WriteFMov   : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 1; }
+def GRV32WriteFMulS  : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 5; }
+def GRV32WriteFMulD  : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 6; }
+def GRV32WriteFMAS   : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 8; }
+
+def GRV32WriteFMAD   : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 9; }
+def GRV32WriteFDivS  : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 15; }
+def GRV32WriteFDivD  : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 25; }
+def GRV32WriteFSqrtS : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 17; }
+def GRV32WriteFSqrtD : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 32; }
+
+// NEON has an odd mix of latencies. Simply name the write types by latency.
+def GRV32WriteV1 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 1; }
+def GRV32WriteV2 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 2; }
+def GRV32WriteV3 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 3; }
+def GRV32WriteV4 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 4; }
+def GRV32WriteV5 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 5; }
+def GRV32WriteV6 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 6; }
+def GRV32WriteV7 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 7; }
+def GRV32WriteV9 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 9; }
+def GRV32WriteV10 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> { let Latency = 10; }
+
+def : WriteRes<WriteVLD1, []>;
+def : WriteRes<WriteVST1, []>;
+
+// Reserve GRV32UnitFP for 2 consecutive cycles.
+def GRV32Write2V4 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> {
+  let Latency = 4;
+  let ResourceCycles = [2];
+}
+def GRV32Write2V7 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> {
+  let Latency = 7;
+  let ResourceCycles = [2];
+}
+def GRV32Write2V9 : SchedWriteRes<[GRV32UnitFP, GRV32UnitAGU]> {
+  let Latency = 9;
+  let ResourceCycles = [2];
+}
+
+// Branches don't have a def operand but still consume resources.
+def GRV32WriteB : SchedWriteRes<[GRV32UnitB]>;
+
+// Address generation.
+def GRV32WriteAdr : SchedWriteRes<[GRV32UnitAGU]> { let NumMicroOps = 0; }
+
+// Load Integer.
+def GRV32WriteL : SchedWriteRes<[GRV32UnitLS]> { let Latency = 3; }
+def : SchedAlias<WriteLd, GRV32WriteL>;
+// Load the upper 32-bits using the same micro-op.
+def GRV32WriteLHi : SchedWriteRes<[]> { let Latency = 3;
+                                     let NumMicroOps = 0; }
+// Offset shifted by register.
+def GRV32WriteLsi : SchedWriteRes<[GRV32UnitLS]> { let Latency = 4; }
+// Load (and zero extend) a byte.
+def GRV32WriteLb : SchedWriteRes<[GRV32UnitLS]> { let Latency = 4; }
+def GRV32WriteLbsi : SchedWriteRes<[GRV32UnitLS]> { let Latency = 5; }
+
+// Load or Store Float, aligned.
+def GRV32WriteLSfp : SchedWriteRes<[GRV32UnitLS, GRV32UnitFP]> { let Latency = 1; }
+
+// Store Integer.
+def GRV32WriteS : SchedWriteRes<[GRV32UnitLS]>;
+
+//===----------------------------------------------------------------------===//
+// Define resources dynamically for load multiple variants.
+
+// Define helpers for extra latency without consuming resources.
+def GRV32WriteCycle1 : SchedWriteRes<[]> { let Latency = 1; let NumMicroOps = 0; }
+foreach NumCycles = 2-8 in {
+def GRV32WriteCycle#NumCycles : WriteSequence<[GRV32WriteCycle1], NumCycles>;
+} // foreach NumCycles
+
+// Define address generation sequences and predicates for 8 flavors of LDMs.
+foreach NumAddr = 1-8 in {
+
+// Define GRV32WriteAdr1-8 as a sequence of GRV32WriteAdr with additive
+// latency for instructions that generate multiple loads or stores.
+def GRV32WriteAdr#NumAddr : WriteSequence<[GRV32WriteAdr], NumAddr>;
+
+// Define a predicate to select the LDM based on number of memory addresses.
+def GRV32LMAdr#NumAddr#Pred :
+  SchedPredicate<"(TII->getNumLDMAddresses(*MI)+1)/2 == "#NumAddr>;
+
+} // foreach NumAddr
+
+// Fall-back for unknown LDMs.
+def GRV32LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == 0">;
+
+// LDM/VLDM/VLDn address generation latency & resources.
+// Dynamically select the GRV32WriteAdrN sequence using a predicate.
+def GRV32WriteLMAdr : SchedWriteVariant<[
+  SchedVar<GRV32LMAdr1Pred, [GRV32WriteAdr1]>,
+  SchedVar<GRV32LMAdr2Pred, [GRV32WriteAdr2]>,
+  SchedVar<GRV32LMAdr3Pred, [GRV32WriteAdr3]>,
+  SchedVar<GRV32LMAdr4Pred, [GRV32WriteAdr4]>,
+  SchedVar<GRV32LMAdr5Pred, [GRV32WriteAdr5]>,
+  SchedVar<GRV32LMAdr6Pred, [GRV32WriteAdr6]>,
+  SchedVar<GRV32LMAdr7Pred, [GRV32WriteAdr7]>,
+  SchedVar<GRV32LMAdr8Pred, [GRV32WriteAdr8]>,
+  // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
+  SchedVar<GRV32LMUnknownPred, [GRV32WriteAdr2]>]>;
+
+// Define LDM Resources.
+// These take no issue resource, so they can be combined with other
+// writes like WriteB.
+// GRV32WriteLMLo takes a single LS resource and 2 cycles.
+def GRV32WriteLMLo : SchedWriteRes<[GRV32UnitLS]> { let Latency = 2;
+                                              let NumMicroOps = 0; }
+// Assuming aligned access, the upper half of each pair is free with
+// the same latency.
+def GRV32WriteLMHi : SchedWriteRes<[]> { let Latency = 2;
+                                      let NumMicroOps = 0; }
+// Each GRV32WriteL#N variant adds N cycles of latency without consuming
+// additional resources.
+foreach NumAddr = 1-8 in {
+def GRV32WriteL#NumAddr : WriteSequence<
+  [GRV32WriteLMLo, !cast<SchedWrite>("GRV32WriteCycle"#NumAddr)]>;
+def GRV32WriteL#NumAddr#Hi : WriteSequence<
+  [GRV32WriteLMHi, !cast<SchedWrite>("GRV32WriteCycle"#NumAddr)]>;
+}
+
+//===----------------------------------------------------------------------===//
+// LDM: Load multiple into 32-bit integer registers.
+
+def GRV32WriteLMOpsList : GRV32WriteLMOpsListType<
+                 [GRV32WriteL1, GRV32WriteL1Hi,
+                  GRV32WriteL2, GRV32WriteL2Hi,
+                  GRV32WriteL3, GRV32WriteL3Hi,
+                  GRV32WriteL4, GRV32WriteL4Hi,
+                  GRV32WriteL5, GRV32WriteL5Hi,
+                  GRV32WriteL6, GRV32WriteL6Hi,
+                  GRV32WriteL7, GRV32WriteL7Hi,
+                  GRV32WriteL8, GRV32WriteL8Hi]>;
+
+// GRV32WriteLM variants expand into a pair of writes for each 64-bit
+// value loaded. When the number of registers is odd, the last
+// GRV32WriteLnHi is naturally ignored because the instruction has no
+// following def operands.  These variants take no issue resource, so
+// they may need to be part of a WriteSequence that includes GRV32WriteIssue.
+def GRV32WriteLM : SchedWriteVariant<[
+  SchedVar<GRV32LMAdr1Pred, GRV32WriteLMOpsList.Writes[0-1]>,
+  SchedVar<GRV32LMAdr2Pred, GRV32WriteLMOpsList.Writes[0-3]>,
+  SchedVar<GRV32LMAdr3Pred, GRV32WriteLMOpsList.Writes[0-5]>,
+  SchedVar<GRV32LMAdr4Pred, GRV32WriteLMOpsList.Writes[0-7]>,
+  SchedVar<GRV32LMAdr5Pred, GRV32WriteLMOpsList.Writes[0-9]>,
+  SchedVar<GRV32LMAdr6Pred, GRV32WriteLMOpsList.Writes[0-11]>,
+  SchedVar<GRV32LMAdr7Pred, GRV32WriteLMOpsList.Writes[0-13]>,
+  SchedVar<GRV32LMAdr8Pred, GRV32WriteLMOpsList.Writes[0-15]>,
+  // For unknown LDMs, define the maximum number of writes, but only
+  // make the first two consume resources.
+  SchedVar<GRV32LMUnknownPred, [GRV32WriteL1, GRV32WriteL1Hi,
+                             GRV32WriteL2, GRV32WriteL2Hi,
+                             GRV32WriteL3Hi, GRV32WriteL3Hi,
+                             GRV32WriteL4Hi, GRV32WriteL4Hi,
+                             GRV32WriteL5Hi, GRV32WriteL5Hi,
+                             GRV32WriteL6Hi, GRV32WriteL6Hi,
+                             GRV32WriteL7Hi, GRV32WriteL7Hi,
+                             GRV32WriteL8Hi, GRV32WriteL8Hi]>]> {
+  let Variadic = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// VFP Load/Store Multiple Variants, and NEON VLDn/VSTn support.
+
+// GRV32WriteLfpOp is the same as GRV32WriteLSfp but takes no issue resources
+// so can be used in WriteSequences for in single-issue instructions that
+// encapsulate multiple loads.
+def GRV32WriteLfpOp : SchedWriteRes<[GRV32UnitLS, GRV32UnitFP]> {
+  let Latency = 1;
+  let NumMicroOps = 0;
+}
+
+foreach NumAddr = 1-8 in {
+
+// Helper for GRV32WriteLfp1-8: A sequence of fp loads with no micro-ops.
+def GRV32WriteLfp#NumAddr#Seq : WriteSequence<[GRV32WriteLfpOp], NumAddr>;
+
+// GRV32WriteLfp1-8 definitions are statically expanded into a sequence of
+// GRV32WriteLfpOps with additive latency that takes a single issue slot.
+// Used directly to describe NEON VLDn.
+def GRV32WriteLfp#NumAddr : WriteSequence<
+  [GRV32WriteIssue, !cast<SchedWrite>("GRV32WriteLfp"#NumAddr#Seq)]>;
+
+// GRV32WriteLfp1-8Mov adds a cycle of latency and FP resource for
+// permuting loaded values.
+def GRV32WriteLfp#NumAddr#Mov : WriteSequence<
+  [GRV32WriteF, !cast<SchedWrite>("GRV32WriteLfp"#NumAddr#Seq)]>;
+
+} // foreach NumAddr
+
+// Define VLDM/VSTM PreRA resources.
+// GRV32WriteLMfpPreRA are dynamically expanded into the correct
+// GRV32WriteLfp1-8 sequence based on a predicate. This supports the
+// preRA VLDM variants in which all 64-bit loads are written to the
+// same tuple of either single or double precision registers.
+def GRV32WriteLMfpPreRA : SchedWriteVariant<[
+  SchedVar<GRV32LMAdr1Pred, [GRV32WriteLfp1]>,
+  SchedVar<GRV32LMAdr2Pred, [GRV32WriteLfp2]>,
+  SchedVar<GRV32LMAdr3Pred, [GRV32WriteLfp3]>,
+  SchedVar<GRV32LMAdr4Pred, [GRV32WriteLfp4]>,
+  SchedVar<GRV32LMAdr5Pred, [GRV32WriteLfp5]>,
+  SchedVar<GRV32LMAdr6Pred, [GRV32WriteLfp6]>,
+  SchedVar<GRV32LMAdr7Pred, [GRV32WriteLfp7]>,
+  SchedVar<GRV32LMAdr8Pred, [GRV32WriteLfp8]>,
+  // For unknown VLDM/VSTM PreRA, assume 2xS registers.
+  SchedVar<GRV32LMUnknownPred, [GRV32WriteLfp2]>]>;
+
+// Define VLDM/VSTM PostRA Resources.
+// GRV32WriteLMfpLo takes a LS and FP resource and one issue slot but no latency.
+def GRV32WriteLMfpLo : SchedWriteRes<[GRV32UnitLS, GRV32UnitFP]> { let Latency = 0; }
+
+foreach NumAddr = 1-8 in {
+
+// Each GRV32WriteL#N variant adds N cycles of latency without consuming
+// additional resources.
+def GRV32WriteLMfp#NumAddr : WriteSequence<
+  [GRV32WriteLMfpLo, !cast<SchedWrite>("GRV32WriteCycle"#NumAddr)]>;
+
+// Assuming aligned access, the upper half of each pair is free with
+// the same latency.
+def GRV32WriteLMfp#NumAddr#Hi : WriteSequence<
+  [GRV32WriteLMHi, !cast<SchedWrite>("GRV32WriteCycle"#NumAddr)]>;
+
+} // foreach NumAddr
+
+// VLDM PostRA Variants. These variants expand GRV32WriteLMfpPostRA into a
+// pair of writes for each 64-bit data loaded. When the number of
+// registers is odd, the last WriteLMfpnHi is naturally ignored because
+// the instruction has no following def operands.
+
+def GRV32WriteLMfpPostRAOpsList : GRV32WriteLMOpsListType<
+                 [GRV32WriteLMfp1, GRV32WriteLMfp2,       // 0-1
+                  GRV32WriteLMfp3, GRV32WriteLMfp4,       // 2-3
+                  GRV32WriteLMfp5, GRV32WriteLMfp6,       // 4-5
+                  GRV32WriteLMfp7, GRV32WriteLMfp8,       // 6-7
+                  GRV32WriteLMfp1Hi,                   // 8-8
+                  GRV32WriteLMfp2Hi, GRV32WriteLMfp2Hi,   // 9-10
+                  GRV32WriteLMfp3Hi, GRV32WriteLMfp3Hi,   // 11-12
+                  GRV32WriteLMfp4Hi, GRV32WriteLMfp4Hi,   // 13-14
+                  GRV32WriteLMfp5Hi, GRV32WriteLMfp5Hi,   // 15-16
+                  GRV32WriteLMfp6Hi, GRV32WriteLMfp6Hi,   // 17-18
+                  GRV32WriteLMfp7Hi, GRV32WriteLMfp7Hi,   // 19-20
+                  GRV32WriteLMfp8Hi, GRV32WriteLMfp8Hi]>; // 21-22
+
+def GRV32WriteLMfpPostRA : SchedWriteVariant<[
+  SchedVar<GRV32LMAdr1Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
+  SchedVar<GRV32LMAdr2Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-1, 9-10]>,
+  SchedVar<GRV32LMAdr3Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-2, 10-12]>,
+  SchedVar<GRV32LMAdr4Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-3, 11-14]>,
+  SchedVar<GRV32LMAdr5Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-4, 12-16]>,
+  SchedVar<GRV32LMAdr6Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-5, 13-18]>,
+  SchedVar<GRV32LMAdr7Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-6, 14-20]>,
+  SchedVar<GRV32LMAdr8Pred, GRV32WriteLMfpPostRAOpsList.Writes[0-7, 15-22]>,
+  // For unknown LDMs, define the maximum number of writes, but only
+  // make the first two consume resources. We are optimizing for the case
+  // where the operands are DPRs, and this determines the first eight
+  // types. The remaining eight types are filled to cover the case
+  // where the operands are SPRs.
+  SchedVar<GRV32LMUnknownPred, [GRV32WriteLMfp1, GRV32WriteLMfp2,
+                             GRV32WriteLMfp3Hi, GRV32WriteLMfp4Hi,
+                             GRV32WriteLMfp5Hi, GRV32WriteLMfp6Hi,
+                             GRV32WriteLMfp7Hi, GRV32WriteLMfp8Hi,
+                             GRV32WriteLMfp5Hi, GRV32WriteLMfp5Hi,
+                             GRV32WriteLMfp6Hi, GRV32WriteLMfp6Hi,
+                             GRV32WriteLMfp7Hi, GRV32WriteLMfp7Hi,
+                             GRV32WriteLMfp8Hi, GRV32WriteLMfp8Hi]>]> {
+  let Variadic = 1;
+}
+
+// Distinguish between our multiple MI-level forms of the same
+// VLDM/VSTM instructions.
+def GRV32PreRA : SchedPredicate<
+  "TargetRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg())">;
+def GRV32PostRA : SchedPredicate<
+  "TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).getReg())">;
+
+// VLDM represents all destination registers as a single register
+// tuple, unlike LDM. So the number of write operands is not variadic.
+def GRV32WriteLMfp : SchedWriteVariant<[
+  SchedVar<GRV32PreRA, [GRV32WriteLMfpPreRA]>,
+  SchedVar<GRV32PostRA, [GRV32WriteLMfpPostRA]>]>;
+
+//===----------------------------------------------------------------------===//
+// Resources for other (non-LDM/VLDM) Variants.
+
+// These mov immediate writers are unconditionally expanded with
+// additive latency.
+def GRV32WriteI2 : WriteSequence<[GRV32WriteI, GRV32WriteI]>;
+def GRV32WriteI2pc : WriteSequence<[GRV32WriteI, GRV32WriteI, WriteALU]>;
+def GRV32WriteI2ld  : WriteSequence<[GRV32WriteI, GRV32WriteI, GRV32WriteL]>;
+
+// Some ALU operations can read loaded integer values one cycle early.
+def GRV32ReadALU : SchedReadAdvance<1,
+  [GRV32WriteL, GRV32WriteLHi, GRV32WriteLsi, GRV32WriteLb, GRV32WriteLbsi,
+   GRV32WriteL1, GRV32WriteL2, GRV32WriteL3, GRV32WriteL4,
+   GRV32WriteL5, GRV32WriteL6, GRV32WriteL7, GRV32WriteL8,
+   GRV32WriteL1Hi, GRV32WriteL2Hi, GRV32WriteL3Hi, GRV32WriteL4Hi,
+   GRV32WriteL5Hi, GRV32WriteL6Hi, GRV32WriteL7Hi, GRV32WriteL8Hi]>;
+
+// Read types for operands that are unconditionally read in cycle N
+// after the instruction issues, decreases producer latency by N-1.
+def GRV32Read2 : SchedReadAdvance<1>;
+def GRV32Read3 : SchedReadAdvance<2>;
+def GRV32Read4 : SchedReadAdvance<3>;
+
+// Map SchedRWs that are identical for cortexa9 to existing resources.
+def : SchedAlias<WriteALU, GRV32WriteALU>;
+def : SchedAlias<WriteALUsr, GRV32WriteALUsr>;
+def : SchedAlias<WriteALUSsr, GRV32WriteALUsr>;
+def : SchedAlias<ReadALU, GRV32ReadALU>;
+def : SchedAlias<ReadALUsr, GRV32ReadALU>;
+def : SchedAlias<WriteST, GRV32WriteS>;
+
+// ===---------------------------------------------------------------------===//
+// Floating-point. Map target defined SchedReadWrite to processor specific ones
+//
+def : WriteRes<WriteFPCVT, [GRV32UnitFP, GRV32UnitAGU]> { let Latency = 4; }
+def : SchedAlias<WriteFPMOV, GRV32WriteFMov>;
+
+def : SchedAlias<WriteFPALU32, GRV32WriteF>;
+def : SchedAlias<WriteFPALU64, GRV32WriteF>;
+
+def : SchedAlias<WriteFPMUL32, GRV32WriteFMulS>;
+def : SchedAlias<WriteFPMUL64, GRV32WriteFMulD>;
+
+def : SchedAlias<WriteFPMAC32, GRV32WriteFMAS>;
+def : SchedAlias<WriteFPMAC64, GRV32WriteFMAD>;
+
+def : SchedAlias<WriteFPDIV32, GRV32WriteFDivS>;
+def : SchedAlias<WriteFPDIV64, GRV32WriteFDivD>;
+def : SchedAlias<WriteFPSQRT32, GRV32WriteFSqrtS>;
+def : SchedAlias<WriteFPSQRT64, GRV32WriteFSqrtD>;
+
+def : ReadAdvance<ReadFPMUL, 0>;
+def : ReadAdvance<ReadFPMAC, 0>;
+
+// ===---------------------------------------------------------------------===//
+// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types.
+//
+def : SchedAlias<WriteCMP, GRV32WriteALU>;
+def : SchedAlias<WriteCMPsi, GRV32WriteALU>;
+def : SchedAlias<WriteCMPsr, GRV32WriteALU>;
+
+def : WriteRes<WriteDIV, []> { let Latency = 0; }
+
+def : WriteRes<WriteBr, [GRV32UnitB]>;
+def : WriteRes<WriteBrL, [GRV32UnitB]>;
+def : WriteRes<WriteBrTbl, [GRV32UnitB]>;
+def : WriteRes<WritePreLd, []>;
+def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
+} // SchedModel = GRV32Model

lib/Target/RISCV/RISCVSubtarget.h

 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 
 #include "RISCVFrameLowering.h"
 #include "RISCVISelLowering.h"
 #include "RISCVInstrInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetMachine.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "RISCVGenSubtargetInfo.inc"
 
 namespace llvm {
+class RISCVTargetMachine;
 class StringRef;
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
class RISCVSubtarget : public RISCVGenSubtargetInfo {
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                   bool Is64Bit);
 
 public:
   // Initializes the data members to match that of the specified triple.
   RISCVSubtarget(const Triple &TT, const std::string &CPU,
-                 const std::string &FS, const TargetMachine &TM);
+                 const std::string &FS, const RISCVTargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   const RISCVFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const RISCVRegisterInfo *getRegisterInfo() const override {
     return &RegInfo;
   }
   const RISCVTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
+  const CallLowering *getCallLowering() const override;
+  const InstructionSelector *getInstructionSelector() const override;
+  const LegalizerInfo *getLegalizerInfo() const override;
+  const RegisterBankInfo *getRegBankInfo() const override;
+
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
+
+  bool useMachineScheduler() const { return UseMISched; }
+  bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
+
+  /// Returns true if machine scheduler should be enabled.
+  bool enableMachineScheduler() const override;
+
+  /// True for some subtargets at > -O0.
+  bool enablePostRAScheduler() const override;
+
+protected:
+  /// UseMISched - True if MachineScheduler should be used for this subtarget.
+  bool UseMISched = false;
+
+  /// DisablePostRAScheduler - False if scheduling should happen again after
+  /// register allocation.
+  bool DisablePostRAScheduler = false;
+
+private:
+  /// GlobalISel related APIs.
+  std::unique_ptr<CallLowering> CallLoweringInfo;
+  std::unique_ptr<InstructionSelector> InstSelector;
+  std::unique_ptr<LegalizerInfo> Legalizer;
+  std::unique_ptr<RegisterBankInfo> RegBankInfo;
 };
 } // End llvm namespace
 
 #endif

lib/Target/RISCV/RISCVSubtarget.cpp

 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
+#include "RISCVCallLowering.h"
+#include "RISCVLegalizerInfo.h"
+#include "RISCVRegisterBankInfo.h"
 #include "RISCVSubtarget.h"
+#include "RISCVTargetMachine.h"
 #include "RISCV.h"
 #include "RISCVFrameLowering.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
   if (Is64Bit) {
     XLenVT = MVT::i64;
     XLen = 64;
   }
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU,
-                               const std::string &FS, const TargetMachine &TM)
+                               const std::string &FS,
+                               const RISCVTargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
-      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {
+  CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
+  Legalizer.reset(new RISCVLegalizerInfo(*this, TM));
+
+  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
+  InstSelector.reset(createRISCVInstructionSelector(
+      *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
+
+  RegBankInfo.reset(RBI);
+}
+
+const CallLowering *RISCVSubtarget::getCallLowering() const {
+  return CallLoweringInfo.get();
+}
+
+const InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
+  return InstSelector.get();
+}
+
+const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
+  return Legalizer.get();
+}
+
+const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
+  return RegBankInfo.get();
+}
+
+bool RISCVSubtarget::enableMachineScheduler() const {
+  // Enable the MachineScheduler before register allocation for subtargets
+  // with the use-misched feature.
+  return useMachineScheduler();
+}
+
+// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
+bool RISCVSubtarget::enablePostRAScheduler() const {
+  return !disablePostRAScheduler();
+}

lib/Target/RISCV/RISCVTargetMachine.cpp

 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // Implements the info about RISCV target spec.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 extern "C" void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
+
+  PassRegistry &Registry = *PassRegistry::getPassRegistry();
+  initializeGlobalISel(Registry);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit()) {
     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   } else {
     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
     return "e-m:e-p:32:32-i64:64-n32-S128";
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
       Subtarget(TT, CPU, FS, *this) {
   initAsmInfo();
 }
 
 namespace {
 class RISCVPassConfig : public TargetPassConfig {
 public:
   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
-      : TargetPassConfig(TM, PM) {}
+      : TargetPassConfig(TM, PM) {
+    if (TM.getOptLevel() != CodeGenOpt::None) {
+      RISCVGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
+                              TM.getTargetFeatureString());
+      if (STI.hasFeature(RISCV::FeatureUseMISched))
+        substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
+    }
+  }
 
   RISCVTargetMachine &getRISCVTargetMachine() const {
     return getTM<RISCVTargetMachine>();
   }
 
+  bool addGlobalInstructionSelect() override;
   bool addInstSelector() override;
+  bool addIRTranslator() override;
+  bool addLegalizeMachineIR() override;
+  bool addRegBankSelect() override;
   void addPreEmitPass() override;
 };
 }
 
 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new RISCVPassConfig(*this, PM);
 }
 
+bool RISCVPassConfig::addGlobalInstructionSelect() {
+  addPass(new InstructionSelect());
+  return false;
+}
+
 bool RISCVPassConfig::addInstSelector() {
   addPass(createRISCVISelDag(getRISCVTargetMachine()));
 
   return false;
 }
 
+bool RISCVPassConfig::addIRTranslator() {
+  addPass(new IRTranslator());
+  return false;
+}
+
+bool RISCVPassConfig::addLegalizeMachineIR() {
+  addPass(new Legalizer());
+  return false;
+}
+
+bool RISCVPassConfig::addRegBankSelect() {
+  addPass(new RegBankSelect());
+  return false;
+}
+
 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }