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[RISCV] Initial Machine Scheduler

Authored by xiangzhai on Jan 13 2018, 11:25 PM.



Hi LLVM developers,


I am reviewing Compiler Principle about ILP and learning Slides about Machine Scheduler.

So I just initial Machine scheduling model for RISCV Target, but I have no idea where to find scheduling information derived from "Which RV32 or RV64 Technical Reference Manual".

And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core what about PULP? is it in-order or out-of-order?

Please give me some directions, thanks a lot!

PS: I will rebase this patch based on D41700 and D41653 for porting GlobalISel to RISCV Target.

Leslie Zhai

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Event Timeline

xiangzhai created this revision.Jan 13 2018, 11:25 PM
javed.absar added inline comments.Jan 18 2018, 2:08 AM

These definitions may be ok for a start, but you would need to decide what best fits your purpose (maybe fewer SchedWriteTypes to begin with ?)


Why not ProcResource?

xiangzhai added inline comments.Jan 18 2018, 3:06 AM

Hi Javed,

Thanks for your review and great tutorial about Writing Great Machine Schedulers !

As my comment FIXME mentioned:

I have no idea how to find scheduling information, perhaps some RV32 Technical Reference Manual provided?

So I am reading gcc riscv Target's Generic DFA-based pipeline without manual, it is like AVR Target migate to LLD, there is no ABI manual either, so I have to borrow code from binutils in D37615 .

I want to learn and practice, please leading me, thanks a lot!

Leslie Zhai

xiangzhai added inline comments.Jan 18 2018, 3:08 AM

My sincere thanks still need to goto you for reviewing D39712 even it is not LGTM :)

asb added a comment.Jan 18 2018, 4:27 AM

Leslie - there's a huge amount here that's copied and pasted from, much of it really isn't relevant to any current RISC-V implementation, such as load-multiple/store-multiple and vector operations. Additionally, the A9 is an out-of-order superscalar core. The majority of the RISC-V community are targeting in-order cores (Rocket, PULP, other microcontroller class cores). If you're keen to explore scheduling models for out-of-order cores then BOOM is of course the obvious target.

This patch is intermingled with other changes that you have for review (e.g. calling convention implementation changes, globalisel) - it's always best to post a diff that only contains the changes needed for this particular review.

What you've done here is a good start for getting a better understanding of how machine scheduling works. What I think you need to do now is figure out what sort of scheduling model you want to write (e.g. for the default configuration of Rocket), and how you can write tests that demonstrate the model is doing what it is meant to do, then you can try to produce something that's a little more minimal than what you have here. I don't have enough experience with LLVM scheduling models to predict how much there might be to gain for a pipeline as simple as Rocket. It's single-issue in-order, but does have a non-blocking L1 cache which allows the pipeline to continue under a cache miss until there is a dependency on the result.

Hi Alex,

Thanks for your response! Sorry that I borrow code from which is of course not suitable for RISCV Target, and I only find some product introduction PDFs:

And Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core

But where could I find the scheduling information providing "RV32 or RV64 Technical Reference Manual"? I am reading GCC riscv Target Generic DFA-based pipeline but its comment indicated that:

Based on MIPS target for GNU compiler.

So perhaps I can "migrate" GCC pipeline to LLVM by reading GCC source code, if there is no manual?

Leslie Zhai

xiangzhai abandoned this revision.May 1 2021, 2:19 AM
rkruppe removed a subscriber: rkruppe.May 1 2021, 3:43 AM