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Differential D40836

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
ClosedPublic

Authored by thegameg on Dec 5 2017, 6:12 AM.

Details

Reviewers
MatzeB
echristo
rovka
bogner
aprantl
qcolombet
Summary

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

Work towards the unification of MIR and debug output by refactoring the interfaces.

For MachineOperand::print, keep a simple version that can be easily called from dump(), and a more complex one which will be called from both the MIRPrinter and MachineInstr::print.

Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr).

Diff Detail

Event Timeline

thegameg created this revision.Dec 5 2017, 6:12 AM
Herald added a subscriber: JDevlieghere. · View Herald TranscriptDec 5 2017, 6:12 AM
MatzeB edited edge metadata.Dec 5 2017, 8:28 PM

Looks good, but I assume this is incomplete and cannot be pushed like this?

lib/CodeGen/MachineInstr.cpp
1245

I think in case of MachineInstr::print() (at least by default) we should print all register ties on machine operands. Not sure what your plans with this flag are anyway as it's not really used by MachineOperand::print yet?

lib/CodeGen/MachineOperand.cpp
264–268

Is this necessary for the printing changes?

360

This feels a bit strange to me in cases where the user already specified TRI/IntrinsicInfo/...

thegameg updated this revision to Diff 125695.Dec 6 2017, 4:17 AM
thegameg retitled this revision from [CodeGen] Unify printing API for MachineOperand between MIR and debug to [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register..
thegameg edited the summary of this revision. (Show Details)
thegameg added reviewers: aprantl, qcolombet.
  • Move implementation from the MIRPrinter to MachineOperand.
  • Update tests.
Herald added subscribers: kbarton, eraman, javed.absar and 6 others. · View Herald TranscriptDec 6 2017, 4:17 AM
thegameg added inline comments.Dec 6 2017, 4:25 AM
lib/CodeGen/LiveVariables.cpp
238

I also assumed <imp-kill> here meant implicit-use killed.

lib/CodeGen/MachineOperand.cpp
264–268

No, not necessary. I can commit this separately.

360

Indeed, it was one of the questions I was having: should we assume that if the user is using the "complex" printing method then we're not trying to get the target info for them (and remove the default arguments to make it more obvious) ? In other words, should we only call tryToGetTargetInfo on the first ::print method (and obviously document this behavior and do the same for MI, MBB, MF) ?

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
156

I don't know how much we want this debug-use to show up here. What do you think @aprantl?

MatzeB accepted this revision.Dec 6 2017, 11:27 AM

LGTM, thanks for thoroughly replacing the syntax in all the comments.

include/llvm/CodeGen/MachineBasicBlock.h
705

too much automatic replacements :) (and too fancy writing in the original comment)

lib/CodeGen/LiveVariables.cpp
238

yes it's an implicit use with a kill flag. Is there anything confusing here?

I know the syntax used in the comments isn't always consistent. We also have this strange thing in .mir where implicit-def is just another word for implicit def (but that is something to fix another day).

lib/CodeGen/MachineOperand.cpp
360

Yeah given that this is more of a convenience functionality rather than a core part of printing moving it to the other convenience print function makes sense to me.

lib/CodeGen/MachineSink.cpp
249

shouldn't this be implicit def dead

lib/CodeGen/RegAllocFast.cpp
275

killed

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
156

The MachineOperand isDebug flag is so obvious (it is exactly set on the operands of DBG_VALUE instructions and nowhere else) and is more of a shortcut to avoid a few MachineOperand::getParent()->isDebug() calls rather than a flag that contains real information that I'd vote to not print or parse it. (And just compute it when parsing .mir I believe this is already happening anyway). Of course we don't necessarily need to make this change in this patch.

This revision is now accepted and ready to land.Dec 6 2017, 11:27 AM
thegameg closed this revision.Dec 7 2017, 2:55 AM
thegameg marked 9 inline comments as done.

Committed as r320022 [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

lib/CodeGen/LiveVariables.cpp
238

Right, I was wondering why not <imp-use,kill>.

Large Diff

This large diff affects 330 files. Files without inline comments have been collapsed. Expand All Files

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Diff 125695

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

include/llvm/CodeGen/LivePhysRegs.h

include/llvm/CodeGen/MachineBasicBlock.h

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
/// Possible outcome of a register liveness query to computeRegisterLiveness() /// Possible outcome of a register liveness query to computeRegisterLiveness()
enum LivenessQueryResult { enum LivenessQueryResult {
LQR_Live, ///< Register is known to be (at least partially) live. LQR_Live, ///< Register is known to be (at least partially) live.
LQR_Dead, ///< Register is known to be fully dead. LQR_Dead, ///< Register is known to be fully dead.
LQR_Unknown ///< Register liveness not decidable from local neighborhood. LQR_Unknown ///< Register liveness not decidable from local neighborhood.
}; };
/// Return whether (physical) register \p Reg has been <def>ined and not /// Return whether (physical) register \p Reg has been ined and not
MatzeBUnsubmitted
Not Done
ReplyInline Actions

too much automatic replacements :) (and too fancy writing in the original comment)

MatzeB: too much automatic replacements :) (and too fancy writing in the original comment)
/// <kill>ed as of just before \p Before. /// <kill>ed as of just before \p Before.
/// ///
/// Search is localised to a neighborhood of \p Neighborhood instructions /// Search is localised to a neighborhood of \p Neighborhood instructions
/// before (searching for defs or kills) and \p Neighborhood instructions /// before (searching for defs or kills) and \p Neighborhood instructions
/// after (searching just for defs) \p Before. /// after (searching just for defs) \p Before.
/// ///
/// \p Reg must be a physical register. /// \p Reg must be a physical register.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
▲ Show 20 Lines • Show All 182 Lines • Show Last 20 Lines

include/llvm/CodeGen/MachineInstr.h

include/llvm/CodeGen/MachineInstrBundle.h

include/llvm/CodeGen/MachineOperand.h

include/llvm/CodeGen/TargetInstrInfo.h

include/llvm/CodeGen/TargetRegisterInfo.h

lib/CodeGen/AggressiveAntiDepBreaker.cpp

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

lib/CodeGen/BranchFolding.cpp

lib/CodeGen/CriticalAntiDepBreaker.cpp

lib/CodeGen/ExpandPostRAPseudos.cpp

lib/CodeGen/ImplicitNullChecks.cpp

lib/CodeGen/InlineSpiller.cpp

lib/CodeGen/LiveIntervalAnalysis.cpp

lib/CodeGen/LiveVariables.cpp

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
/// super-register. /// super-register.
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
MachineInstr *LastDef = PhysRegDef[Reg]; MachineInstr *LastDef = PhysRegDef[Reg];
// If there was a previous use or a "full" def all is well. // If there was a previous use or a "full" def all is well.
if (!LastDef && !PhysRegUse[Reg]) { if (!LastDef && !PhysRegUse[Reg]) {
// Otherwise, the last sub-register def implicitly defines this register. // Otherwise, the last sub-register def implicitly defines this register.
// e.g. // e.g.
// AH = // AH =
// AL = ... <imp-def EAX>, <imp-kill AH> // AL = ... implicit-def EAX, implicit killed AH
thegamegAuthorUnsubmitted
Done
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I also assumed <imp-kill> here meant implicit-use killed.

thegameg: I also assumed `<imp-kill>` here meant `implicit-use killed`.
MatzeBUnsubmitted
Not Done
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yes it's an implicit use with a kill flag. Is there anything confusing here?

I know the syntax used in the comments isn't always consistent. We also have this strange thing in .mir where implicit-def is just another word for implicit def (but that is something to fix another day).

MatzeB: yes it's an implicit use with a kill flag. Is there anything confusing here? I know the syntax…
thegamegAuthorUnsubmitted
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Right, I was wondering why not <imp-use,kill>.

thegameg: Right, I was wondering why not <imp-use,kill>.
// = AH // = AH
// ... // ...
// = EAX // = EAX
// All of the sub-registers must have been defined before the use of Reg! // All of the sub-registers must have been defined before the use of Reg!
SmallSet<unsigned, 4> PartDefRegs; SmallSet<unsigned, 4> PartDefRegs;
MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
// If LastPartialDef is NULL, it must be using a livein register. // If LastPartialDef is NULL, it must be using a livein register.
if (LastPartialDef) { if (LastPartialDef) {
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef; MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef]; unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
// The whole register is used. // The whole register is used.
// AL = // AL =
// AH = // AH =
// //
// = AX // = AX
// = AL, AX<imp-use, kill> // = AL, implicit killed AX
// AX = // AX =
// //
// Or whole register is defined, but not used at all. // Or whole register is defined, but not used at all.
// AX<dead> = // dead AX =
// ... // ...
// AX = // AX =
// //
// Or whole register is defined, but only partly used. // Or whole register is defined, but only partly used.
// AX<dead> = AL<imp-def> // dead AX = implicit-def AL
// = AL<kill> // = killed AL
// AX = // AX =
MachineInstr *LastPartDef = nullptr; MachineInstr *LastPartDef = nullptr;
unsigned LastPartDefDist = 0; unsigned LastPartDefDist = 0;
SmallSet<unsigned, 8> PartUses; SmallSet<unsigned, 8> PartUses;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
unsigned SubReg = *SubRegs; unsigned SubReg = *SubRegs;
MachineInstr *Def = PhysRegDef[SubReg]; MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) { if (Def && Def != LastDef) {
Show All 16 Lines
LastRefOrPartRef = Use; LastRefOrPartRef = Use;
} }
} }
} }
if (!PhysRegUse[Reg]) { if (!PhysRegUse[Reg]) {
// Partial uses. Mark register def dead and add implicit def of // Partial uses. Mark register def dead and add implicit def of
// sub-registers which are used. // sub-registers which are used.
// EAX<dead> = op AL<imp-def> // dead EAX = op implicit-def AL
// That is, EAX def is dead but AL def extends pass it. // That is, EAX def is dead but AL def extends pass it.
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
unsigned SubReg = *SubRegs; unsigned SubReg = *SubRegs;
if (!PartUses.count(SubReg)) if (!PartUses.count(SubReg))
continue; continue;
bool NeedDef = true; bool NeedDef = true;
if (PhysRegDef[Reg] == PhysRegDef[SubReg]) { if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

lib/CodeGen/MIRPrinter.cpp

lib/CodeGen/MachineCSE.cpp

lib/CodeGen/MachineCopyPropagation.cpp

lib/CodeGen/MachineInstr.cpp

Show All 12 Lines
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/ADT/APFloat.h" #include "llvm/ADT/APFloat.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/Hashing.h" #include "llvm/ADT/Hashing.h"
#include "llvm/ADT/None.h" #include "llvm/ADT/None.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/Loads.h" #include "llvm/Analysis/Loads.h"
#include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
▲ Show 20 Lines • Show All 400 Lines • ▼ Show 20 Lines
const MachineOperand &MO = getOperand(i); const MachineOperand &MO = getOperand(i);
if (!MO.isReg() || MO.getReg() != Reg) if (!MO.isReg() || MO.getReg() != Reg)
continue; continue;
if (Ops) if (Ops)
Ops->push_back(i); Ops->push_back(i);
if (MO.isUse()) if (MO.isUse())
Use |= !MO.isUndef(); Use |= !MO.isUndef();
else if (MO.getSubReg() && !MO.isUndef()) else if (MO.getSubReg() && !MO.isUndef())
// A partial <def,undef> doesn't count as reading the register. // A partial def undef doesn't count as reading the register.
PartDef = true; PartDef = true;
else else
FullDef = true; FullDef = true;
} }
// A partial redefine uses Reg unless there is also a full define. // A partial redefine uses Reg unless there is also a full define.
return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
} }
▲ Show 20 Lines • Show All 400 Lines • ▼ Show 20 Lines
for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
i != e; ++i) { i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i); const MachineOperand &MO = MI.getOperand(i);
if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
addOperand(MF, MO); addOperand(MF, MO);
} }
} }
bool MachineInstr::hasComplexRegisterTies() const {
const MCInstrDesc &MCID = getDesc();
for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
const auto &Operand = getOperand(I);
if (!Operand.isReg() || Operand.isDef())
// Ignore the defined registers as MCID marks only the uses as tied.
continue;
int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
if (ExpectedTiedIdx != TiedIdx)
return true;
}
return false;
}
LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
const MachineRegisterInfo &MRI) const {
const MachineOperand &Op = getOperand(OpIdx);
if (!Op.isReg())
return LLT{};
if (isVariadic() || OpIdx >= getNumExplicitOperands())
return MRI.getType(Op.getReg());
auto &OpInfo = getDesc().OpInfo[OpIdx];
if (!OpInfo.isGenericType())
return MRI.getType(Op.getReg());
if (PrintedTypes[OpInfo.getGenericTypeIndex()])
return LLT{};
PrintedTypes.set(OpInfo.getGenericTypeIndex());
return MRI.getType(Op.getReg());
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void MachineInstr::dump() const { LLVM_DUMP_METHOD void MachineInstr::dump() const {
dbgs() << " "; dbgs() << " ";
print(dbgs()); print(dbgs());
} }
#endif #endif
void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc, void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
Show All 25 Lines
TII = MF->getSubtarget().getInstrInfo(); TII = MF->getSubtarget().getInstrInfo();
IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
} }
} }
// Save a list of virtual registers. // Save a list of virtual registers.
SmallVector<unsigned, 8> VirtRegs; SmallVector<unsigned, 8> VirtRegs;
SmallBitVector PrintedTypes(8);
bool ShouldPrintRegisterTies = hasComplexRegisterTies();
auto getTiedOperandIdx = [&](unsigned OpIdx) {
MatzeBUnsubmitted
Not Done
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I think in case of MachineInstr::print() (at least by default) we should print all register ties on machine operands. Not sure what your plans with this flag are anyway as it's not really used by MachineOperand::print yet?

MatzeB: I think in case of MachineInstr::print() (at least by default) we should print all register…
if (!ShouldPrintRegisterTies)
return 0U;
const MachineOperand &MO = getOperand(OpIdx);
if (MO.isReg() && MO.isTied() && !MO.isDef())
return findTiedOperandIdx(OpIdx);
return 0U;
};
// Print explicitly defined operands on the left of an assignment syntax. // Print explicitly defined operands on the left of an assignment syntax.
unsigned StartOp = 0, e = getNumOperands(); unsigned StartOp = 0, e = getNumOperands();
for (; StartOp < e && getOperand(StartOp).isReg() && for (; StartOp < e && getOperand(StartOp).isReg() &&
getOperand(StartOp).isDef() && getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit();
!getOperand(StartOp).isImplicit();
++StartOp) { ++StartOp) {
if (StartOp != 0) OS << ", "; if (StartOp != 0)
getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo); OS << ", ";
LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false,
ShouldPrintRegisterTies, TiedOperandIdx, TRI,
IntrinsicInfo);
unsigned Reg = getOperand(StartOp).getReg(); unsigned Reg = getOperand(StartOp).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (TargetRegisterInfo::isVirtualRegister(Reg))
VirtRegs.push_back(Reg); VirtRegs.push_back(Reg);
LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
if (Ty.isValid())
OS << '(' << Ty << ')';
}
} }
if (StartOp != 0) if (StartOp != 0)
OS << " = "; OS << " = ";
// Print the opcode name. // Print the opcode name.
if (TII) if (TII)
OS << TII->getName(getOpcode()); OS << TII->getName(getOpcode());
else else
OS << "UNKNOWN"; OS << "UNKNOWN";
if (SkipOpers) if (SkipOpers)
return; return;
// Print the rest of the operands. // Print the rest of the operands.
bool FirstOp = true; bool FirstOp = true;
unsigned AsmDescOp = ~0u; unsigned AsmDescOp = ~0u;
unsigned AsmOpCount = 0; unsigned AsmOpCount = 0;
if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
// Print asm string. // Print asm string.
OS << " "; OS << " ";
getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI); const unsigned OpIdx = InlineAsm::MIOp_AsmString;
LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true,
ShouldPrintRegisterTies, TiedOperandIdx, TRI,
IntrinsicInfo);
// Print HasSideEffects, MayLoad, MayStore, IsAlignStack // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
if (ExtraInfo & InlineAsm::Extra_HasSideEffects) if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
OS << " [sideeffect]"; OS << " [sideeffect]";
if (ExtraInfo & InlineAsm::Extra_MayLoad) if (ExtraInfo & InlineAsm::Extra_MayLoad)
OS << " [mayload]"; OS << " [mayload]";
if (ExtraInfo & InlineAsm::Extra_MayStore) if (ExtraInfo & InlineAsm::Extra_MayStore)
Show All 26 Lines
if (MCOI.isOptionalDef()) if (MCOI.isOptionalDef())
OS << "opt:"; OS << "opt:";
} }
if (isDebugValue() && MO.isMetadata()) { if (isDebugValue() && MO.isMetadata()) {
// Pretty print DBG_VALUE instructions. // Pretty print DBG_VALUE instructions.
auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
if (DIV && !DIV->getName().empty()) if (DIV && !DIV->getName().empty())
OS << "!\"" << DIV->getName() << '\"'; OS << "!\"" << DIV->getName() << '\"';
else else {
MO.print(OS, MST, TRI); LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
}
} else if (TRI && (isInsertSubreg() || isRegSequence() || } else if (TRI && (isInsertSubreg() || isRegSequence() ||
(isSubregToReg() && i == 3)) && MO.isImm()) { (isSubregToReg() && i == 3)) && MO.isImm()) {
OS << TRI->getSubRegIndexName(MO.getImm()); OS << TRI->getSubRegIndexName(MO.getImm());
} else if (i == AsmDescOp && MO.isImm()) { } else if (i == AsmDescOp && MO.isImm()) {
// Pretty print the inline asm operand descriptor. // Pretty print the inline asm operand descriptor.
OS << '$' << AsmOpCount++; OS << '$' << AsmOpCount++;
unsigned Flag = MO.getImm(); unsigned Flag = MO.getImm();
switch (InlineAsm::getKind(Flag)) { switch (InlineAsm::getKind(Flag)) {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
unsigned TiedTo = 0; unsigned TiedTo = 0;
if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
OS << " tiedto:$" << TiedTo; OS << " tiedto:$" << TiedTo;
OS << ']'; OS << ']';
// Compute the index of the next operand descriptor. // Compute the index of the next operand descriptor.
AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
} else } else {
MO.print(OS, MST, TRI); LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, ShouldPrintRegisterTies,
TiedOperandIdx, TRI, IntrinsicInfo);
}
} }
bool HaveSemi = false; bool HaveSemi = false;
const unsigned PrintableFlags = FrameSetup | FrameDestroy; const unsigned PrintableFlags = FrameSetup | FrameDestroy;
if (Flags & PrintableFlags) { if (Flags & PrintableFlags) {
if (!HaveSemi) { if (!HaveSemi) {
OS << ";"; OS << ";";
HaveSemi = true; HaveSemi = true;
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

lib/CodeGen/MachineOperand.cpp

Show All 9 Lines
/// \file Methods common to all machine operands. /// \file Methods common to all machine operands.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOperand.h"
#include "llvm/Analysis/Loads.h" #include "llvm/Analysis/Loads.h"
#include "llvm/CodeGen/MIRPrinter.h" #include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h" #include "llvm/IR/Constants.h"
#include "llvm/IR/ModuleSlotTracker.h" #include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm; using namespace llvm;
static cl::opt<int> static cl::opt<int>
PrintRegMaskNumRegs("print-regmask-num-regs", PrintRegMaskNumRegs("print-regmask-num-regs",
cl::desc("Number of registers to limit to when " cl::desc("Number of registers to limit to when "
"printing regmask operands in IR dumps. " "printing regmask operands in IR dumps. "
"unlimited = -1"), "unlimited = -1"),
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines case MachineOperand::MO_RegisterLiveOut: {
const uint32_t *RegMask = getRegMask(); const uint32_t *RegMask = getRegMask();
const uint32_t *OtherRegMask = Other.getRegMask(); const uint32_t *OtherRegMask = Other.getRegMask();
if (RegMask == OtherRegMask) if (RegMask == OtherRegMask)
return true; return true;
// Calculate the size of the RegMask // Calculate the size of the RegMask
const MachineFunction *MF = getParent()->getMF(); const MachineFunction *MF = getParent()->getMF();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32; unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
// Deep compare of the two RegMasks // Deep compare of the two RegMasks
return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
} }
MatzeBUnsubmitted
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Is this necessary for the printing changes?

MatzeB: Is this necessary for the printing changes?
thegamegAuthorUnsubmitted
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No, not necessary. I can commit this separately.

thegameg: No, not necessary. I can commit this separately.
case MachineOperand::MO_MCSymbol: case MachineOperand::MO_MCSymbol:
return getMCSymbol() == Other.getMCSymbol(); return getMCSymbol() == Other.getMCSymbol();
case MachineOperand::MO_CFIIndex: case MachineOperand::MO_CFIIndex:
return getCFIIndex() == Other.getCFIIndex(); return getCFIIndex() == Other.getCFIIndex();
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
return getMetadata() == Other.getMetadata(); return getMetadata() == Other.getMetadata();
case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_IntrinsicID:
return getIntrinsicID() == Other.getIntrinsicID(); return getIntrinsicID() == Other.getIntrinsicID();
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lineshash_code llvm::hash_value(const MachineOperand &MO) {
case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_IntrinsicID:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
case MachineOperand::MO_Predicate: case MachineOperand::MO_Predicate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
} }
llvm_unreachable("Invalid machine operand type"); llvm_unreachable("Invalid machine operand type");
} }
// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
// it.
static void tryToGetTargetInfo(const MachineOperand &MO,
const TargetRegisterInfo *&TRI,
const TargetIntrinsicInfo *&IntrinsicInfo) {
if (const MachineInstr *MI = MO.getParent()) {
if (const MachineBasicBlock *MBB = MI->getParent()) {
if (const MachineFunction *MF = MBB->getParent()) {
TRI = MF->getSubtarget().getRegisterInfo();
IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
}
}
}
}
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI, void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const { const TargetIntrinsicInfo *IntrinsicInfo) const {
ModuleSlotTracker DummyMST(nullptr); ModuleSlotTracker DummyMST(nullptr);
print(OS, DummyMST, TRI, IntrinsicInfo); print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
/*ShouldPrintRegisterTies=*/false,
/*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
} }
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
LLT TypeToPrint, bool PrintDef,
bool ShouldPrintRegisterTies,
unsigned TiedOperandIdx,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const { const TargetIntrinsicInfo *IntrinsicInfo) const {
switch (getType()) { tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
MatzeBUnsubmitted
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This feels a bit strange to me in cases where the user already specified TRI/IntrinsicInfo/...

MatzeB: This feels a bit strange to me in cases where the user already specified TRI/IntrinsicInfo/...
thegamegAuthorUnsubmitted
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Indeed, it was one of the questions I was having: should we assume that if the user is using the "complex" printing method then we're not trying to get the target info for them (and remove the default arguments to make it more obvious) ? In other words, should we only call tryToGetTargetInfo on the first ::print method (and obviously document this behavior and do the same for MI, MBB, MF) ?

thegameg: Indeed, it was one of the questions I was having: should we assume that if the user is using…
MatzeBUnsubmitted
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Yeah given that this is more of a convenience functionality rather than a core part of printing moving it to the other convenience print function makes sense to me.

MatzeB: Yeah given that this is more of a convenience functionality rather than a core part of printing…
case MachineOperand::MO_Register:
OS << printReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || switch (getType()) {
isInternalRead() || isEarlyClobber() || isTied()) { case MachineOperand::MO_Register: {
OS << '<'; unsigned Reg = getReg();
bool NeedComma = false;
if (isDef()) {
if (NeedComma)
OS << ',';
if (isEarlyClobber())
OS << "earlyclobber,";
if (isImplicit()) if (isImplicit())
OS << "imp-"; OS << (isDef() ? "implicit-def " : "implicit ");
else if (PrintDef && isDef())
// Print the 'def' flag only when the operand is defined after '='.
OS << "def"; OS << "def ";
NeedComma = true; if (isInternalRead())
// <def,read-undef> only makes sense when getSubReg() is set. OS << "internal ";
// Don't clutter the output otherwise. if (isDead())
if (isUndef() && getSubReg())
OS << ",read-undef";
} else if (isImplicit()) {
OS << "imp-use";
NeedComma = true;
}
if (isKill()) {
if (NeedComma)
OS << ',';
OS << "kill";
NeedComma = true;
}
if (isDead()) {
if (NeedComma)
OS << ',';
OS << "dead"; OS << "dead ";
NeedComma = true; if (isKill())
} OS << "killed ";
if (isUndef() && isUse()) { if (isUndef())
if (NeedComma)
OS << ',';
OS << "undef"; OS << "undef ";
NeedComma = true; if (isEarlyClobber())
OS << "early-clobber ";
if (isDebug())
OS << "debug-use ";
OS << printReg(Reg, TRI);
// Print the sub register.
if (unsigned SubReg = getSubReg()) {
if (TRI)
OS << '.' << TRI->getSubRegIndexName(SubReg);
else
OS << ".subreg" << SubReg;
}
// Print the register class / bank.
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
if (const MachineInstr *MI = getParent()) {
if (const MachineBasicBlock *MBB = MI->getParent()) {
if (const MachineFunction *MF = MBB->getParent()) {
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (!PrintDef || MRI.def_empty(Reg)) {
OS << ':';
OS << printRegClassOrBank(Reg, MRI, TRI);
} }
if (isInternalRead()) {
if (NeedComma)
OS << ',';
OS << "internal";
NeedComma = true;
} }
if (isTied()) {
if (NeedComma)
OS << ',';
OS << "tied";
if (TiedTo != 15)
OS << unsigned(TiedTo - 1);
} }
OS << '>';
} }
}
// Print ties.
if (ShouldPrintRegisterTies && isTied() && !isDef())
OS << "(tied-def " << TiedOperandIdx << ")";
// Print types.
if (TypeToPrint.isValid())
OS << '(' << TypeToPrint << ')';
break; break;
}
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
OS << getImm(); OS << getImm();
break; break;
case MachineOperand::MO_CImmediate: case MachineOperand::MO_CImmediate:
getCImm()->getValue().print(OS, false); getCImm()->getValue().print(OS, false);
break; break;
case MachineOperand::MO_FPImmediate: case MachineOperand::MO_FPImmediate:
if (getFPImm()->getType()->isFloatTy()) { if (getFPImm()->getType()->isFloatTy()) {
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesvoid MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
case MachineOperand::MO_BlockAddress: case MachineOperand::MO_BlockAddress:
OS << '<'; OS << '<';
getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST); getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
if (getOffset()) if (getOffset())
OS << "+" << getOffset(); OS << "+" << getOffset();
OS << '>'; OS << '>';
break; break;
case MachineOperand::MO_RegisterMask: { case MachineOperand::MO_RegisterMask: {
OS << "<regmask";
if (TRI) {
unsigned NumRegsInMask = 0; unsigned NumRegsInMask = 0;
unsigned NumRegsEmitted = 0; unsigned NumRegsEmitted = 0;
OS << "<regmask";
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
unsigned MaskWord = i / 32; unsigned MaskWord = i / 32;
unsigned MaskBit = i % 32; unsigned MaskBit = i % 32;
if (getRegMask()[MaskWord] & (1 << MaskBit)) { if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintRegMaskNumRegs < 0 || if (PrintRegMaskNumRegs < 0 ||
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
OS << " " << printReg(i, TRI); OS << " " << printReg(i, TRI);
NumRegsEmitted++; NumRegsEmitted++;
} }
NumRegsInMask++; NumRegsInMask++;
} }
} }
if (NumRegsEmitted != NumRegsInMask) if (NumRegsEmitted != NumRegsInMask)
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more..."; OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
} else {
OS << " ...";
}
OS << ">"; OS << ">";
break; break;
} }
case MachineOperand::MO_RegisterLiveOut: case MachineOperand::MO_RegisterLiveOut:
OS << "<regliveout>"; OS << "<regliveout>";
break; break;
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
OS << '<'; OS << '<';
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

lib/CodeGen/MachineSink.cpp

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
// BreakPHIEdge is true if all the uses are in the successor MBB being sunken // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
// into and they are all PHI nodes. In this case, machine-sink must break // into and they are all PHI nodes. In this case, machine-sink must break
// the critical edge first. e.g. // the critical edge first. e.g.
// //
// %bb.1: derived from LLVM BB %bb4.preheader // %bb.1: derived from LLVM BB %bb4.preheader
// Predecessors according to CFG: %bb.0 // Predecessors according to CFG: %bb.0
// ... // ...
// %reg16385<def> = DEC64_32r %reg16437, %eflags<imp-def,dead> // %reg16385 = DEC64_32r %reg16437, implicit dead %eflags
MatzeBUnsubmitted
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shouldn't this be implicit def dead

MatzeB: shouldn't this be `implicit def dead`
// ... // ...
// JE_4 <%bb.37>, %eflags<imp-use> // JE_4 <%bb.37>, implicit %eflags
// Successors according to CFG: %bb.37 %bb.2 // Successors according to CFG: %bb.37 %bb.2
// //
// %bb.2: derived from LLVM BB %bb.nph // %bb.2: derived from LLVM BB %bb.nph
// Predecessors according to CFG: %bb.0 %bb.1 // Predecessors according to CFG: %bb.0 %bb.1
// %reg16386<def> = PHI %reg16434, %bb.0, %reg16385, %bb.1 // %reg16386 = PHI %reg16434, %bb.0, %reg16385, %bb.1
BreakPHIEdge = true; BreakPHIEdge = true;
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
MachineInstr *UseInst = MO.getParent(); MachineInstr *UseInst = MO.getParent();
unsigned OpNo = &MO - &UseInst->getOperand(0); unsigned OpNo = &MO - &UseInst->getOperand(0);
MachineBasicBlock *UseBlock = UseInst->getParent(); MachineBasicBlock *UseBlock = UseInst->getParent();
if (!(UseBlock == MBB && UseInst->isPHI() && if (!(UseBlock == MBB && UseInst->isPHI() &&
UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) { UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
BreakPHIEdge = false; BreakPHIEdge = false;
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

lib/CodeGen/MachineVerifier.cpp

lib/CodeGen/RegAllocFast.cpp

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
if (MO.getReg() == LR.PhysReg) if (MO.getReg() == LR.PhysReg)
MO.setIsKill(); MO.setIsKill();
// else, don't do anything we are problably redefining a // else, don't do anything we are problably redefining a
// subreg of this register and given we don't track which // subreg of this register and given we don't track which
// lanes are actually dead, we cannot insert a kill flag here. // lanes are actually dead, we cannot insert a kill flag here.
// Otherwise we may end up in a situation like this: // Otherwise we may end up in a situation like this:
// ... = (MO) physreg:sub1, physreg <implicit-use, kill> // ... = (MO) physreg:sub1, implicit kill physreg
MatzeBUnsubmitted
Done
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killed

MatzeB: `killed`
// ... <== Here we would allow later pass to reuse physreg:sub1 // ... <== Here we would allow later pass to reuse physreg:sub1
// which is potentially wrong. // which is potentially wrong.
// LR:sub0 = ... // LR:sub0 = ...
// ... = LR.sub1 <== This is going to use physreg:sub1 // ... = LR.sub1 <== This is going to use physreg:sub1
} }
} }
/// Mark virtreg as no longer available. /// Mark virtreg as no longer available.
▲ Show 20 Lines • Show All 386 Lines • ▼ Show 20 Lines
MO.setIsKill(false); MO.setIsKill(false);
} else if (MO.isDead()) { } else if (MO.isDead()) {
DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
MO.setIsDead(false); MO.setIsDead(false);
} }
} else if (MO.isKill()) { } else if (MO.isKill()) {
// We must remove kill flags from uses of reloaded registers because the // We must remove kill flags from uses of reloaded registers because the
// register would be killed immediately, and there might be a second use: // register would be killed immediately, and there might be a second use:
// %foo = OR %x<kill>, %x // %foo = OR killed %x, %x
// This would cause a second reload of %x into a different register. // This would cause a second reload of %x into a different register.
DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
MO.setIsKill(false); MO.setIsKill(false);
} else if (MO.isDead()) { } else if (MO.isDead()) {
DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
MO.setIsDead(false); MO.setIsDead(false);
} }
assert(LRI->PhysReg && "Register not assigned"); assert(LRI->PhysReg && "Register not assigned");
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

lib/CodeGen/RegisterCoalescer.cpp

lib/CodeGen/RegisterScavenging.cpp

lib/CodeGen/SplitKit.cpp

lib/CodeGen/TargetRegisterInfo.cpp

lib/CodeGen/TwoAddressInstructionPass.cpp

lib/CodeGen/VirtRegMap.cpp

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

lib/Target/AArch64/AArch64InstrInfo.cpp

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

lib/Target/AMDGPU/CaymanInstructions.td

lib/Target/AMDGPU/EvergreenInstructions.td

lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

lib/Target/AMDGPU/SIFixWWMLiveness.cpp

lib/Target/AMDGPU/SIFoldOperands.cpp

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

lib/Target/ARM/ARMBaseInstrInfo.cpp

lib/Target/ARM/ARMExpandPseudoInsts.cpp

lib/Target/ARM/ARMISelLowering.cpp

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

lib/Target/BPF/BPFISelDAGToDAG.cpp

lib/Target/Hexagon/HexagonBlockRanges.cpp

lib/Target/Hexagon/HexagonConstPropagation.cpp

lib/Target/Hexagon/HexagonCopyToCombine.cpp

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

lib/Target/Hexagon/HexagonExpandCondsets.cpp

lib/Target/Hexagon/HexagonHardwareLoops.cpp

lib/Target/Hexagon/HexagonInstrInfo.cpp

lib/Target/Hexagon/HexagonNewValueJump.cpp

lib/Target/Hexagon/HexagonPeephole.cpp

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp

lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp

lib/Target/Hexagon/RDFGraph.h

lib/Target/Mips/MipsInstrInfo.cpp

lib/Target/NVPTX/NVPTXPeephole.cpp

lib/Target/PowerPC/PPCBranchCoalescing.cpp

lib/Target/PowerPC/PPCInstrInfo.cpp

lib/Target/PowerPC/PPCMIPeephole.cpp

lib/Target/PowerPC/PPCQPXLoadSplat.cpp

lib/Target/PowerPC/PPCVSXFMAMutate.cpp

lib/Target/SystemZ/SystemZElimCompare.cpp

lib/Target/X86/README-X86-64.txt

lib/Target/X86/X86FixupBWInsts.cpp

lib/Target/X86/X86InstrInfo.cpp

lib/Target/X86/X86VZeroUpper.cpp

test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir

test/CodeGen/AArch64/GlobalISel/verify-selected.mir

test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll

test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll

test/CodeGen/AArch64/arm64-csldst-mmo.ll

test/CodeGen/AArch64/arm64-dead-register-def-bug.ll

test/CodeGen/AArch64/arm64-fast-isel-rem.ll

test/CodeGen/AArch64/arm64-ldp-cluster.ll

test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll

test/CodeGen/AArch64/arm64-misched-memdep-bug.ll

test/CodeGen/AArch64/arm64-misched-multimmo.ll

test/CodeGen/AArch64/loh.mir

test/CodeGen/AArch64/machine-copy-prop.ll

test/CodeGen/AArch64/scheduledag-constreg.mir

test/CodeGen/AArch64/tailcall_misched_graph.ll

test/CodeGen/AMDGPU/llvm.dbg.value.ll

test/CodeGen/AMDGPU/schedule-regpressure.mir

test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll

test/CodeGen/ARM/2011-11-14-EarlyClobber.ll

test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll

test/CodeGen/ARM/Windows/vla-cpsr.ll

test/CodeGen/ARM/crash-greedy.ll

test/CodeGen/ARM/ifcvt-dead-def.ll

test/CodeGen/ARM/misched-copy-arm.ll

test/CodeGen/ARM/misched-int-basic-thumb2.mir

test/CodeGen/ARM/misched-int-basic.mir

test/CodeGen/ARM/sched-it-debug-nodes.mir

test/CodeGen/ARM/single-issue-r52.mir

test/CodeGen/ARM/subreg-remat.ll

test/CodeGen/ARM/vldm-liveness.mir

test/CodeGen/AVR/select-must-add-unconditional-jump.ll

test/CodeGen/Hexagon/branch-folder-hoist-kills.mir

test/CodeGen/Hexagon/post-inc-aa-metadata.ll

test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll

test/CodeGen/PowerPC/byval-agg-info.ll

test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

test/CodeGen/PowerPC/quadint-return.ll

test/CodeGen/SystemZ/pr32505.ll

test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir

test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll

test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll

test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll

test/CodeGen/X86/2010-04-08-CoalescerBug.ll

test/CodeGen/X86/2010-05-12-FastAllocKills.ll

test/CodeGen/X86/GlobalISel/add-scalar.ll

test/CodeGen/X86/GlobalISel/ext-x86-64.ll

test/CodeGen/X86/GlobalISel/ext.ll

test/CodeGen/X86/GlobalISel/gep.ll

test/CodeGen/X86/GlobalISel/x86_64-fallback.ll

test/CodeGen/X86/add-sub-nsw-nuw.ll

test/CodeGen/X86/add.ll

test/CodeGen/X86/addcarry.ll

test/CodeGen/X86/anyext.ll

test/CodeGen/X86/atomic-eflags-reuse.ll

test/CodeGen/X86/avx-cast.ll

test/CodeGen/X86/avx-cmp.ll

test/CodeGen/X86/avx-intrinsics-fast-isel.ll

test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll

test/CodeGen/X86/avx-vinsertf128.ll

test/CodeGen/X86/avx-vzeroupper.ll

test/CodeGen/X86/avx2-conversions.ll

test/CodeGen/X86/avx2-intrinsics-fast-isel.ll

test/CodeGen/X86/avx2-shift.ll

test/CodeGen/X86/avx2-vector-shifts.ll

test/CodeGen/X86/avx512-arith.ll

test/CodeGen/X86/avx512-build-vector.ll

test/CodeGen/X86/avx512-calling-conv.ll

test/CodeGen/X86/avx512-cmp-kor-sequence.ll

test/CodeGen/X86/avx512-cvt.ll

test/CodeGen/X86/avx512-ext.ll

test/CodeGen/X86/avx512-extract-subvector.ll

test/CodeGen/X86/avx512-hadd-hsub.ll

test/CodeGen/X86/avx512-insert-extract.ll

test/CodeGen/X86/avx512-insert-extract_i1.ll

test/CodeGen/X86/avx512-intrinsics-upgrade.ll

test/CodeGen/X86/avx512-intrinsics.ll

test/CodeGen/X86/avx512-mask-op.ll

test/CodeGen/X86/avx512-memfold.ll

test/CodeGen/X86/avx512-regcall-Mask.ll

test/CodeGen/X86/avx512-regcall-NoMask.ll

test/CodeGen/X86/avx512-schedule.ll

test/CodeGen/X86/avx512-select.ll

test/CodeGen/X86/avx512-shift.ll

test/CodeGen/X86/avx512-shuffles/partial_permute.ll

test/CodeGen/X86/avx512-trunc.ll

test/CodeGen/X86/avx512-vbroadcast.ll

test/CodeGen/X86/avx512-vec-cmp.ll

test/CodeGen/X86/avx512-vec3-crash.ll

test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

test/CodeGen/X86/avx512bw-mov.ll

test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

test/CodeGen/X86/avx512bwvl-intrinsics.ll

test/CodeGen/X86/avx512bwvl-vec-test-testn.ll

test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll

test/CodeGen/X86/avx512dq-intrinsics.ll

test/CodeGen/X86/avx512dq-mask-op.ll

test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll

test/CodeGen/X86/avx512dqvl-intrinsics.ll

test/CodeGen/X86/avx512f-vec-test-testn.ll

test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

test/CodeGen/X86/avx512vl-intrinsics.ll

test/CodeGen/X86/avx512vl-vec-cmp.ll

test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

test/CodeGen/X86/avx512vl-vec-test-testn.ll

test/CodeGen/X86/bitcast-and-setcc-128.ll

test/CodeGen/X86/bitcast-and-setcc-256.ll

test/CodeGen/X86/bitcast-and-setcc-512.ll

test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll

test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

test/CodeGen/X86/bitcast-int-to-vector-bool.ll

test/CodeGen/X86/bitcast-int-to-vector.ll

test/CodeGen/X86/bitcast-setcc-128.ll

test/CodeGen/X86/bitcast-setcc-256.ll

test/CodeGen/X86/bitcast-setcc-512.ll

test/CodeGen/X86/bitreverse.ll

test/CodeGen/X86/bmi-schedule.ll

test/CodeGen/X86/bmi.ll

test/CodeGen/X86/bool-simplify.ll

test/CodeGen/X86/bool-vector.ll

test/CodeGen/X86/broadcastm-lowering.ll

test/CodeGen/X86/bypass-slow-division-32.ll

test/CodeGen/X86/bypass-slow-division-64.ll

test/CodeGen/X86/clz.ll

test/CodeGen/X86/cmov-into-branch.ll

test/CodeGen/X86/cmov-promotion.ll

test/CodeGen/X86/cmov.ll

test/CodeGen/X86/cmovcmov.ll

test/CodeGen/X86/coalescer-dce.ll

test/CodeGen/X86/combine-abs.ll

test/CodeGen/X86/compress_expand.ll

test/CodeGen/X86/critical-edge-split-2.ll

test/CodeGen/X86/ctpop-combine.ll

test/CodeGen/X86/dagcombine-cse.ll

test/CodeGen/X86/divide-by-constant.ll

test/CodeGen/X86/divrem.ll

test/CodeGen/X86/divrem8_ext.ll

test/CodeGen/X86/extractelement-index.ll

test/CodeGen/X86/f16c-intrinsics-fast-isel.ll

test/CodeGen/X86/fast-isel-cmp.ll

test/CodeGen/X86/fast-isel-sext-zext.ll

test/CodeGen/X86/fast-isel-shift.ll

test/CodeGen/X86/fixup-bw-copy.ll

test/CodeGen/X86/fixup-bw-inst.mir

test/CodeGen/X86/gpr-to-mask.ll

test/CodeGen/X86/half.ll

test/CodeGen/X86/handle-move.ll

test/CodeGen/X86/horizontal-reduce-smax.ll

test/CodeGen/X86/horizontal-reduce-smin.ll

test/CodeGen/X86/horizontal-reduce-umax.ll

test/CodeGen/X86/horizontal-reduce-umin.ll

test/CodeGen/X86/iabs.ll

test/CodeGen/X86/illegal-bitfield-loadstore.ll

test/CodeGen/X86/imul.ll

test/CodeGen/X86/inline-asm-fpstack.ll

test/CodeGen/X86/lea-3.ll

test/CodeGen/X86/lea-opt-cse3.ll

test/CodeGen/X86/lea32-schedule.ll

test/CodeGen/X86/liveness-local-regalloc.ll

test/CodeGen/X86/loop-search.ll

test/CodeGen/X86/lzcnt-schedule.ll

test/CodeGen/X86/lzcnt-zext-cmp.ll

test/CodeGen/X86/machine-cp.ll

test/CodeGen/X86/machine-cse.ll

test/CodeGen/X86/masked_gather_scatter.ll

test/CodeGen/X86/masked_memop.ll

test/CodeGen/X86/misched-copy.ll

test/CodeGen/X86/movmsk.ll

test/CodeGen/X86/mul-constant-i16.ll

test/CodeGen/X86/mul-constant-i32.ll

test/CodeGen/X86/mul-constant-result.ll

test/CodeGen/X86/negate-i1.ll

test/CodeGen/X86/norex-subreg.ll

test/CodeGen/X86/oddshuffles.ll

test/CodeGen/X86/or-lea.ll

test/CodeGen/X86/phys_subreg_coalesce-3.ll

test/CodeGen/X86/pmul.ll

test/CodeGen/X86/popcnt-schedule.ll

test/CodeGen/X86/popcnt.ll

test/CodeGen/X86/pr22970.ll

test/CodeGen/X86/pr28173.ll

test/CodeGen/X86/pr28560.ll

test/CodeGen/X86/pr29061.ll

test/CodeGen/X86/pr32282.ll

test/CodeGen/X86/pr32329.ll

test/CodeGen/X86/pr32345.ll

test/CodeGen/X86/pr34653.ll

test/CodeGen/X86/promote-vec3.ll

test/CodeGen/X86/psubus.ll

test/CodeGen/X86/reduce-trunc-shl.ll

test/CodeGen/X86/remat-phys-dead.ll

test/CodeGen/X86/sar_fold64.ll

test/CodeGen/X86/schedule-x86_64.ll

test/CodeGen/X86/select.ll

test/CodeGen/X86/select_const.ll

test/CodeGen/X86/setcc-lowering.ll

test/CodeGen/X86/sext-i1.ll

test/CodeGen/X86/shift-combine.ll

test/CodeGen/X86/shift-double.ll

test/CodeGen/X86/shrink-compare.ll

test/CodeGen/X86/shuffle-vs-trunc-256.ll

test/CodeGen/X86/sse2-schedule.ll

test/CodeGen/X86/sse42-schedule.ll

test/CodeGen/X86/subvector-broadcast.ll

test/CodeGen/X86/tbm-intrinsics-fast-isel.ll

test/CodeGen/X86/tbm_patterns.ll

test/CodeGen/X86/umul-with-overflow.ll

test/CodeGen/X86/urem-i8-constant.ll

test/CodeGen/X86/urem-power-of-two.ll

test/CodeGen/X86/vec_cmp_uint-128.ll

test/CodeGen/X86/vec_fp_to_int.ll

test/CodeGen/X86/vec_ins_extract-1.ll

test/CodeGen/X86/vec_insert-4.ll

test/CodeGen/X86/vec_insert-5.ll

test/CodeGen/X86/vec_insert-8.ll

test/CodeGen/X86/vec_insert-mmx.ll

test/CodeGen/X86/vec_int_to_fp.ll

test/CodeGen/X86/vec_minmax_sint.ll

test/CodeGen/X86/vec_minmax_uint.ll

test/CodeGen/X86/vec_ss_load_fold.ll

test/CodeGen/X86/vector-bitreverse.ll

test/CodeGen/X86/vector-compare-all_of.ll

test/CodeGen/X86/vector-compare-any_of.ll

test/CodeGen/X86/vector-compare-results.ll

test/CodeGen/X86/vector-extend-inreg.ll

test/CodeGen/X86/vector-half-conversions.ll

test/CodeGen/X86/vector-lzcnt-128.ll

test/CodeGen/X86/vector-lzcnt-256.ll

test/CodeGen/X86/vector-popcnt-128.ll

test/CodeGen/X86/vector-popcnt-256.ll

test/CodeGen/X86/vector-rotate-128.ll

test/CodeGen/X86/vector-rotate-256.ll

test/CodeGen/X86/vector-sext.ll

test/CodeGen/X86/vector-shift-ashr-128.ll

test/CodeGen/X86/vector-shift-ashr-256.ll

test/CodeGen/X86/vector-shift-lshr-128.ll

test/CodeGen/X86/vector-shift-lshr-256.ll

test/CodeGen/X86/vector-shift-shl-128.ll

test/CodeGen/X86/vector-shift-shl-256.ll

test/CodeGen/X86/vector-shuffle-256-v4.ll

test/CodeGen/X86/vector-shuffle-512-v16.ll

test/CodeGen/X86/vector-shuffle-512-v8.ll

test/CodeGen/X86/vector-shuffle-avx512.ll

test/CodeGen/X86/vector-shuffle-combining-avx2.ll

test/CodeGen/X86/vector-shuffle-v1.ll

test/CodeGen/X86/vector-shuffle-variable-128.ll

test/CodeGen/X86/vector-shuffle-variable-256.ll

test/CodeGen/X86/vector-trunc-math.ll

test/CodeGen/X86/vector-trunc.ll

test/CodeGen/X86/vector-tzcnt-128.ll

test/CodeGen/X86/vector-tzcnt-256.ll

test/CodeGen/X86/vpshufbitqbm-intrinsics.ll

test/CodeGen/X86/vselect-pcmp.ll

test/CodeGen/X86/widen_bitops-0.ll

test/CodeGen/X86/x86-interleaved-access.ll

test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
# Let's verify that the slot index ranges for the unused variables argc/argv, # Let's verify that the slot index ranges for the unused variables argc/argv,
# connected to physical regs %edi and %rsi, does not overlap with the ranges # connected to physical regs %edi and %rsi, does not overlap with the ranges
# for %2 and %3. The register allocator is actually allocating the # for %2 and %3. The register allocator is actually allocating the
# virtual registers # to %edi and %esi, so the ranges for argc/argv should # virtual registers # to %edi and %esi, so the ranges for argc/argv should
# not cover the whole BB. # not cover the whole BB.
# #
# CHECKDBG-LABEL: ********** EMITTING LIVE DEBUG VARIABLES ********** # CHECKDBG-LABEL: ********** EMITTING LIVE DEBUG VARIABLES **********
# CHECKDBG-NEXT: !"argc,5" [0B;0e):0 Loc0=%edi # CHECKDBG-NEXT: !"argc,5" [0B;0e):0 Loc0=debug-use %edi
thegamegAuthorUnsubmitted
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I don't know how much we want this debug-use to show up here. What do you think @aprantl?

thegameg: I don't know how much we want this `debug-use` to show up here. What do you think @aprantl?
MatzeBUnsubmitted
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The MachineOperand isDebug flag is so obvious (it is exactly set on the operands of DBG_VALUE instructions and nowhere else) and is more of a shortcut to avoid a few MachineOperand::getParent()->isDebug() calls rather than a flag that contains real information that I'd vote to not print or parse it. (And just compute it when parsing .mir I believe this is already happening anyway). Of course we don't necessarily need to make this change in this patch.

MatzeB: The MachineOperand isDebug flag is so obvious (it is exactly set on the operands of DBG_VALUE…
# CHECKDBG-NEXT: [0B;0e):0 %bb.0-160B # CHECKDBG-NEXT: [0B;0e):0 %bb.0-160B
# CHECKDBG-NEXT: !"argv,5" [0B;0e):0 Loc0=%rsi # CHECKDBG-NEXT: !"argv,5" [0B;0e):0 Loc0=debug-use %rsi
# CHECKDBG-NEXT: [0B;0e):0 %bb.0-160B # CHECKDBG-NEXT: [0B;0e):0 %bb.0-160B
# CHECKDBG-NEXT: !"a0,7" [16r;64r):0 Loc0=%2 # CHECKDBG-NEXT: !"a0,7" [16r;64r):0 Loc0=debug-use %2
# CHECKDBG-NEXT: [16r;64r):0 %bb.0-160B # CHECKDBG-NEXT: [16r;64r):0 %bb.0-160B
# CHECKDBG-NEXT: !"a1,8" [32r;80r):0 Loc0=%3 # CHECKDBG-NEXT: !"a1,8" [32r;80r):0 Loc0=debug-use %3
# CHECKDBG-NEXT: [32r;80r):0 %bb.0-160B # CHECKDBG-NEXT: [32r;80r):0 %bb.0-160B

test/MC/AArch64/arm64-leaf-compact-unwind.s

unittests/CodeGen/MachineOperandTest.cpp