[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

[thegameg]

Summary

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

Work towards the unification of MIR and debug output by refactoring the interfaces.

For MachineOperand::print, keep a simple version that can be easily called from dump(), and a more complex one which will be called from both the MIRPrinter and MachineInstr::print.

Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr).

[MatzeB]

Looks good, but I assume this is incomplete and cannot be pushed like this?

lib/CodeGen/MachineInstr.cpp

1245

I think in case of MachineInstr::print() (at least by default) we should print all register ties on machine operands. Not sure what your plans with this flag are anyway as it's not really used by MachineOperand::print yet?

lib/CodeGen/MachineOperand.cpp

261–276

Is this necessary for the printing changes?

368

This feels a bit strange to me in cases where the user already specified TRI/IntrinsicInfo/...

[thegameg]

• Move implementation from the MIRPrinter to MachineOperand.
• Update tests.

[thegameg]

lib/CodeGen/LiveVariables.cpp

238 ↗

(On Diff #125695)

I also assumed <imp-kill> here meant implicit-use killed.

lib/CodeGen/MachineOperand.cpp

261–276

No, not necessary. I can commit this separately.

368

Indeed, it was one of the questions I was having: should we assume that if the user is using the "complex" printing method then we're not trying to get the target info for them (and remove the default arguments to make it more obvious) ? In other words, should we only call tryToGetTargetInfo on the first ::print method (and obviously document this behavior and do the same for MI, MBB, MF) ?

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

156 ↗

(On Diff #125695)

I don't know how much we want this debug-use to show up here. What do you think @aprantl?

[MatzeB]

LGTM, thanks for thoroughly replacing the syntax in all the comments.

include/llvm/CodeGen/MachineBasicBlock.h

705 ↗

(On Diff #125695)

too much automatic replacements :) (and too fancy writing in the original comment)

lib/CodeGen/LiveVariables.cpp

238 ↗

(On Diff #125695)

yes it's an implicit use with a kill flag. Is there anything confusing here?

I know the syntax used in the comments isn't always consistent. We also have this strange thing in .mir where implicit-def is just another word for implicit def (but that is something to fix another day).

lib/CodeGen/MachineOperand.cpp

368

Yeah given that this is more of a convenience functionality rather than a core part of printing moving it to the other convenience print function makes sense to me.

lib/CodeGen/MachineSink.cpp

249 ↗

(On Diff #125695)

shouldn't this be implicit def dead

lib/CodeGen/RegAllocFast.cpp

275 ↗

(On Diff #125695)

killed

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

156 ↗

(On Diff #125695)

The MachineOperand isDebug flag is so obvious (it is exactly set on the operands of DBG_VALUE instructions and nowhere else) and is more of a shortcut to avoid a few MachineOperand::getParent()->isDebug() calls rather than a flag that contains real information that I'd vote to not print or parse it. (And just compute it when parsing .mir I believe this is already happening anyway). Of course we don't necessarily need to make this change in this patch.

[thegameg]

Committed as r320022 [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

lib/CodeGen/LiveVariables.cpp

238 ↗

(On Diff #125695)

Right, I was wondering why not <imp-use,kill>.

include/llvm/CodeGen/MachineInstr.h

 class DILocalVariable;
 class MachineBasicBlock;
 class MachineFunction;
 class MachineMemOperand;
 class MachineRegisterInfo;
 class ModuleSlotTracker;
 class raw_ostream;
 template <typename T> class SmallVectorImpl;
+class SmallBitVector;
 class StringRef;
 class TargetInstrInfo;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 
 //===----------------------------------------------------------------------===//
 /// Representation of each machine instruction.
 ///

   bool allDefsAreDead() const;
 
   /// Copy implicit register operands from specified
   /// instruction to this instruction.
   void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
 
   /// Debugging support
   /// @{
+  /// Determine the generic type to be printed (if needed) on uses and defs.
+  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
+                     const MachineRegisterInfo &MRI) const;
+
+  /// Return true when an instruction has tied register that can't be determined
+  /// by the instruction's descriptor. This is useful for MIR printing, to
+  /// determine whether we need to print the ties or not.
+  bool hasComplexRegisterTies() const;
+
   /// Print this MI to \p OS.
   /// Only print the defs and the opcode if \p SkipOpers is true.
   /// Otherwise, also print operands if \p SkipDebugLoc is true.
   /// Otherwise, also print the debug loc, with a terminating newline.
   /// \p TII is used to print the opcode name.  If it's not present, but the
   /// MI is in a function, the opcode will be printed using the function's TII.
   void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
              const TargetInstrInfo *TII = nullptr) const;

include/llvm/CodeGen/MachineOperand.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
 #define LLVM_CODEGEN_MACHINEOPERAND_H
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/LowLevelTypeImpl.h"
 #include <cassert>
 
 namespace llvm {
 
 class BlockAddress;
 class ConstantFP;
 class ConstantInt;
 class GlobalValue;
public:
   /// MachineInstr, the parent pointer must be cleared.
   ///
   /// Never call clearParent() on an operand in a MachineInstr.
   ///
   void clearParent() { ParentMI = nullptr; }
 
   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
-  void print(raw_ostream &os, ModuleSlotTracker &MST,
-             const TargetRegisterInfo *TRI = nullptr,
+  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
+             bool PrintDef, bool ShouldPrintRegisterTies,
+             unsigned TiedOperandIdx, const TargetRegisterInfo *TRI = nullptr,
              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
   void dump() const;
 
   //===--------------------------------------------------------------------===//
   // Accessors that tell you what kind of MachineOperand you're looking at.
   //===--------------------------------------------------------------------===//
 
   /// isReg - Tests if this is a MO_Register operand.
if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
         LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
                              MachineOperand::MO_Tombstone))
       return LHS.getType() == RHS.getType();
     return LHS.isIdenticalTo(RHS);
   }
 };
 
 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
-  MO.print(OS, nullptr);
+  MO.print(OS);
   return OS;
 }
 
 // See friend declaration above. This additional declaration is required in
 // order to compile LLVM with IBM xlC compiler.
 hash_code hash_value(const MachineOperand &MO);
 } // namespace llvm
 
 #endif

include/llvm/CodeGen/TargetRegisterInfo.h

 ///
 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
 
 /// \brief Create Printable object to print virtual registers and physical
 /// registers on a \ref raw_ostream.
 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
 
+/// \brief Create Printable object to print register classes or register banks
+/// on a \ref raw_ostream.
+Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
+                              const TargetRegisterInfo *TRI);
+
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H

lib/CodeGen/MIRPrinter.cpp

public:
   void print(const MachineInstr &MI);
   void printIRBlockReference(const BasicBlock &BB);
   void printIRValueReference(const Value &V);
   void printStackObjectReference(int FrameIndex);
   void printOffset(int64_t Offset);
   void printTargetFlags(const MachineOperand &Op);
   void print(const MachineInstr &MI, unsigned OpIdx,
              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
-             LLT TypeToPrint, bool IsDef = false);
+             LLT TypeToPrint, bool PrintDef = true);
   void print(const LLVMContext &Context, const TargetInstrInfo &TII,
              const MachineMemOperand &Op);
   void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
 
   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
 };
 
 } // end namespace llvm
if (RegMask[I / 32] & (1u << (I % 32))) {
       OS << printReg(I, TRI);
       IsRegInRegMaskFound = true;
     }
   }
 
   OS << ')';
 }
 
-static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
-                                const MachineRegisterInfo &RegInfo,
-                                const TargetRegisterInfo *TRI) {
-  if (RegInfo.getRegClassOrNull(Reg))
-    OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
-  else if (RegInfo.getRegBankOrNull(Reg))
-    OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
-  else {
-    OS << "_";
-    assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
-           "Generic registers must have a valid type");
-  }
-}
-
 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
                                 const MachineRegisterInfo &RegInfo,
                                 const TargetRegisterInfo *TRI) {
   raw_string_ostream OS(Dest.Value);
-  printRegClassOrBank(Reg, OS, RegInfo, TRI);
+  OS << printRegClassOrBank(Reg, RegInfo, TRI);
 }
 
 
 void MIRPrinter::convert(yaml::MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo,
                          const TargetRegisterInfo *TRI) {
   MF.TracksRegLiveness = RegInfo.tracksLiveness();
 
   // Print the virtual register definitions.
   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     yaml::VirtualRegisterDefinition VReg;
     VReg.ID = I;
-    printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
+    ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
     if (PreferredReg)
       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
     MF.VirtualRegisters.push_back(VReg);
   }
 
   // Print the live ins.
   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
       IsInBundle = true;
     }
     OS << "\n";
   }
   if (IsInBundle)
     OS.indent(2) << "}\n";
 }
 
-/// Return true when an instruction has tied register that can't be determined
-/// by the instruction's descriptor.
-static bool hasComplexRegisterTies(const MachineInstr &MI) {
-  const MCInstrDesc &MCID = MI.getDesc();
-  for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
-    const auto &Operand = MI.getOperand(I);
-    if (!Operand.isReg() || Operand.isDef())
-      // Ignore the defined registers as MCID marks only the uses as tied.
-      continue;
-    int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
-    int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
-    if (ExpectedTiedIdx != TiedIdx)
-      return true;
-  }
-  return false;
-}
-
-static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
-                          SmallBitVector &PrintedTypes,
-                          const MachineRegisterInfo &MRI) {
-  const MachineOperand &Op = MI.getOperand(OpIdx);
-  if (!Op.isReg())
-    return LLT{};
-
-  if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
-    return MRI.getType(Op.getReg());
-
-  auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
-  if (!OpInfo.isGenericType())
-    return MRI.getType(Op.getReg());
-
-  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
-    return LLT{};
-
-  PrintedTypes.set(OpInfo.getGenericTypeIndex());
-  return MRI.getType(Op.getReg());
-}
-
 void MIPrinter::print(const MachineInstr &MI) {
   const auto *MF = MI.getMF();
   const auto &MRI = MF->getRegInfo();
   const auto &SubTarget = MF->getSubtarget();
   const auto *TRI = SubTarget.getRegisterInfo();
   assert(TRI && "Expected target register info");
   const auto *TII = SubTarget.getInstrInfo();
   assert(TII && "Expected target instruction info");
   if (MI.isCFIInstruction())
     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
 
   SmallBitVector PrintedTypes(8);
-  bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
+  bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
   unsigned I = 0, E = MI.getNumOperands();
   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
          !MI.getOperand(I).isImplicit();
        ++I) {
     if (I)
       OS << ", ";
     print(MI, I, TRI, ShouldPrintRegisterTies,
-          getTypeToPrint(MI, I, PrintedTypes, MRI),
-          /*IsDef=*/true);
+          MI.getTypeToPrint(I, PrintedTypes, MRI),
+          /*PrintDef=*/false);
   }
 
   if (I)
     OS << " = ";
   if (MI.getFlag(MachineInstr::FrameSetup))
     OS << "frame-setup ";
   OS << TII->getName(MI.getOpcode());
   if (I < E)
     OS << ' ';
 
   bool NeedComma = false;
   for (; I < E; ++I) {
     if (NeedComma)
       OS << ", ";
     print(MI, I, TRI, ShouldPrintRegisterTies,
-          getTypeToPrint(MI, I, PrintedTypes, MRI));
+          MI.getTypeToPrint(I, PrintedTypes, MRI));
     NeedComma = true;
   }
 
   if (MI.getDebugLoc()) {
     if (NeedComma)
       OS << ',';
     OS << " debug-location ";
     MI.getDebugLoc()->printAsOperand(OS, MST);
for (const auto &I : Indices) {
     }
   }
   return nullptr;
 }
 
 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
                       const TargetRegisterInfo *TRI,
                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
-                      bool IsDef) {
+                      bool PrintDef) {
   const MachineOperand &Op = MI.getOperand(OpIdx);
   printTargetFlags(Op);
   switch (Op.getType()) {
   case MachineOperand::MO_Register: {
     unsigned Reg = Op.getReg();
     if (Op.isImplicit())
       OS << (Op.isDef() ? "implicit-def " : "implicit ");
-    else if (!IsDef && Op.isDef())
+    else if (PrintDef && Op.isDef())
       // Print the 'def' flag only when the operand is defined after '='.
       OS << "def ";
     if (Op.isInternalRead())
       OS << "internal ";
     if (Op.isDead())
       OS << "dead ";
     if (Op.isKill())
       OS << "killed ";
     if (Op.isUndef())
       OS << "undef ";
     if (Op.isEarlyClobber())
       OS << "early-clobber ";
     if (Op.isDebug())
       OS << "debug-use ";
     OS << printReg(Reg, TRI);
     // Print the sub register.
     if (Op.getSubReg() != 0)
       OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
       const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
-      if (IsDef || MRI.def_empty(Reg)) {
+      if (!PrintDef || MRI.def_empty(Reg)) {
         OS << ':';
-        printRegClassOrBank(Reg, OS, MRI, TRI);
+        OS << printRegClassOrBank(Reg, MRI, TRI);
       }
     }
     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")";
     if (TypeToPrint.isValid())
       OS << '(' << TypeToPrint << ')';
     break;
   }

lib/CodeGen/MachineInstr.cpp

 
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/Hashing.h"
 #include "llvm/ADT/None.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/Loads.h"
 #include "llvm/Analysis/MemoryLocation.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
void MachineInstr::copyImplicitOps(MachineFunction &MF,
   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
        i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
       addOperand(MF, MO);
   }
 }
 
+bool MachineInstr::hasComplexRegisterTies() const {
+  const MCInstrDesc &MCID = getDesc();
+  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
+    const auto &Operand = getOperand(I);
+    if (!Operand.isReg() || Operand.isDef())
+      // Ignore the defined registers as MCID marks only the uses as tied.
+      continue;
+    int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
+    int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
+    if (ExpectedTiedIdx != TiedIdx)
+      return true;
+  }
+  return false;
+}
+
+LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
+                                 const MachineRegisterInfo &MRI) const {
+  const MachineOperand &Op = getOperand(OpIdx);
+  if (!Op.isReg())
+    return LLT{};
+
+  if (isVariadic() || OpIdx >= getNumExplicitOperands())
+    return MRI.getType(Op.getReg());
+
+  auto &OpInfo = getDesc().OpInfo[OpIdx];
+  if (!OpInfo.isGenericType())
+    return MRI.getType(Op.getReg());
+
+  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
+    return LLT{};
+
+  PrintedTypes.set(OpInfo.getGenericTypeIndex());
+  return MRI.getType(Op.getReg());
+}
+
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-LLVM_DUMP_METHOD void MachineInstr::dump() const {
+LLVM_DUMP_METHOD void
+MachineInstr::dump() const {
   dbgs() << "  ";
   print(dbgs());
 }
 #endif
 
 void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
                          const TargetInstrInfo *TII) const {
   const Module *M = nullptr;
if (MF) {
         TII = MF->getSubtarget().getInstrInfo();
       IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
     }
   }
 
   // Save a list of virtual registers.
   SmallVector<unsigned, 8> VirtRegs;
 
+  SmallBitVector PrintedTypes(8);
+  bool ShouldPrintRegisterTies = hasComplexRegisterTies();
+  auto getTiedOperandIdx = [&](unsigned OpIdx) {
+    if (!ShouldPrintRegisterTies)
+      return 0U;
+    const MachineOperand &MO = getOperand(OpIdx);
+    if (MO.isReg() && MO.isTied() && !MO.isDef())
+      return findTiedOperandIdx(OpIdx);
+    return 0U;
+  };
   // Print explicitly defined operands on the left of an assignment syntax.
   unsigned StartOp = 0, e = getNumOperands();
   for (; StartOp < e && getOperand(StartOp).isReg() &&
-         getOperand(StartOp).isDef() &&
-         !getOperand(StartOp).isImplicit();
+         getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit();
        ++StartOp) {
-    if (StartOp != 0) OS << ", ";
-    getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
+    if (StartOp != 0)
+      OS << ", ";
+    LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
+    unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
+    getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false,
+                              ShouldPrintRegisterTies, TiedOperandIdx, TRI,
+                              IntrinsicInfo);
     unsigned Reg = getOperand(StartOp).getReg();
     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
       VirtRegs.push_back(Reg);
       LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
       if (Ty.isValid())
         OS << '(' << Ty << ')';
     }
   }
void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
   // Print the rest of the operands.
   bool FirstOp = true;
   unsigned AsmDescOp = ~0u;
   unsigned AsmOpCount = 0;
 
   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
     // Print asm string.
     OS << " ";
-    getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
+    const unsigned OpIdx = InlineAsm::MIOp_AsmString;
+    LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
+    unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
+    getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true,
+                            ShouldPrintRegisterTies, TiedOperandIdx, TRI,
+                            IntrinsicInfo);
 
     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
       OS << " [sideeffect]";
     if (ExtraInfo & InlineAsm::Extra_MayLoad)
       OS << " [mayload]";
     if (ExtraInfo & InlineAsm::Extra_MayStore)
if (i < getDesc().NumOperands) {
       if (MCOI.isOptionalDef())
         OS << "opt:";
     }
     if (isDebugValue() && MO.isMetadata()) {
       // Pretty print DBG_VALUE instructions.
       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
       if (DIV && !DIV->getName().empty())
         OS << "!\"" << DIV->getName() << '\"';
-      else
-        MO.print(OS, MST, TRI);
+      else {
+        LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
+        unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
+        MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
+                 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
+      }
     } else if (TRI && (isInsertSubreg() || isRegSequence() ||
                        (isSubregToReg() && i == 3)) && MO.isImm()) {
       OS << TRI->getSubRegIndexName(MO.getImm());
     } else if (i == AsmDescOp && MO.isImm()) {
       // Pretty print the inline asm operand descriptor.
       OS << '$' << AsmOpCount++;
       unsigned Flag = MO.getImm();
       switch (InlineAsm::getKind(Flag)) {
if (isDebugValue() && MO.isMetadata()) {
       unsigned TiedTo = 0;
       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
         OS << " tiedto:$" << TiedTo;
 
       OS << ']';
 
       // Compute the index of the next operand descriptor.
       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
-    } else
-      MO.print(OS, MST, TRI);
+    } else {
+      LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
+      unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
+      MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, ShouldPrintRegisterTies,
+               TiedOperandIdx, TRI, IntrinsicInfo);
+    }
   }
 
   bool HaveSemi = false;
   const unsigned PrintableFlags = FrameSetup | FrameDestroy;
   if (Flags & PrintableFlags) {
     if (!HaveSemi) {
       OS << ";";
       HaveSemi = true;

lib/CodeGen/MachineOperand.cpp

 /// \file Methods common to all machine operands.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Analysis/Loads.h"
 #include "llvm/CodeGen/MIRPrinter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetIntrinsicInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/ModuleSlotTracker.h"
+#include "llvm/Target/TargetIntrinsicInfo.h"
+#include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 
 static cl::opt<int>
     PrintRegMaskNumRegs("print-regmask-num-regs",
                         cl::desc("Number of registers to limit to when "
                                  "printing regmask operands in IR dumps. "
                                  "unlimited = -1"),
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
   case MachineOperand::MO_RegisterMask:
   case MachineOperand::MO_RegisterLiveOut: {
     // Shallow compare of the two RegMasks
     const uint32_t *RegMask = getRegMask();
     const uint32_t *OtherRegMask = Other.getRegMask();
     if (RegMask == OtherRegMask)
       return true;
 
+    if (const MachineInstr *MI = getParent()) {
+      if (const MachineBasicBlock *MBB = MI->getParent()) {
+        if (const MachineFunction *MF = MBB->getParent()) {
           // Calculate the size of the RegMask
-    const MachineFunction *MF = getParent()->getMF();
           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
           unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
 
           // Deep compare of the two RegMasks
           return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
         }
+      }
+    }
+    // We don't know the size of the RegMask, so we can't deep compare the two
+    // reg masks.
+    return false;
+  }
   case MachineOperand::MO_MCSymbol:
     return getMCSymbol() == Other.getMCSymbol();
   case MachineOperand::MO_CFIIndex:
     return getCFIIndex() == Other.getCFIIndex();
   case MachineOperand::MO_Metadata:
     return getMetadata() == Other.getMetadata();
   case MachineOperand::MO_IntrinsicID:
     return getIntrinsicID() == Other.getIntrinsicID();
hash_code llvm::hash_value(const MachineOperand &MO) {
   case MachineOperand::MO_IntrinsicID:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
   case MachineOperand::MO_Predicate:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
   }
   llvm_unreachable("Invalid machine operand type");
 }
 
+// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
+// it.
+static void tryToGetTargetInfo(const MachineOperand &MO,
+                               const TargetRegisterInfo *&TRI,
+                               const TargetIntrinsicInfo *&IntrinsicInfo) {
+  if (const MachineInstr *MI = MO.getParent()) {
+    if (const MachineBasicBlock *MBB = MI->getParent()) {
+     if (const MachineFunction *MF = MBB->getParent()) {
+       TRI = MF->getSubtarget().getRegisterInfo();
+       IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
+     }
+    }
+  }
+}
+
 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   ModuleSlotTracker DummyMST(nullptr);
-  print(OS, DummyMST, TRI, IntrinsicInfo);
+  print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
+        /*ShouldPrintRegisterTies=*/false,
+        /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 }
 
 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
+                           LLT TypeToPrint, bool PrintDef,
+                           bool ShouldPrintRegisterTies,
+                           unsigned TiedOperandIdx,
                            const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
+  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
+
   switch (getType()) {
   case MachineOperand::MO_Register:
     OS << printReg(getReg(), TRI, getSubReg());
 
     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
         isInternalRead() || isEarlyClobber() || isTied()) {
       OS << '<';
       bool NeedComma = false;
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
   case MachineOperand::MO_BlockAddress:
     OS << '<';
     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
     if (getOffset())
       OS << "+" << getOffset();
     OS << '>';
     break;
   case MachineOperand::MO_RegisterMask: {
+    OS << "<regmask";
+    if (TRI) {
       unsigned NumRegsInMask = 0;
       unsigned NumRegsEmitted = 0;
-    OS << "<regmask";
       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
         unsigned MaskWord = i / 32;
         unsigned MaskBit = i % 32;
         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
           if (PrintRegMaskNumRegs < 0 ||
               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
             OS << " " << printReg(i, TRI);
             NumRegsEmitted++;
           }
           NumRegsInMask++;
         }
       }
       if (NumRegsEmitted != NumRegsInMask)
         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
+    } else {
+      OS << " ...";
+    }
     OS << ">";
     break;
   }
   case MachineOperand::MO_RegisterLiveOut:
     OS << "<regliveout>";
     break;
   case MachineOperand::MO_Metadata:
     OS << '<';

lib/CodeGen/TargetRegisterInfo.cpp

return Printable([Unit, TRI](raw_ostream &OS) {
     if (TRI && TRI->isVirtualRegister(Unit)) {
       OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
     } else {
       OS << printRegUnit(Unit, TRI);
     }
   });
 }
 
+Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
+                              const TargetRegisterInfo *TRI) {
+  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
+    if (RegInfo.getRegClassOrNull(Reg))
+      OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
+    else if (RegInfo.getRegBankOrNull(Reg))
+      OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
+    else {
+      OS << "_";
+      assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
+             "Generic registers must have a valid type");
+    }
+  });
+}
+
 } // end namespace llvm
 
 /// getAllocatableClass - Return the maximal subclass of the given register
 /// class that is alloctable, or NULL.
 const TargetRegisterClass *
 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
   if (!RC || RC->isAllocatable())
     return RC;

unittests/CodeGen/MachineOperandTest.cpp

 //===- MachineOperandTest.cpp ---------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/Support/raw_ostream.h"
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 namespace {
 
 TEST(MachineOperandTest, ChangeToTargetIndexTest) {
   // Creating a MachineOperand to change it to TargetIndex
TEST(MachineOperandTest, ChangeToTargetIndexTest) {
   // Checking that the mutation to TargetIndex happened
   // correctly.
   ASSERT_TRUE(MO.isTargetIndex());
   ASSERT_TRUE(MO.getIndex() == 74);
   ASSERT_TRUE(MO.getOffset() == 57);
   ASSERT_TRUE(MO.getTargetFlags() == 12);
 }
 
+TEST(MachineOperandTest, PrintRegisterMask) {
+  uint32_t Dummy;
+  MachineOperand MO = MachineOperand::CreateRegMask(&Dummy);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isRegMask());
+  ASSERT_TRUE(MO.getRegMask() == &Dummy);
+
+  // Print a MachineOperand containing a RegMask. Here we check that without a
+  // TRI and IntrinsicInfo we still print a less detailed regmask.
+  std::string str;
+  raw_string_ostream OS(str);
+  MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+  ASSERT_TRUE(OS.str() == "<regmask ...>");
+}
+
 } // end namespace