[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors

[sdesmalen]

Summary

Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

[rengolin]

Adding a few AArch64 folks, to make sure we get enough eyes on this, thus avoiding silly problems in the future, if we miss anything.

[fhahn]

This looks good to me, what do you think @rengolin ?

[rengolin]

This one is trivial, I agree.

llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp

bool TypeInfer::EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec,
   ValidateOnExit _1(Vec), _2(Sub);
   if (TP.hasError())
     return false;
 
   /// Return true if B is a suB-vector of P, i.e. P is a suPer-vector of B.
   auto IsSubVec = [](MVT B, MVT P) -> bool {
     if (!B.isVector() || !P.isVector())
       return false;
+    // Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
+    // but until there are obvious use-cases for this, keep the
+    // types separate.
+    if (B.isScalableVector() != P.isScalableVector())
+      return false;
     if (B.getVectorElementType() != P.getVectorElementType())
       return false;
     return B.getVectorNumElements() < P.getVectorNumElements();
   };
 
   /// Return true if S has no element (vector type) that T is a sub-vector of,
   /// i.e. has the same element type as T and more elements.
   auto NoSubV = [&IsSubVec](const TypeSetByHwMode::SetType &S, MVT T) -> bool {