[AArch64] Implement R_AARCH64_ LD_PREL_LO19

[davide]

Summary

Fixes PR34660. See the test for details on the reloc.

[ruiu]

Where's the documentation about this reloc?

[davide]

http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf

[davide]

Sorry, I mean http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056b/IHI0056B_aaelf64.pdf

[davide]

273 R_AARCH64_LD_PREL_LO19
S + A - P Set a load-literal immediate value to bits [20:2] of X; check that -2^20 ≤ X < 2^20

See, for reference, also, already implemented CONDBR19 (which does the same, but for branch instructions (this is for loads).

[ruiu]

I believe Peter Smith is the right person to review this, as he knows this part of code the most.

Just to make sure, is does the test pass when you use ld.bfd or ld.gold instead of ld.lld?

[davide]

In D38053#875579, @ruiu wrote:

I believe Peter Smith is the right person to review this, as he knows this part of code the most.

Just to make sure, is does the test pass when you use ld.bfd or ld.gold instead of ld.lld?

yes, that's how I checked the output (with bfd).

[davide]

Adding Peter Smith to the reviewers list.

[davide]

Rafael's comments.

[peter.smith]

Only thing I can spot is that I think that we are missing an alignment check on the result, otherwise looks good to me as well. The address of the value to be loaded must be at least 4-byte aligned. BFD has implemented this check, for example if I change the test case a little:

ldr x8, patatino

        .data
        .zero 5
patatino:

BFD will give me t.o:(.text+0x0): relocation truncated to fit: R_AARCH64_LD_PREL_LO19 against `.data', which is BFD's rather obtuse way of reporting alignment faults. The target of the conditional branch (R_AARCH64_CONDBR19) must be an instruction, which must be 4 byte aligned for AArch64, so I think it is safe to add a check for that as well. It is harder to write a realistic test case for that one though.

You can find the details of the instruction ldr (literal) in the architecture reference manual https://developer.arm.com/products/architecture/a-profile/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

ELF/Arch/AArch64.cpp

RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
   case R_AARCH64_CONDBR19:
   case R_AARCH64_JUMP26:
   case R_AARCH64_TSTBR14:
     return R_PLT_PC;
   case R_AARCH64_PREL16:
   case R_AARCH64_PREL32:
   case R_AARCH64_PREL64:
   case R_AARCH64_ADR_PREL_LO21:
+  case R_AARCH64_LD_PREL_LO19:
     return R_PC;
   case R_AARCH64_ADR_PREL_PG_HI21:
     return R_PAGE_PC;
   case R_AARCH64_LD64_GOT_LO12_NC:
   case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
     return R_GOT;
   case R_AARCH64_ADR_GOT_PAGE:
   case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
   case R_AARCH64_TLSDESC_ADR_PAGE21:
     checkInt<33>(Loc, Val, Type);
     write32AArch64Addr(Loc, Val >> 12);
     break;
   case R_AARCH64_ADR_PREL_LO21:
     checkInt<21>(Loc, Val, Type);
     write32AArch64Addr(Loc, Val);
     break;
+  case R_AARCH64_LD_PREL_LO19:
+    checkInt<21>(Loc, Val, Type);
+    or32le(Loc, (Val & 0x1FFFFC) << 3);
+    break;
   case R_AARCH64_JUMP26:
     // Normally we would just write the bits of the immediate field, however
     // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
     // we want to replace a non-branch instruction with a branch immediate
     // instruction. By writing all the bits of the instruction including the
     // opcode and the immediate (0 001 | 01 imm26) we can do this
     // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
     // the instruction we want to patch.

ELF/InputSection.cpp

static uint64_t getAArch64UndefinedRelativeWeakVA(uint64_t Type, uint64_t A,
   case R_AARCH64_JUMP26:
   case R_AARCH64_TSTBR14:
     return P + 4 + A;
   // Unresolved non branch pc-relative relocations
   case R_AARCH64_PREL16:
   case R_AARCH64_PREL32:
   case R_AARCH64_PREL64:
   case R_AARCH64_ADR_PREL_LO21:
+  case R_AARCH64_LD_PREL_LO19:
     return P + A;
   }
   llvm_unreachable("AArch64 pc-relative relocation expected\n");
 }
 
 // ARM SBREL relocations are of the form S + A - B where B is the static base
 // The ARM ABI defines base to be "addressing origin of the output segment
 // defining the symbol S". We defined the "addressing origin"/static base to be

test/ELF/pr34660.s

+# REQUIRES: aarch64
+
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-none %s -o %t.o
+# RUN: llvm-readobj -elf-output-style=GNU %t.o -r | FileCheck %s --check-prefix=RELS
+# RUN: ld.lld -shared %t.o -o %t
+# RUN: llvm-objdump %t -d | FileCheck %s --check-prefix=DISASM
+# RUN: llvm-readobj -elf-output-style=GNU %t -t | FileCheck %s --check-prefix=SYM
+
+# It would be much easier to understand/read this test if llvm-objdump would print
+# the immediates in hex.
+# IMM = hex(65540) = 0x10004
+# PC = 0x10000
+# As the relocation is PC-relative, IMM + PC = 0x20004 which is the VA of the
+# correct symbol.
+
+# RELS: Relocation section '.rela.text' at offset 0xa8 contains 1 entries:
+# RELS: 0000000000000000  0000000300000111 R_AARCH64_LD_PREL_LO19 0000000000000000 .data + 4
+
+# DISASM: Disassembly of section .text:
+# DISASM-NEXT: $x.0:
+# DISASM-NEXT:   10000:       28 00 08 58     ldr     x8, #65540
+
+# SYM: Symbol table '.symtab'
+# SYM:  0000000000020004     0 NOTYPE  LOCAL  DEFAULT    5 patatino
+
+  ldr x8, patatino
+  .data
+  .zero 4
+patatino: