[AArch64] Assembler support for the ARMv8.2a dot product instructions

[SjoerdMeijer]

Summary

Dot product is an optional ARMv8.2a extension, see also the public architecture specification here: https://developer.arm.com/products/architecture/a-profile/exploration-tools.
This patch adds AArch64 assembler support for these dot product instructions.

[t.p.northover]

Looks reasonable to me.

[SjoerdMeijer]

Thanks for the review!

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

AARCH64_ARCH("armv8-a", ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
              (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
 AARCH64_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a",
              ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_LSE))
 AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
              ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-              AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
+              AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+              AArch64::AEK_DOTPROD))
 #undef AARCH64_ARCH
 
 #ifndef AARCH64_ARCH_EXT_NAME
 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
 #endif
 // FIXME: This would be nicer were it tablegen
 AARCH64_ARCH_EXT_NAME("invalid",  AArch64::AEK_INVALID,  nullptr,  nullptr)
 AARCH64_ARCH_EXT_NAME("none",     AArch64::AEK_NONE,     nullptr,  nullptr)
 AARCH64_ARCH_EXT_NAME("crc",      AArch64::AEK_CRC,      "+crc",   "-crc")
 AARCH64_ARCH_EXT_NAME("lse",      AArch64::AEK_LSE,      "+lse",   "-lse")
 AARCH64_ARCH_EXT_NAME("crypto",   AArch64::AEK_CRYPTO,   "+crypto","-crypto")
+AARCH64_ARCH_EXT_NAME("dotprod",  AArch64::AEK_DOTPROD,  "+dotprod","-dotprod")
 AARCH64_ARCH_EXT_NAME("fp",       AArch64::AEK_FP,       "+fp-armv8",  "-fp-armv8")
 AARCH64_ARCH_EXT_NAME("simd",     AArch64::AEK_SIMD,     "+neon",  "-neon")
 AARCH64_ARCH_EXT_NAME("fp16",     AArch64::AEK_FP16,     "+fullfp16",  "-fullfp16")
 AARCH64_ARCH_EXT_NAME("profile",  AArch64::AEK_PROFILE,  "+spe",  "-spe")
 AARCH64_ARCH_EXT_NAME("ras",      AArch64::AEK_RAS,      "+ras",  "-ras")
 AARCH64_ARCH_EXT_NAME("sve",      AArch64::AEK_SVE,      "+sve",  "-sve")
 #undef AARCH64_ARCH_EXT_NAME
 

llvm/trunk/include/llvm/Support/TargetParser.h

enum ArchExtKind : unsigned {
   AEK_CRC = 0x2,
   AEK_CRYPTO = 0x4,
   AEK_FP = 0x8,
   AEK_SIMD = 0x10,
   AEK_FP16 = 0x20,
   AEK_PROFILE = 0x40,
   AEK_RAS = 0x80,
   AEK_LSE = 0x100,
-  AEK_SVE = 0x200
+  AEK_SVE = 0x200,
+  AEK_DOTPROD = 0x400
 };
 
 StringRef getCanonicalArchName(StringRef Arch);
 
 // Information by ID
 StringRef getFPUName(unsigned FPUKind);
 ARM::FPUVersion getFPUVersion(unsigned FPUKind);
 ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);

llvm/trunk/lib/Target/AArch64/AArch64.td

 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
     "Disable latency scheduling heuristic">;
 
 def FeatureUseRSqrt : SubtargetFeature<
     "use-reciprocal-square-root", "UseRSqrt", "true",
     "Use the reciprocal square root approximation">;
 
+def FeatureDotProd : SubtargetFeature<
+    "dotprod", "HasDotProd", "true",
+    "Enable dot product support">;
+
 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
                                         "NegativeImmediates", "false",
                                         "Convert immediates and instructions "
                                         "to their negated or complemented "
                                         "equivalent when the immediate does "
                                         "not fit in the encoding.">;
 
 def FeatureLSLFast : SubtargetFeature<

llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<3> size, bits<5> opcode,
   let Inst{23-21} = size;
   let Inst{20-16} = Rm;
   let Inst{15-11} = opcode;
   let Inst{10}    = 1;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,
+                                 string kind2> :
+        BaseSIMDThreeSameVector<Q, U, 0b100, 0b10010, V128, asm, kind1, [] > {
+  let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
+}
+
 // All operand sizes distinguished in the encoding.
 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
                                SDPatternOperator OpNode> {
   def v8i8  : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
                                       asm, ".8b",
          [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
   def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
                                       asm, ".16b",
class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
   let Inst{20-16} = Rm;
   let Inst{15-12} = opc;
   // Bit 11 must be set by the derived class.
   let Inst{10}    = 0;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+// ARMv8.2 Index Dot product instructions
+class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string dst_kind,
+                                      string lhs_kind, string rhs_kind> :
+        BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, V128, V128, V128, VectorIndexS,
+                            asm, "", dst_kind, lhs_kind, rhs_kind, []> {
+  bits<2> idx;
+  let Inst{21}    = idx{0};  // L
+  let Inst{11}    = idx{1};  // H
+}
+
 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
                          SDPatternOperator OpNode> {
   let Predicates = [HasNEON, HasFullFP16] in {
   def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc,
                                       V64, V64,
                                       V128_lo, VectorIndexH,
                                       asm, ".4h", ".4h", ".4h", ".h",
     [(set (v4f16 V64:$Rd),
multiclass STOPregister<string asm, string instr> {
   def : BaseSTOPregister<asm,        GPR32, WZR,
                     !cast<Instruction>(instr # "W")>;
   def : BaseSTOPregister<asm,        GPR64, XZR,
                     !cast<Instruction>(instr # "X")>;
 }
 
 //----------------------------------------------------------------------------
 // Allow the size specifier tokens to be upper case, not just lower.
+def : TokenAlias<".4B", ".4b">;  // Add dot product
 def : TokenAlias<".8B", ".8b">;
 def : TokenAlias<".4H", ".4h">;
 def : TokenAlias<".2S", ".2s">;
 def : TokenAlias<".1D", ".1d">;
 def : TokenAlias<".16B", ".16b">;
 def : TokenAlias<".8H", ".8h">;
 def : TokenAlias<".4S", ".4s">;
 def : TokenAlias<".2D", ".2d">;
 def : TokenAlias<".1Q", ".1q">;
 def : TokenAlias<".2H", ".2h">;
 def : TokenAlias<".B", ".b">;
 def : TokenAlias<".H", ".h">;
 def : TokenAlias<".S", ".s">;
 def : TokenAlias<".D", ".d">;
 def : TokenAlias<".Q", ".q">;

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 def HasV8_2a         : Predicate<"Subtarget->hasV8_2aOps()">,
                                  AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "neon">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
+def HasDotProd       : Predicate<"Subtarget->hasDotProd()">,
+                                 AssemblerPredicate<"FeatureDotProd", "dotprod">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
 def HasLSE           : Predicate<"Subtarget->hasLSE()">,
                                  AssemblerPredicate<"FeatureLSE", "lse">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
                                  AssemblerPredicate<"FeatureRAS", "ras">;
 def HasRDM           : Predicate<"Subtarget->hasRDM()">,
                                  AssemblerPredicate<"FeatureRDM", "rdm">;

 
 def DSB   : CRmSystemI<barrier_op, 0b100, "dsb",
                        [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
 
 def ISB   : CRmSystemI<barrier_op, 0b110, "isb",
                        [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
 }
 
+// ARMv8.2 Dot Product
+let Predicates = [HasDotProd] in {
+def UDOT2S    : BaseSIMDThreeSameVectorDot<0, 1, "udot", ".2s", ".8b">;
+def SDOT2S    : BaseSIMDThreeSameVectorDot<0, 0, "sdot", ".2s", ".8b">;
+def UDOT4S    : BaseSIMDThreeSameVectorDot<1, 1, "udot", ".4s", ".16b">;
+def SDOT4S    : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;
+def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s", ".8b", ".4b">;
+def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s", ".8b", ".4b">;
+def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4b">;
+def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;
+}
+
 def : InstAlias<"clrex", (CLREX 0xf)>;
 def : InstAlias<"isb", (ISB 0xf)>;
 
 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   ARMProcFamilyEnum ARMProcFamily = Others;
 
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;
 
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
+  bool HasDotProd = false;
   bool HasCRC = false;
   bool HasLSE = false;
   bool HasRAS = false;
   bool HasRDM = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasSPE = false;
   bool HasLSLFast = false;
public:
   unsigned getMinVectorRegisterBitWidth() const {
     return MinVectorRegisterBitWidth;
   }
 
   bool isX18Reserved() const { return ReserveX18; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON; }
   bool hasCrypto() const { return HasCrypto; }
+  bool hasDotProd() const { return HasDotProd; }
   bool hasCRC() const { return HasCRC; }
   bool hasLSE() const { return HasLSE; }
   bool hasRAS() const { return HasRAS; }
   bool hasRDM() const { return HasRDM; }
   bool balanceFPOps() const { return BalanceFPOps; }
   bool predictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

return StringSwitch<bool>(Name.lower())
       // aren't used in the right places, the token operand won't match so
       // all will work out.
       .Case(".b", true)
       .Case(".h", true)
       .Case(".s", true)
       .Case(".d", true)
       // Needed for fp16 scalar pairwise reductions
       .Case(".2h", true)
+      // another special case for the ARMv8.2a dot product operand
+      .Case(".4b", true)
       .Default(false);
 }
 
 static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
                                  char &ElementKind) {
   assert(isValidVectorKind(Name));
 
   ElementKind = Name.lower()[Name.size() - 1];

llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s

+// RUN: not llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+udot v0.2s, v1.8b, v2.4b[4]
+sdot v0.2s, v1.8b, v2.4b[4]
+udot v0.4s, v1.16b, v2.4b[4]
+sdot v0.4s, v1.16b, v2.4b[4]
+
+// CHECK-ERROR: vector lane must be an integer in range [0, 3]
+// CHECK-ERROR: vector lane must be an integer in range [0, 3]
+// CHECK-ERROR: vector lane must be an integer in range [0, 3]
+// CHECK-ERROR: vector lane must be an integer in range [0, 3]

llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s

+// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s | FileCheck %s  --check-prefix=CHECK-DOTPROD
+// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+
+udot v0.2s, v1.8b, v2.8b
+sdot v0.2s, v1.8b, v2.8b
+udot v0.4s, v1.16b, v2.16b
+sdot v0.4s, v1.16b, v2.16b
+udot v0.2s, v1.8b, v2.4b[0]
+sdot v0.2s, v1.8b, v2.4b[1]
+udot v0.4s, v1.16b, v2.4b[2]
+sdot v0.4s, v1.16b, v2.4b[3]
+
+// Check that the upper case types are aliases
+udot v0.2S, v1.8B, v2.4B[0]
+udot v0.4S, v1.16B, v2.4B[2]
+
+// CHECK-DOTPROD:  udot  v0.2s, v1.8b, v2.8b     // encoding: [0x20,0x94,0x82,0x2e]
+// CHECK-DOTPROD:  sdot  v0.2s, v1.8b, v2.8b     // encoding: [0x20,0x94,0x82,0x0e]
+// CHECK-DOTPROD:  udot  v0.4s, v1.16b, v2.16b   // encoding: [0x20,0x94,0x82,0x6e]
+// CHECK-DOTPROD:  sdot  v0.4s, v1.16b, v2.16b   // encoding: [0x20,0x94,0x82,0x4e]
+// CHECK-DOTPROD:  udot  v0.2s, v1.8b, v2.4b[0]  // encoding: [0x20,0xe0,0x82,0x2f]
+// CHECK-DOTPROD:  sdot  v0.2s, v1.8b, v2.4b[1]  // encoding: [0x20,0xe0,0xa2,0x0f]
+// CHECK-DOTPROD:  udot  v0.4s, v1.16b, v2.4b[2] // encoding: [0x20,0xe8,0x82,0x6f]
+// CHECK-DOTPROD:  sdot  v0.4s, v1.16b, v2.4b[3] // encoding: [0x20,0xe8,0xa2,0x4f]
+
+// CHECK-DOTPROD:  udot  v0.2s, v1.8b, v2.4b[0]  // encoding: [0x20,0xe0,0x82,0x2f]
+// CHECK-DOTPROD:  udot  v0.4s, v1.16b, v2.4b[2] // encoding: [0x20,0xe8,0x82,0x6f]
+
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.8b
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.8b
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.16b
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.16b
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.4b[0]
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.4b[1]
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.4b[2]
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.4b[3]
+// CHECK-NO-DOTPROD: ^
+
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.2S, v1.8B, v2.4B[0]
+// CHECK-NO-DOTPROD: ^
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: udot v0.4S, v1.16B, v2.4B[2]
+// CHECK-NO-DOTPROD: ^

llvm/trunk/test/MC/AArch64/neon-diagnostics.s

 
 //----------------------------------------------------------------------
 // Permutation with 3 vectors
 //----------------------------------------------------------------------
 
         uzp1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
         uzp2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
         zip1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
-\
+
         zip2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
         trn1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
         trn2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn2 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 //----------------------------------------------------------------------
 // Permutation with 3 vectors
 //----------------------------------------------------------------------
 
         uzp1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
         uzp2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         uzp2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         uzp2 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         uzp2 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
         zip1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
 
 
         zip2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         zip2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         zip2 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         zip2 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
 
         trn1 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn1 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
 // CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
         trn1 v0.2d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn1 v0.1d, v1.1d, v2.1d
 // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
 
 
 
         trn2 v0.16b, v1.8b, v2.8b
 // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
         trn2 v0.8b, v1.4b, v2.4b
-// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
-// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
+// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.8h, v1.4h, v2.4h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4h, v1.2h, v2.2h
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.4s, v1.2s, v2.2s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
         trn2 v0.2s, v1.1s, v2.1s
 // CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+0x20,0x94,0x82,0x2e
+0x20,0x94,0x82,0x0e
+0x20,0x94,0x82,0x6e
+0x20,0x94,0x82,0x4e
+0x20,0xe0,0x82,0x2f
+0x20,0xe0,0xa2,0x0f
+0x20,0xe8,0x82,0x6f
+0x20,0xe8,0xa2,0x4f
+
+#CHECK:  udot  v0.2s, v1.8b, v2.8b
+#CHECK:  sdot  v0.2s, v1.8b, v2.8b
+#CHECK:  udot  v0.4s, v1.16b, v2.16b
+#CHECK:  sdot  v0.4s, v1.16b, v2.16b
+#CHECK:  udot  v0.2s, v1.8b, v2.4b[0]
+#CHECK:  sdot  v0.2s, v1.8b, v2.4b[1]
+#CHECK:  udot  v0.4s, v1.16b, v2.4b[2]
+#CHECK:  sdot  v0.4s, v1.16b, v2.4b[3]
+
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding
+# CHECK-ERROR:  invalid instruction encoding