[AArch64] Explicitly enable FeatureFuseLiterals on Cortex-A72 (NFC).

[fhahn]

Summary

This feature explicitly enables the fusion of instructions for literal
generation and PC-relative address calculations on Cortex-A72, as
recommended in its Software Optimisation Guide, sections 4.11 and
4.12. This is a NFC, as the Cortex-A72 currently uses the Cortex-A57
processor model which already schedules those instructions back-to-back
when the PostRAScheduler is not used.

[javed.absar]

lib/Target/AArch64/AArch64.td

221

Should this be listed right after FeatureFPARMv8 and not after FeatureNEON to respect consistent ordering? e.g. see ProcA57 above.

[sbaranga]

Hi Florian,

Is the plan to add the missing features (which would include also include FeatureFuseAES I guess) and then turn PostRA scheduling on?

I think we should benchmark this with PostRA scheduling on, to check its impact.

Cheers,
Silviu

[fhahn]

Hi Silviu,
yes the plan is to include FeatureFuseAES for A72 as well, I'm going to commit a patch soon that adds FeatureFuseAES for Cortex-A72 and I'll also put up a patch for review that makes instruction fusion slightly more aggressive on AArch64.

I didn't plan to do anything with respect to PostRA, but I could benchmark the difference with and without PostRA.

Cheers

[javed.absar]

In D33196#755104, @fhahn wrote:

I didn't plan to do anything with respect to PostRA, but I could benchmark the difference with and without PostRA.

Hi Florian:
I looks to me like you don't have to to anything special for PostRA (see AArch64TargetMachine.cpp::282-292 - if(hasFuseLiterals()) ), other than benchmark it like Silviu mentions.
Best Regards, Javed.

[fhahn]

My investigations did not show any measurable benefit. I will drop this for now

lib/Target/AArch64/AArch64.td

def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
                                    FeaturePredictableSelectIsExpensive
                                    ]>;
 
 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
                                    "Cortex-A72 ARM processors", [
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
+                                   FeatureFuseLiterals,
                                    FeatureNEON,
                                    FeaturePerfMon
                                    ]>;
 
 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
                                    "Cortex-A73 ARM processors", [
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureNEON,

test/CodeGen/AArch64/misched-fusion-lit.ll

 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=-fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKDONT
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57      | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72      | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
 
 @g = common local_unnamed_addr global i8* null, align 8
 
 define i8* @litp(i32 %a, i32 %b) {
 entry:
   %add = add nsw i32 %b, %a
   %idx.ext = sext i32 %add to i64
   %add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @litp to i8*), i64 %idx.ext