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[AArch64] Explicitly enable FeatureFuseLiterals on Cortex-A72 (NFC).
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Authored by fhahn on May 15 2017, 6:53 AM.

Details

Summary

This feature explicitly enables the fusion of instructions for literal
generation and PC-relative address calculations on Cortex-A72, as
recommended in its Software Optimisation Guide, sections 4.11 and
4.12. This is a NFC, as the Cortex-A72 currently uses the Cortex-A57
processor model which already schedules those instructions back-to-back
when the PostRAScheduler is not used.

Diff Detail

Event Timeline

fhahn created this revision.May 15 2017, 6:53 AM
javed.absar added inline comments.May 15 2017, 7:03 AM
lib/Target/AArch64/AArch64.td
221

Should this be listed right after FeatureFPARMv8 and not after FeatureNEON to respect consistent ordering? e.g. see ProcA57 above.

fhahn updated this revision to Diff 99002.May 15 2017, 7:24 AM
fhahn marked an inline comment as done.

Hi Florian,

Is the plan to add the missing features (which would include also include FeatureFuseAES I guess) and then turn PostRA scheduling on?

I think we should benchmark this with PostRA scheduling on, to check its impact.

Cheers,
Silviu

fhahn added a comment.May 15 2017, 8:23 AM

Hi Silviu,
yes the plan is to include FeatureFuseAES for A72 as well, I'm going to commit a patch soon that adds FeatureFuseAES for Cortex-A72 and I'll also put up a patch for review that makes instruction fusion slightly more aggressive on AArch64.

I didn't plan to do anything with respect to PostRA, but I could benchmark the difference with and without PostRA.

Cheers

I didn't plan to do anything with respect to PostRA, but I could benchmark the difference with and without PostRA.

Hi Florian:
I looks to me like you don't have to to anything special for PostRA (see AArch64TargetMachine.cpp::282-292 - if(hasFuseLiterals()) ), other than benchmark it like Silviu mentions.
Best Regards, Javed.

fhahn abandoned this revision.Jan 2 2018, 7:18 AM

My investigations did not show any measurable benefit. I will drop this for now