v2f32 ops

[jonpa]

Summary

A few days ago I described this issue on llvm-commits along with patch:

Hi,

I found that on SystemZ, for v2f32, four and not two scalar operations are emitted. This is because the v2f32 type is widened, which is good in cases of memory-only operations for instance. There is however no fp32 vector support on z13, so these will always be scalarized. If this is done after type-legalization, four and not two operations are produced, which is particularly bad in case of fp32 divide inside a vectorized loop.

In order to fix this, my patch unrolls these operations before type legalization (with a target DAG combine). They must also have the operation action of 'Expand', since otherwise other DAGCombiner methods may re-vectorized them again. This happened in reduceBuildVecConvertToConvertBuildVec(), where I also needed to add a call to TLI.isOperationLegalOrCustom(Opcode, VT), to check on the *result* type, which would in this case be v2f32. It would not work to
mark all the operand VT's of SINT_TO_FP as 'Expand', because this is only true for the v2f32 result case.

I do get some failing regression tests, which I am not sure about:

Failing Tests (3):

LLVM :: CodeGen/ARM/vdup.ll
LLVM :: CodeGen/X86/2009-02-26-MachineLICMBug.ll
LLVM :: CodeGen/X86/cvtv2f32.ll

Is it ok to add the check for the result type per what I did?

/Jonas

In short, this is something I did for the SystemZ target, but because I had to add an extra check in reduceBuildVecConvertToConvertBuildVec(), three tests failed.

I have now tried to regenerate the tests, but only one of them was successfully regenerated. I include that test diff, plus the two output diffs of the two remaining test cases.

I hope that either the tests have been improved as expected (which I can't tell for myself for sure), or that someone gives me a pointer on how to change the patch.

Thanks

/Jonas

[efriedma]

On platforms where the widened operation is legal or custom-lowered, we want to use that operation. (For example, if v4f32 uitofp is custom, we also want to use that lowering for v2f32.)

It looks like x86 in particular is legalizing v2f32 uint_to_fp nodes earlier than it should, so the DAGCombine can't trigger after type legalization.

It looks like on ARM, we can't perform the transform after type legalization because we end up with a 32-bit sitofp (because ARM doesn't have 16-bit registers). The "SrcVT != InVT" check could be extended to handle this case.

That said, if you don't want to mess with other targets, maybe you could change the new check in DAGCombine to "if (LegalTypes && !TLI.isOperationLegalOrCustom(Opcode, VT))"?

test/CodeGen/X86/cvtv2f32.ll

21

This looks worse.

31

This... is arguably better, I guess, but you're not really reaching it in any principled manner.

test_CodeGen_ARM_vdup.diff

83

The old code was loading directly to a vector register (vld1 is a splat load, vmovl is a sign-extend, and vcvt is the int->float conversion). The new code is loading to an integer register (ldrsh), moving to an fp register (vmov), converting to fp (vcvt), then splatting the result (vdup). The new code is slightly worse. (Ultimately, we want to do the splat before the int->fp conversion here because we can fold the splat into the load.)

test_CodeGen_X86_MLICMbug.diff

58

This looks worse.

[jonpa]

Thanks for help with the test regressions!

That said, if you don't want to mess with other targets, maybe you could change the new check in DAGCombine to "if (LegalTypes && !TLI.isOperationLegalOrCustom(Opcode, VT))"?

I don't think that would work, becuase this problem arose as an infinite loop *before* type legalization (the point was to call DAG.UnrollVectorOp() before type legalization with only two elements).

On platforms where the widened operation is legal or custom-lowered, we want to use that operation. (For example, if v4f32 uitofp is custom, we also want to use that lowering for v2f32.)

I tried this idea, by adding a check for also the widened VT, but that didn't work. In vdup.ll,
this optimization is needed to make a 'v4f32 = sint_to_fp' node. This is however marked for 'Expand', so TLI.isOperationLegalOrCustom() doesn't work.

Instead, I made my check more precise, to handle only exactly the case where before type legalization, if the result is going to be widened, and both the narrow and wider ops are 'Expand', then don't vectorize it (return SDValue()). This seems to work better, with no regressions.

This seems even possibly even like a general DAG heuristic, to actually scalarize early in this case. Or is it not?

I also realized that I don't have to call setOperationAction(Op, MVT::v2f32, Expand) at all, since this is true already per default for all vector ops in SystemZ.

[RKSimon]

What is stopping you from implementing SystemZTargetLowering::ReplaceNodeResults to handle these?

Please can you keep the x86/arm regressions in your patch.

[jonpa]

What is stopping you from implementing SystemZTargetLowering::ReplaceNodeResults to handle these?

The problem I see is with the FP_TO_XINT nodes. The fp->v2i64 are legal, which is correct in the case of v2f64->v2i64. This also means in practice that v2f32 -> v2i64 is legal which it is not, but this is basically ok since there is no vector support for f32. Unfortunately, there is no way to specify that just v2f32->v2iXX should be custom, based on the operand type.

This is a problem there does not seem to be a solution to at the moment - it depends on checking the operand type in this case, while CustomWidenLowerNode() just checks for the result VT.

It might be possible to mark all FP_TO_XINT nodes of all integer vector types as custom, but that would also affect other things, such as cost functions and what not, so I am not sure that would be worth bothering with.

I could apply the patch as it is or move that transformation to ReplaceNodeResults() and maybe just ignore the FP_TO_XINT nodes for now, since fp32 is not a high priority.

Please can you keep the x86/arm regressions in your patch.

The test regressions are gone because I avoided it with the tighter check - sorry I didn't mention that more clearly.

As I said before, if anything I would like to try to make this a general rule that if a node is going to get widened and then expanded, then it should be expanded if possilbe before type legalization (widening). Otherwise unnecessary scalar operations will be built for the undef elements of the widened vector.

[jonpa]

The main reason that ReplaceNodeResults() cannot be used in this case, is really because it is run after type-legalization and the widening performed there on these operations. Then the VT has changed to v4f32 and it is not possible anymore to expand to just two ops.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
          && "Should only handle conversion from integer to float.");
   assert(SrcVT != MVT::Other && "Cannot determine source type!");
 
   EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
 
   if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
     return SDValue();
 
+  // Check operation result VT (there may be less support for a particular fp
+  // width).
+  if (!TLI.isOperationLegalOrCustom(Opcode, VT))
+    return SDValue();
+
   // Just because the floating-point vector type is legal does not necessarily
   // mean that the corresponding integer vector type is.
   if (!isTypeLegal(NVT))
     return SDValue();
 
   SmallVector<SDValue, 8> Opnds;
   for (unsigned i = 0; i != NumInScalars; ++i) {
     SDValue In = N->getOperand(i);

lib/Target/SystemZ/SystemZISelLowering.cpp

SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
   setTargetDAGCombine(ISD::FP_ROUND);
   setTargetDAGCombine(ISD::BSWAP);
   setTargetDAGCombine(ISD::SHL);
   setTargetDAGCombine(ISD::SRA);
   setTargetDAGCombine(ISD::SRL);
   setTargetDAGCombine(ISD::ROTL);
 
+  // Scalarize v2f32 early, to avoid later expansion to 4 operations (see
+  // comment in PerformDAGCombine).
+  SmallVector<ISD::NodeType, 12> FP32Ops =
+    {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV, ISD::FREM, ISD::SINT_TO_FP,
+     ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT};
+  for (auto Op : FP32Ops) {
+    setTargetDAGCombine(Op);
+    setOperationAction(Op, MVT::v2f32, Expand);
+  }
+
   // Handle intrinsics.
   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   // We want to use MVC in preference to even a single load/store pair.
   MaxStoresPerMemcpy = 0;
   MaxStoresPerMemcpyOptSize = 0;
 
SDValue SystemZTargetLowering::combineSHIFTROT(
   }
 
   return SDValue();
 }
 
 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
                                                  DAGCombinerInfo &DCI) const {
   switch(N->getOpcode()) {
-  default: break;
+  default:
+    // Z13 can handle fp32 vectors in registers and memory, but does not
+    // support any vector operations on them. v2f32 is widened to v4f32 and
+    // kept in a single vector register, which is better when only memory
+    // operations are involved. Any operations on v2f32 should be scalarized
+    // before type legalization, or else all four operations will actually be
+    // emitted.
+    if (N->getValueType(0) == MVT::v2f32 ||
+        ((N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::FP_TO_UINT) &&
+         (N->getOperand(0)->getValueType(0) == MVT::v2f32 &&
+          N->getValueType(0) == MVT::v2i32)))
+      return DCI.DAG.UnrollVectorOp(N, 2);
+
+    break;
   case ISD::SIGN_EXTEND:        return combineSIGN_EXTEND(N, DCI);
   case SystemZISD::MERGE_HIGH:
   case SystemZISD::MERGE_LOW:   return combineMERGE(N, DCI);
   case ISD::STORE:              return combineSTORE(N, DCI);
   case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
   case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
   case ISD::FP_ROUND:           return combineFP_ROUND(N, DCI);
   case ISD::BSWAP:              return combineBSWAP(N, DCI);

test/CodeGen/SystemZ/fp32-vec-conv.ll

+; Test that a vector of two floats only generates two instructions (and not
+; four).
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+
+define <2 x float> @fun0(<2 x i32> %val1) {
+; CHECK-LABEL: fun0:
+; CHECK:  celfbr
+; CHECK:  celfbr
+; CHECK-NOT:  celfbr
+  %z = uitofp <2 x i32> %val1 to <2 x float>
+  ret <2 x float> %z
+}
+
+define <2 x float> @fun1(<2 x i32> %val1) {
+; CHECK-LABEL: fun1:
+; CHECK:  cefbr
+; CHECK:  cefbr
+; CHECK-NOT:  cefbr
+  %z = sitofp <2 x i32> %val1 to <2 x float>
+  ret <2 x float> %z
+}
+
+define <2 x i32> @fun2(<2 x float> %val1) {
+; CHECK-LABEL: fun2:
+; CHECK:  cfebr
+; CHECK:  cfebr
+; CHECK-NOT:  cfebr
+  %z = fptosi <2 x float> %val1 to <2 x i32>
+  ret <2 x i32> %z
+}
+
+define <2 x i32> @fun3(<2 x float> %val1) {
+; CHECK-LABEL: fun3:
+; CHECK:  clfebr
+; CHECK:  clfebr
+; CHECK-NOT:  clfebr
+  %z = fptoui <2 x float> %val1 to <2 x i32>
+  ret <2 x i32> %z
+}

test/CodeGen/SystemZ/fp32-vec-ops.ll

+; Test that a vector of two floats only generates two instructions (and not
+; four).
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+define <2 x float> @fun0(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: fun0:
+; CHECK:  aebr
+; CHECK:  aebr
+; CHECK-NOT:  aebr
+  %ret = fadd <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}
+
+define <2 x float> @fun1(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: fun1:
+; CHECK:  sebr
+; CHECK:  sebr
+; CHECK-NOT:  sebr
+  %ret = fsub <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}
+
+define <2 x float> @fun2(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: fun2:
+; CHECK:  meebr
+; CHECK:  meebr
+; CHECK-NOT:  meebr
+  %ret = fmul <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}
+
+define <2 x float> @fun3(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: fun3:
+; CHECK:  debr
+; CHECK:  debr
+; CHECK-NOT:  debr
+  %ret = fdiv <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}
+
+define <2 x float> @fun4(<2 x float> %val1, <2 x float> %val2) {
+; CHECK-LABEL: fun4:
+; CHECK:  brasl %r14, fmodf@PLT
+; CHECK:  brasl %r14, fmodf@PLT
+; CHECK-NOT:  brasl %r14, fmodf@PLT
+  %ret = frem <2 x float> %val1, %val2
+  ret <2 x float> %ret
+}

test/CodeGen/X86/cvtv2f32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X32
 ; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X64
 
 ; uitofp <2 x i32> codegen from buildvector or legalization is different but gives the same results
 ; across the full 0 - 0xFFFFFFFF u32 range.
 
 define <2 x float> @uitofp_2i32_buildvector(i32 %x, i32 %y, <2 x float> %v) {
 ; X32-LABEL: uitofp_2i32_buildvector:
 ; X32:       # BB#0:
-; X32-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
-; X32-NEXT:    movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200]
-; X32-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
-; X32-NEXT:    psrld $16, %xmm1
-; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]
-; X32-NEXT:    addps {{\.LCPI.*}}, %xmm1
-; X32-NEXT:    addps %xmm2, %xmm1
+; X32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; X32-NEXT:    orpd %xmm2, %xmm1
+; X32-NEXT:    subsd %xmm2, %xmm1
+; X32-NEXT:    cvtsd2ss %xmm1, %xmm1
+; X32-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; X32-NEXT:    orpd %xmm2, %xmm3
+; X32-NEXT:    subsd %xmm2, %xmm3
+; X32-NEXT:    xorps %xmm2, %xmm2
+; X32-NEXT:    cvtsd2ss %xmm3, %xmm2
+; X32-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
 ; X32-NEXT:    mulps %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: uitofp_2i32_buildvector:
 ; X64:       # BB#0:
-; X64-NEXT:    movd %edi, %xmm1
-; X64-NEXT:    pinsrd $1, %esi, %xmm1
-; X64-NEXT:    movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200]
-; X64-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
-; X64-NEXT:    psrld $16, %xmm1
-; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]
-; X64-NEXT:    addps {{.*}}(%rip), %xmm1
-; X64-NEXT:    addps %xmm2, %xmm1
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    cvtsi2ssq %rax, %xmm1
+; X64-NEXT:    movl %esi, %eax
+; X64-NEXT:    cvtsi2ssq %rax, %xmm2
+; X64-NEXT:    insertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
 ; X64-NEXT:    mulps %xmm1, %xmm0
 ; X64-NEXT:    retq
   %t1 = uitofp i32 %x to float
   %t2 = insertelement <2 x float> undef, float %t1, i32 0
   %t3 = uitofp i32 %y to float
   %t4 = insertelement <2 x float> %t2, float %t3, i32 1
   %t5 = fmul <2 x float> %v, %t4
   ret <2 x float> %t5

test_CodeGen_ARM_vdup.diff

+--- vdup.trunk.s  2017-02-23 14:41:45.000000000 +0200
++++ vdup.patch.s  2017-02-23 14:41:27.000000000 +0200
+@@ -588,76 +588,77 @@
+  vmov  r0, r1, d16
+  mov pc, lr
+ .Lfunc_end35:
+  .size check_i8, .Lfunc_end35-check_i8
+  .cantunwind
+  .fnend
+ 
+  .globl  check_spr_splat2
+  .p2align  2
+  .type check_spr_splat2,%function
+  .code 32                      @ @check_spr_splat2
+ check_spr_splat2:
+  .fnstart
+ @ BB#0:
+  lsl r2, r2, #16
+- vmov  d17, r0, r1
++ vmov  d16, r0, r1
+  asr r2, r2, #16
+- vdup.32 d16, r2
+- vcvt.f32.s32  d16, d16
+- vsub.f32  d16, d16, d17
++ vmov  s0, r2
++ vcvt.f32.s32  s0, s0
++ vdup.32 d17, d0[0]
++ vsub.f32  d16, d17, d16
+  vmov  r0, r1, d16
+  mov pc, lr
+ .Lfunc_end36:
+  .size check_spr_splat2, .Lfunc_end36-check_spr_splat2
+  .fnend
+ 
+  .globl  check_spr_splat4
+  .p2align  2
+  .type check_spr_splat4,%function
+  .code 32                      @ @check_spr_splat4
+ check_spr_splat4:
+  .fnstart
+ @ BB#0:
+- mov r12, sp
+- vmov  d19, r2, r3
+- vld1.16 {d16[]}, [r12:16]
+- vmov  d18, r0, r1
+- vmovl.s16 q8, d16
+- vcvt.f32.s32  q8, q8
+- vsub.f32  q8, q8, q9
++ ldrsh r12, [sp]
++ vmov  d17, r2, r3
++ vmov  d16, r0, r1
++ vmov  s0, r12
++ vcvt.f32.s32  s0, s0
++ vdup.32 q9, d0[0]
++ vsub.f32  q8, q9, q8
+  vmov  r0, r1, d16
+  vmov  r2, r3, d17
+  mov pc, lr
+ .Lfunc_end37:
+  .size check_spr_splat4, .Lfunc_end37-check_spr_splat4
+  .fnend
+ 
+  .globl  check_spr_splat4_lane1
+  .p2align  2
+  .type check_spr_splat4_lane1,%function
+  .code 32                      @ @check_spr_splat4_lane1
+ check_spr_splat4_lane1:
+  .fnstart
+ @ BB#0:
+- mov r12, sp
+- vmov  d19, r2, r3
+- vld1.16 {d16[]}, [r12:16]
+- vmov  d18, r0, r1
+- vmovl.s16 q8, d16
+- vcvt.f32.s32  q8, q8
+- vsub.f32  q8, q8, q9
++ ldrsh r12, [sp]
++ vmov  d17, r2, r3
++ vmov  d16, r0, r1
++ vmov  s0, r12
++ vcvt.f32.s32  s0, s0
++ vdup.32 q9, d0[0]
++ vsub.f32  q8, q9, q8
+  vmov  r0, r1, d16
+  vmov  r2, r3, d17
+  mov pc, lr
+ .Lfunc_end38:
+  .size check_spr_splat4_lane1, .Lfunc_end38-check_spr_splat4_lane1
+  .fnend
+ 
+  .globl  check_i8_varidx
+  .p2align  2
+  .type check_i8_varidx,%function
+  .code 32                      @ @check_i8_varidx
+ check_i8_varidx:
+  .fnstart
+ @ BB#0:
+  .save {r11}

test_CodeGen_X86_MLICMbug.diff

+--- 2009-02-26-MachineLICMBug.trunk.s 2017-02-23 14:56:54.000000000 +0200
++++ 2009-02-26-MachineLICMBug.patch.s 2017-02-23 14:56:45.000000000 +0200
+@@ -1,59 +1,43 @@
+  .section  __TEXT,__text,regular,pure_instructions
+  .macosx_version_min 10, 6
+- .section  __TEXT,__literal16,16byte_literals
+- .p2align  4
+-LCPI0_0:
+- .long 1258291200              ## 0x4b000000
+- .long 1258291200              ## 0x4b000000
+- .long 1258291200              ## 0x4b000000
+- .long 1258291200              ## 0x4b000000
+-LCPI0_1:
+- .long 1392508928              ## 0x53000000
+- .long 1392508928              ## 0x53000000
+- .long 1392508928              ## 0x53000000
+- .long 1392508928              ## 0x53000000
+-LCPI0_2:
+- .long 3539992704              ## float -5.49764202E+11
+- .long 3539992704              ## float -5.49764202E+11
+- .long 3539992704              ## float -5.49764202E+11
+- .long 3539992704              ## float -5.49764202E+11
+- .section  __TEXT,__text,regular,pure_instructions
+  .globl  _t
+  .p2align  4, 0x90
+ _t:                                     ## @t
+ ## BB#0:                                ## %entry
+  pushq %r14
+  pushq %rbx
+  pushq %rax
+  movq  %rsi, %r14
+  movq  %rdi, %rbx
+  orq $2097152, %r14          ## imm = 0x200000
+  andl  $15728640, %r14d        ## imm = 0xF00000
+  jmp LBB0_1
+  .p2align  4, 0x90
+ LBB0_3:                                 ## %bb.i
+                                         ##   in Loop: Header=BB0_1 Depth=1
+- movd  0, %xmm0                ## xmm0 = mem[0],zero,zero,zero
+- pinsrd  $1, 4, %xmm0
+- pinsrd  $2, 8, %xmm0
+- movdqa  %xmm0, %xmm1
+- pblendw $170, LCPI0_0(%rip), %xmm1 ## xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]
+- psrld $16, %xmm0
+- pblendw $170, LCPI0_1(%rip), %xmm0 ## xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+- addps LCPI0_2(%rip), %xmm0
+- addps %xmm1, %xmm0
++ movl  0, %eax
++ movl  4, %ecx
++ xorps %xmm0, %xmm0
++ cvtsi2ssq %rax, %xmm0
++ xorps %xmm1, %xmm1
++ cvtsi2ssq %rcx, %xmm1
++ movl  8, %eax
++ xorps %xmm2, %xmm2
++ cvtsi2ssq %rax, %xmm2
++ insertps  $16, %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
++ insertps  $32, %xmm2, %xmm0 ## xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+  movaps  %xmm0, 0
+ LBB0_1:                                 ## %bb4
+                                         ## =>This Inner Loop Header: Depth=1
+  xorl  %eax, %eax
+  callq _xxGetOffsetForCode
+  xorl  %esi, %esi
+  xorl  %eax, %eax
+  movq  %rbx, %rdi
+  callq _xxCalculateMidType
+  cmpl  $1, %eax
+  jne LBB0_1
+ ## BB#2:                                ## %bb26
+                                         ##   in Loop: Header=BB0_1 Depth=1
+  cmpq  $1048576, %r14          ## imm = 0x100000
+  jne LBB0_1